2021-02-16 07:10:22 +00:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2021-02-20 06:30:13 +00:00
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#include "shader_recompiler/frontend/ir/microinstruction.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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2021-02-16 07:10:22 +00:00
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#include "shader_recompiler/frontend/ir/program.h"
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#include "shader_recompiler/shader_info.h"
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namespace Shader::Optimization {
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namespace {
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2021-02-20 06:30:13 +00:00
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void AddConstantBufferDescriptor(Info& info, u32 index, u32 count) {
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if (count != 1) {
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throw NotImplementedException("Constant buffer descriptor indexing");
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}
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if ((info.constant_buffer_mask & (1U << index)) != 0) {
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2021-02-16 07:10:22 +00:00
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return;
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}
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2021-02-20 06:30:13 +00:00
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info.constant_buffer_mask |= 1U << index;
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info.constant_buffer_descriptors.push_back({
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2021-02-16 07:10:22 +00:00
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.index{index},
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.count{1},
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});
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}
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2021-02-20 06:30:13 +00:00
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void VisitUsages(Info& info, IR::Inst& inst) {
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2021-02-16 07:10:22 +00:00
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switch (inst.Opcode()) {
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2021-02-19 21:10:18 +00:00
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case IR::Opcode::CompositeConstructF16x2:
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case IR::Opcode::CompositeConstructF16x3:
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case IR::Opcode::CompositeConstructF16x4:
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case IR::Opcode::CompositeExtractF16x2:
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case IR::Opcode::CompositeExtractF16x3:
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case IR::Opcode::CompositeExtractF16x4:
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2021-03-09 20:14:57 +00:00
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case IR::Opcode::SelectF16:
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2021-02-19 21:10:18 +00:00
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::PackFloat2x16:
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case IR::Opcode::UnpackFloat2x16:
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case IR::Opcode::ConvertS16F16:
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case IR::Opcode::ConvertS32F16:
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case IR::Opcode::ConvertS64F16:
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case IR::Opcode::ConvertU16F16:
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case IR::Opcode::ConvertU32F16:
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case IR::Opcode::ConvertU64F16:
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2021-02-16 07:10:22 +00:00
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case IR::Opcode::FPAbs16:
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case IR::Opcode::FPAdd16:
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case IR::Opcode::FPCeil16:
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case IR::Opcode::FPFloor16:
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case IR::Opcode::FPFma16:
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case IR::Opcode::FPMul16:
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case IR::Opcode::FPNeg16:
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case IR::Opcode::FPRoundEven16:
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case IR::Opcode::FPSaturate16:
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case IR::Opcode::FPTrunc16:
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2021-02-19 21:10:18 +00:00
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info.uses_fp16 = true;
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2021-02-16 07:10:22 +00:00
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break;
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case IR::Opcode::FPAbs64:
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case IR::Opcode::FPAdd64:
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case IR::Opcode::FPCeil64:
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case IR::Opcode::FPFloor64:
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case IR::Opcode::FPFma64:
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case IR::Opcode::FPMax64:
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case IR::Opcode::FPMin64:
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case IR::Opcode::FPMul64:
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case IR::Opcode::FPNeg64:
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case IR::Opcode::FPRecip64:
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case IR::Opcode::FPRecipSqrt64:
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case IR::Opcode::FPRoundEven64:
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case IR::Opcode::FPSaturate64:
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case IR::Opcode::FPTrunc64:
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info.uses_fp64 = true;
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break;
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2021-03-09 20:14:57 +00:00
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default:
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break;
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}
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switch (inst.Opcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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case IR::Opcode::UndefU8:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::LoadStorageU8:
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case IR::Opcode::LoadStorageS8:
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case IR::Opcode::WriteStorageU8:
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case IR::Opcode::WriteStorageS8:
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case IR::Opcode::SelectU8:
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info.uses_int8 = true;
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break;
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default:
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break;
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}
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switch (inst.Opcode()) {
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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case IR::Opcode::UndefU16:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::LoadStorageU16:
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case IR::Opcode::LoadStorageS16:
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case IR::Opcode::WriteStorageU16:
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case IR::Opcode::WriteStorageS16:
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case IR::Opcode::SelectU16:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::ConvertS16F16:
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case IR::Opcode::ConvertS16F32:
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case IR::Opcode::ConvertS16F64:
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case IR::Opcode::ConvertU16F16:
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case IR::Opcode::ConvertU16F32:
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case IR::Opcode::ConvertU16F64:
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info.uses_int16 = true;
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break;
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default:
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break;
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}
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switch (inst.Opcode()) {
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case IR::Opcode::GetCbufU64:
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case IR::Opcode::UndefU64:
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case IR::Opcode::LoadGlobalU8:
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case IR::Opcode::LoadGlobalS8:
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case IR::Opcode::LoadGlobalU16:
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case IR::Opcode::LoadGlobalS16:
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case IR::Opcode::LoadGlobal32:
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case IR::Opcode::LoadGlobal64:
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case IR::Opcode::LoadGlobal128:
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case IR::Opcode::WriteGlobalU8:
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case IR::Opcode::WriteGlobalS8:
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case IR::Opcode::WriteGlobalU16:
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case IR::Opcode::WriteGlobalS16:
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case IR::Opcode::WriteGlobal32:
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case IR::Opcode::WriteGlobal64:
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case IR::Opcode::WriteGlobal128:
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case IR::Opcode::SelectU64:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF64U64:
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case IR::Opcode::PackUint2x32:
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case IR::Opcode::UnpackUint2x32:
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case IR::Opcode::IAdd64:
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case IR::Opcode::ISub64:
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case IR::Opcode::INeg64:
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case IR::Opcode::ShiftLeftLogical64:
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case IR::Opcode::ShiftRightLogical64:
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case IR::Opcode::ShiftRightArithmetic64:
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case IR::Opcode::ConvertS64F16:
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case IR::Opcode::ConvertS64F32:
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case IR::Opcode::ConvertS64F64:
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case IR::Opcode::ConvertU64F16:
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case IR::Opcode::ConvertU64F32:
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case IR::Opcode::ConvertU64F64:
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case IR::Opcode::ConvertU64U32:
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case IR::Opcode::ConvertU32U64:
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case IR::Opcode::ConvertF16U64:
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case IR::Opcode::ConvertF32U64:
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case IR::Opcode::ConvertF64U64:
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info.uses_int64 = true;
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break;
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default:
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break;
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}
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switch (inst.Opcode()) {
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case IR::Opcode::WorkgroupId:
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info.uses_workgroup_id = true;
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break;
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case IR::Opcode::LocalInvocationId:
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info.uses_local_invocation_id = true;
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break;
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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case IR::Opcode::GetCbufU32:
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case IR::Opcode::GetCbufF32:
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case IR::Opcode::GetCbufU64: {
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2021-02-16 07:10:22 +00:00
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if (const IR::Value index{inst.Arg(0)}; index.IsImmediate()) {
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2021-02-20 06:30:13 +00:00
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AddConstantBufferDescriptor(info, index.U32(), 1);
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2021-02-16 07:10:22 +00:00
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} else {
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throw NotImplementedException("Constant buffer with non-immediate index");
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}
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2021-03-09 20:14:57 +00:00
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switch (inst.Opcode()) {
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case IR::Opcode::GetCbufU8:
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case IR::Opcode::GetCbufS8:
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info.used_constant_buffer_types |= IR::Type::U8;
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break;
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case IR::Opcode::GetCbufU16:
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case IR::Opcode::GetCbufS16:
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info.used_constant_buffer_types |= IR::Type::U16;
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break;
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case IR::Opcode::GetCbufU32:
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info.used_constant_buffer_types |= IR::Type::U32;
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break;
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case IR::Opcode::GetCbufF32:
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info.used_constant_buffer_types |= IR::Type::F32;
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break;
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case IR::Opcode::GetCbufU64:
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info.used_constant_buffer_types |= IR::Type::U64;
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break;
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default:
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break;
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}
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2021-02-16 07:10:22 +00:00
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break;
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2021-03-09 20:14:57 +00:00
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}
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2021-03-08 21:31:53 +00:00
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case IR::Opcode::BindlessImageSampleImplicitLod:
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case IR::Opcode::BindlessImageSampleExplicitLod:
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case IR::Opcode::BindlessImageSampleDrefImplicitLod:
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case IR::Opcode::BindlessImageSampleDrefExplicitLod:
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case IR::Opcode::BoundImageSampleImplicitLod:
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case IR::Opcode::BoundImageSampleExplicitLod:
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case IR::Opcode::BoundImageSampleDrefImplicitLod:
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case IR::Opcode::BoundImageSampleDrefExplicitLod:
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case IR::Opcode::ImageSampleImplicitLod:
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case IR::Opcode::ImageSampleExplicitLod:
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case IR::Opcode::ImageSampleDrefImplicitLod:
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case IR::Opcode::ImageSampleDrefExplicitLod: {
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const TextureType type{inst.Flags<IR::TextureInstInfo>().type};
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info.uses_sampled_1d |= type == TextureType::Color1D || type == TextureType::ColorArray1D ||
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type == TextureType::Shadow1D || type == TextureType::ShadowArray1D;
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info.uses_sparse_residency |=
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp) != nullptr;
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break;
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}
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2021-02-16 07:10:22 +00:00
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default:
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break;
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}
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}
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2021-02-20 06:30:13 +00:00
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void VisitFpModifiers(Info& info, IR::Inst& inst) {
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switch (inst.Opcode()) {
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case IR::Opcode::FPAdd16:
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case IR::Opcode::FPFma16:
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case IR::Opcode::FPMul16:
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case IR::Opcode::FPRoundEven16:
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case IR::Opcode::FPFloor16:
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case IR::Opcode::FPCeil16:
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case IR::Opcode::FPTrunc16: {
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const auto control{inst.Flags<IR::FpControl>()};
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switch (control.fmz_mode) {
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case IR::FmzMode::DontCare:
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break;
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case IR::FmzMode::FTZ:
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case IR::FmzMode::FMZ:
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info.uses_fp16_denorms_flush = true;
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break;
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case IR::FmzMode::None:
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info.uses_fp16_denorms_preserve = true;
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break;
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}
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break;
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}
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case IR::Opcode::FPAdd32:
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case IR::Opcode::FPFma32:
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case IR::Opcode::FPMul32:
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case IR::Opcode::FPRoundEven32:
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case IR::Opcode::FPFloor32:
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case IR::Opcode::FPCeil32:
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2021-03-11 03:42:17 +00:00
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case IR::Opcode::FPTrunc32:
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case IR::Opcode::FPOrdEqual32:
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case IR::Opcode::FPUnordEqual32:
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case IR::Opcode::FPOrdNotEqual32:
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case IR::Opcode::FPUnordNotEqual32:
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case IR::Opcode::FPOrdLessThan32:
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case IR::Opcode::FPUnordLessThan32:
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case IR::Opcode::FPOrdGreaterThan32:
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case IR::Opcode::FPUnordGreaterThan32:
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case IR::Opcode::FPOrdLessThanEqual32:
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case IR::Opcode::FPUnordLessThanEqual32:
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case IR::Opcode::FPOrdGreaterThanEqual32:
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case IR::Opcode::FPUnordGreaterThanEqual32: {
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2021-02-20 06:30:13 +00:00
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const auto control{inst.Flags<IR::FpControl>()};
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switch (control.fmz_mode) {
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case IR::FmzMode::DontCare:
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break;
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case IR::FmzMode::FTZ:
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case IR::FmzMode::FMZ:
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info.uses_fp32_denorms_flush = true;
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break;
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case IR::FmzMode::None:
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info.uses_fp32_denorms_preserve = true;
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break;
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}
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break;
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}
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default:
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break;
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}
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}
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void Visit(Info& info, IR::Inst& inst) {
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VisitUsages(info, inst);
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VisitFpModifiers(info, inst);
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}
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2021-02-16 07:10:22 +00:00
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} // Anonymous namespace
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void CollectShaderInfoPass(IR::Program& program) {
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Info& info{program.info};
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2021-03-14 06:41:05 +00:00
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for (IR::Block* const block : program.post_order_blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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Visit(info, inst);
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2021-02-16 07:10:22 +00:00
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}
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}
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}
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} // namespace Shader::Optimization
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