artemist/play
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

i made my own pac for some reason

Browse source
This commit is contained in:
Artemis Tosini 2024-03-25 06:06:51 +00:00
parent 44687b0067
commit 97c416c456
Signed by: artemist
GPG key ID: EE5227935FE3FF18
200 changed files with 39004 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
rust-embedded/lpc1114-test/src/main.rs
View file

@ -10,16 +10,16 @@ fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap();
// SAFETY: yes... ha ha ha... YES
let gpio0 = unsafe { &(*lpc11xx::GPIO0::ptr()) };
let gpio0 = unsafe { &(*lpc111x_pac::Gpio0::ptr()) };
gpio0.dir.write(|w| w.dir7().output());
gpio0.dir().write(|w| w.io7().bit(true));
let mut delay = cortex_m::delay::Delay::new(cp.SYST, 12_000_000);
loop {
gpio0.data.write(|w| w.data7().high());
gpio0.data().write(|w| w.data7().bit(true));
delay.delay_ms(500);
gpio0.data.write(|w| w.data7().low());
gpio0.data().write(|w| w.data7().bit(false));
delay.delay_ms(500);
}
}

4
rust-embedded/lpc111x-pac/generate.sh
View file

@ -3,6 +3,10 @@
set -euo pipefail
svdtools patch svd/LPC111x.yaml
# Hard to do this in svdtools, easy in sed
sed -E -i 's#<name>(ENUM|test)</name>##' svd/LPC111x.svd.patched
svd2rust -i svd/LPC111x.svd.patched
rm -r src
form -i lib.rs -o src

73
rust-embedded/lpc111x-pac/src/adc.rs Normal file
View file

@ -0,0 +1,73 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cr: Cr,
gdr: Gdr,
_reserved2: [u8; 0x04],
inten: Inten,
dr: [Dr; 8],
stat: Stat,
}
impl RegisterBlock {
#[doc = "0x00 - A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
#[inline(always)]
pub const fn cr(&self) -> &Cr {
&self.cr
}
#[doc = "0x04 - A/D Global Data Register. Contains the result of the most recent A/D conversion."]
#[inline(always)]
pub const fn gdr(&self) -> &Gdr {
&self.gdr
}
#[doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
#[inline(always)]
pub const fn inten(&self) -> &Inten {
&self.inten
}
#[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
#[inline(always)]
pub const fn dr(&self, n: usize) -> &Dr {
&self.dr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
#[inline(always)]
pub fn dr_iter(&self) -> impl Iterator<Item = &Dr> {
self.dr.iter()
}
#[doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
#[inline(always)]
pub const fn stat(&self) -> &Stat {
&self.stat
}
}
#[doc = "CR (rw) register accessor: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
pub mod cr;
#[doc = "GDR (rw) register accessor: A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdr`]
module"]
#[doc(alias = "GDR")]
pub type Gdr = crate::Reg<gdr::GdrSpec>;
#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion."]
pub mod gdr;
#[doc = "STAT (r) register accessor: A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
#[doc(alias = "STAT")]
pub type Stat = crate::Reg<stat::StatSpec>;
#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
pub mod stat;
#[doc = "INTEN (rw) register accessor: A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
#[doc(alias = "INTEN")]
pub type Inten = crate::Reg<inten::IntenSpec>;
#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
pub mod inten;
#[doc = "DR (rw) register accessor: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
module"]
#[doc(alias = "DR")]
pub type Dr = crate::Reg<dr::DrSpec>;
#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
pub mod dr;

479
rust-embedded/lpc111x-pac/src/adc/cr.rs Normal file
View file

@ -0,0 +1,479 @@
#[doc = "Register `CR` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Register `CR` writer"]
pub type W = crate::W<CrSpec>;
#[doc = "Field `SEL` reader - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
pub type SelR = crate::FieldReader;
#[doc = "Field `SEL` writer - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `CLKDIV` reader - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
pub type ClkdivR = crate::FieldReader;
#[doc = "Field `CLKDIV` writer - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
pub type ClkdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Burst mode\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Burst {
#[doc = "0: Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
Swmode = 0,
#[doc = "1: Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
Hwmode = 1,
}
impl From<Burst> for bool {
#[inline(always)]
fn from(variant: Burst) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `BURST` reader - Burst mode"]
pub type BurstR = crate::BitReader<Burst>;
impl BurstR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Burst {
match self.bits {
false => Burst::Swmode,
true => Burst::Hwmode,
}
}
#[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
#[inline(always)]
pub fn is_swmode(&self) -> bool {
*self == Burst::Swmode
}
#[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
#[inline(always)]
pub fn is_hwmode(&self) -> bool {
*self == Burst::Hwmode
}
}
#[doc = "Field `BURST` writer - Burst mode"]
pub type BurstW<'a, REG> = crate::BitWriter<'a, REG, Burst>;
impl<'a, REG> BurstW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
#[inline(always)]
pub fn swmode(self) -> &'a mut crate::W<REG> {
self.variant(Burst::Swmode)
}
#[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
#[inline(always)]
pub fn hwmode(self) -> &'a mut crate::W<REG> {
self.variant(Burst::Hwmode)
}
}
#[doc = "This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Clks {
#[doc = "0: 11 clocks / 10 bits"]
_10bit = 0,
#[doc = "1: 10 clocks / 9 bits"]
_9bit = 1,
#[doc = "2: 9 clocks / 8 bits"]
_8bit = 2,
#[doc = "3: 8 clocks / 7 bits"]
_7bit = 3,
#[doc = "4: 7 clocks / 6 bits"]
_6bit = 4,
#[doc = "5: 6 clocks / 5 bits"]
_5bit = 5,
#[doc = "6: 5 clocks / 4 bits"]
_4bit = 6,
#[doc = "7: 4 clocks / 3 bits"]
_3bit = 7,
}
impl From<Clks> for u8 {
#[inline(always)]
fn from(variant: Clks) -> Self {
variant as _
}
}
impl crate::FieldSpec for Clks {
type Ux = u8;
}
#[doc = "Field `CLKS` reader - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
pub type ClksR = crate::FieldReader<Clks>;
impl ClksR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Clks {
match self.bits {
0 => Clks::_10bit,
1 => Clks::_9bit,
2 => Clks::_8bit,
3 => Clks::_7bit,
4 => Clks::_6bit,
5 => Clks::_5bit,
6 => Clks::_4bit,
7 => Clks::_3bit,
_ => unreachable!(),
}
}
#[doc = "11 clocks / 10 bits"]
#[inline(always)]
pub fn is_10bit(&self) -> bool {
*self == Clks::_10bit
}
#[doc = "10 clocks / 9 bits"]
#[inline(always)]
pub fn is_9bit(&self) -> bool {
*self == Clks::_9bit
}
#[doc = "9 clocks / 8 bits"]
#[inline(always)]
pub fn is_8bit(&self) -> bool {
*self == Clks::_8bit
}
#[doc = "8 clocks / 7 bits"]
#[inline(always)]
pub fn is_7bit(&self) -> bool {
*self == Clks::_7bit
}
#[doc = "7 clocks / 6 bits"]
#[inline(always)]
pub fn is_6bit(&self) -> bool {
*self == Clks::_6bit
}
#[doc = "6 clocks / 5 bits"]
#[inline(always)]
pub fn is_5bit(&self) -> bool {
*self == Clks::_5bit
}
#[doc = "5 clocks / 4 bits"]
#[inline(always)]
pub fn is_4bit(&self) -> bool {
*self == Clks::_4bit
}
#[doc = "4 clocks / 3 bits"]
#[inline(always)]
pub fn is_3bit(&self) -> bool {
*self == Clks::_3bit
}
}
#[doc = "Field `CLKS` writer - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
pub type ClksW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Clks>;
impl<'a, REG> ClksW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "11 clocks / 10 bits"]
#[inline(always)]
pub fn _10bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_10bit)
}
#[doc = "10 clocks / 9 bits"]
#[inline(always)]
pub fn _9bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_9bit)
}
#[doc = "9 clocks / 8 bits"]
#[inline(always)]
pub fn _8bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_8bit)
}
#[doc = "8 clocks / 7 bits"]
#[inline(always)]
pub fn _7bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_7bit)
}
#[doc = "7 clocks / 6 bits"]
#[inline(always)]
pub fn _6bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_6bit)
}
#[doc = "6 clocks / 5 bits"]
#[inline(always)]
pub fn _5bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_5bit)
}
#[doc = "5 clocks / 4 bits"]
#[inline(always)]
pub fn _4bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_4bit)
}
#[doc = "4 clocks / 3 bits"]
#[inline(always)]
pub fn _3bit(self) -> &'a mut crate::W<REG> {
self.variant(Clks::_3bit)
}
}
#[doc = "When the BURST bit is 0, these bits control whether and when an A/D conversion is started:\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Start {
#[doc = "0: No start (this value should be used when clearing PDN to 0)."]
Stop = 0,
#[doc = "1: Start conversion now."]
Start = 1,
#[doc = "2: Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
Edgepio0_2 = 2,
#[doc = "3: Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
Edgepio1_5 = 3,
#[doc = "4: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
Edgect32b0Mat0_1 = 4,
#[doc = "5: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
Edgect32b0Mat1_1 = 5,
#[doc = "6: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
Edgect16b0Mat0_1 = 6,
#[doc = "7: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
Edgect16b0Mat1_1 = 7,
}
impl From<Start> for u8 {
#[inline(always)]
fn from(variant: Start) -> Self {
variant as _
}
}
impl crate::FieldSpec for Start {
type Ux = u8;
}
#[doc = "Field `START` reader - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
pub type StartR = crate::FieldReader<Start>;
impl StartR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Start {
match self.bits {
0 => Start::Stop,
1 => Start::Start,
2 => Start::Edgepio0_2,
3 => Start::Edgepio1_5,
4 => Start::Edgect32b0Mat0_1,
5 => Start::Edgect32b0Mat1_1,
6 => Start::Edgect16b0Mat0_1,
7 => Start::Edgect16b0Mat1_1,
_ => unreachable!(),
}
}
#[doc = "No start (this value should be used when clearing PDN to 0)."]
#[inline(always)]
pub fn is_stop(&self) -> bool {
*self == Start::Stop
}
#[doc = "Start conversion now."]
#[inline(always)]
pub fn is_start(&self) -> bool {
*self == Start::Start
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
#[inline(always)]
pub fn is_edgepio0_2(&self) -> bool {
*self == Start::Edgepio0_2
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
#[inline(always)]
pub fn is_edgepio1_5(&self) -> bool {
*self == Start::Edgepio1_5
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
#[inline(always)]
pub fn is_edgect32b0_mat0_1(&self) -> bool {
*self == Start::Edgect32b0Mat0_1
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
#[inline(always)]
pub fn is_edgect32b0_mat1_1(&self) -> bool {
*self == Start::Edgect32b0Mat1_1
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
#[inline(always)]
pub fn is_edgect16b0_mat0_1(&self) -> bool {
*self == Start::Edgect16b0Mat0_1
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
#[inline(always)]
pub fn is_edgect16b0_mat1_1(&self) -> bool {
*self == Start::Edgect16b0Mat1_1
}
}
#[doc = "Field `START` writer - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
pub type StartW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Start>;
impl<'a, REG> StartW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "No start (this value should be used when clearing PDN to 0)."]
#[inline(always)]
pub fn stop(self) -> &'a mut crate::W<REG> {
self.variant(Start::Stop)
}
#[doc = "Start conversion now."]
#[inline(always)]
pub fn start(self) -> &'a mut crate::W<REG> {
self.variant(Start::Start)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
#[inline(always)]
pub fn edgepio0_2(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgepio0_2)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
#[inline(always)]
pub fn edgepio1_5(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgepio1_5)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
#[inline(always)]
pub fn edgect32b0_mat0_1(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgect32b0Mat0_1)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
#[inline(always)]
pub fn edgect32b0_mat1_1(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgect32b0Mat1_1)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
#[inline(always)]
pub fn edgect16b0_mat0_1(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgect16b0Mat0_1)
}
#[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
#[inline(always)]
pub fn edgect16b0_mat1_1(self) -> &'a mut crate::W<REG> {
self.variant(Start::Edgect16b0Mat1_1)
}
}
#[doc = "This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Edge {
#[doc = "0: Start conversion on a rising edge on the selected CAP/MAT signal."]
Rising = 0,
#[doc = "1: Start conversion on a rising edge on the selected CAP/MAT signal."]
Falling = 1,
}
impl From<Edge> for bool {
#[inline(always)]
fn from(variant: Edge) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `EDGE` reader - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
pub type EdgeR = crate::BitReader<Edge>;
impl EdgeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Edge {
match self.bits {
false => Edge::Rising,
true => Edge::Falling,
}
}
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
#[inline(always)]
pub fn is_rising(&self) -> bool {
*self == Edge::Rising
}
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
#[inline(always)]
pub fn is_falling(&self) -> bool {
*self == Edge::Falling
}
}
#[doc = "Field `EDGE` writer - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
pub type EdgeW<'a, REG> = crate::BitWriter<'a, REG, Edge>;
impl<'a, REG> EdgeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
#[inline(always)]
pub fn rising(self) -> &'a mut crate::W<REG> {
self.variant(Edge::Rising)
}
#[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
#[inline(always)]
pub fn falling(self) -> &'a mut crate::W<REG> {
self.variant(Edge::Falling)
}
}
impl R {
#[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
#[inline(always)]
pub fn sel(&self) -> SelR {
SelR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
#[inline(always)]
pub fn clkdiv(&self) -> ClkdivR {
ClkdivR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bit 16 - Burst mode"]
#[inline(always)]
pub fn burst(&self) -> BurstR {
BurstR::new(((self.bits >> 16) & 1) != 0)
}
#[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
#[inline(always)]
pub fn clks(&self) -> ClksR {
ClksR::new(((self.bits >> 17) & 7) as u8)
}
#[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(((self.bits >> 24) & 7) as u8)
}
#[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
#[inline(always)]
pub fn edge(&self) -> EdgeR {
EdgeR::new(((self.bits >> 27) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
#[inline(always)]
#[must_use]
pub fn sel(&mut self) -> SelW<CrSpec> {
SelW::new(self, 0)
}
#[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
#[inline(always)]
#[must_use]
pub fn clkdiv(&mut self) -> ClkdivW<CrSpec> {
ClkdivW::new(self, 8)
}
#[doc = "Bit 16 - Burst mode"]
#[inline(always)]
#[must_use]
pub fn burst(&mut self) -> BurstW<CrSpec> {
BurstW::new(self, 16)
}
#[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
#[inline(always)]
#[must_use]
pub fn clks(&mut self) -> ClksW<CrSpec> {
ClksW::new(self, 17)
}
#[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<CrSpec> {
StartW::new(self, 24)
}
#[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
#[inline(always)]
#[must_use]
pub fn edge(&mut self) -> EdgeW<CrSpec> {
EdgeW::new(self, 27)
}
}
#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
impl crate::Writable for CrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CR to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}

70
rust-embedded/lpc111x-pac/src/adc/dr.rs Normal file
View file

@ -0,0 +1,70 @@
#[doc = "Register `DR%s` reader"]
pub type R = crate::R<DrSpec>;
#[doc = "Register `DR%s` writer"]
pub type W = crate::W<DrSpec>;
#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
pub type VVrefR = crate::FieldReader<u16>;
#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
pub type OverrunR = crate::BitReader;
#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
#[inline(always)]
pub fn v_vref(&self) -> VVrefR {
VVrefR::new(((self.bits >> 6) & 0x03ff) as u16)
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
#[inline(always)]
pub fn overrun(&self) -> OverrunR {
OverrunR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
#[inline(always)]
#[must_use]
pub fn v_vref(&mut self) -> VVrefW<DrSpec> {
VVrefW::new(self, 6)
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
#[inline(always)]
#[must_use]
pub fn overrun(&mut self) -> OverrunW<DrSpec> {
OverrunW::new(self, 30)
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<DrSpec> {
DoneW::new(self, 31)
}
}
#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DrSpec;
impl crate::RegisterSpec for DrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
impl crate::Readable for DrSpec {}
#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
impl crate::Writable for DrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DR%s to value 0"]
impl crate::Resettable for DrSpec {
const RESET_VALUE: u32 = 0;
}

85
rust-embedded/lpc111x-pac/src/adc/gdr.rs Normal file
View file

@ -0,0 +1,85 @@
#[doc = "Register `GDR` reader"]
pub type R = crate::R<GdrSpec>;
#[doc = "Register `GDR` writer"]
pub type W = crate::W<GdrSpec>;
#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
pub type VVrefR = crate::FieldReader<u16>;
#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
#[doc = "Field `CHN` reader - These bits contain the channel from which the result bits V_VREF were converted."]
pub type ChnR = crate::FieldReader;
#[doc = "Field `CHN` writer - These bits contain the channel from which the result bits V_VREF were converted."]
pub type ChnW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
pub type OverrunR = crate::BitReader;
#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
pub type DoneR = crate::BitReader;
#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
#[inline(always)]
pub fn v_vref(&self) -> VVrefR {
VVrefR::new(((self.bits >> 6) & 0x03ff) as u16)
}
#[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."]
#[inline(always)]
pub fn chn(&self) -> ChnR {
ChnR::new(((self.bits >> 24) & 7) as u8)
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
#[inline(always)]
pub fn overrun(&self) -> OverrunR {
OverrunR::new(((self.bits >> 30) & 1) != 0)
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new(((self.bits >> 31) & 1) != 0)
}
}
impl W {
#[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
#[inline(always)]
#[must_use]
pub fn v_vref(&mut self) -> VVrefW<GdrSpec> {
VVrefW::new(self, 6)
}
#[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."]
#[inline(always)]
#[must_use]
pub fn chn(&mut self) -> ChnW<GdrSpec> {
ChnW::new(self, 24)
}
#[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
#[inline(always)]
#[must_use]
pub fn overrun(&mut self) -> OverrunW<GdrSpec> {
OverrunW::new(self, 30)
}
#[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
#[inline(always)]
#[must_use]
pub fn done(&mut self) -> DoneW<GdrSpec> {
DoneW::new(self, 31)
}
}
#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GdrSpec;
impl crate::RegisterSpec for GdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`gdr::R`](R) reader structure"]
impl crate::Readable for GdrSpec {}
#[doc = "`write(|w| ..)` method takes [`gdr::W`](W) writer structure"]
impl crate::Writable for GdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets GDR to value 0"]
impl crate::Resettable for GdrSpec {
const RESET_VALUE: u32 = 0;
}

55
rust-embedded/lpc111x-pac/src/adc/inten.rs Normal file
View file

@ -0,0 +1,55 @@
#[doc = "Register `INTEN` reader"]
pub type R = crate::R<IntenSpec>;
#[doc = "Register `INTEN` writer"]
pub type W = crate::W<IntenSpec>;
#[doc = "Field `ADINTENn` reader - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
pub type AdintennR = crate::FieldReader;
#[doc = "Field `ADINTENn` writer - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
pub type AdintennW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
#[doc = "Field `ADGINTEN` reader - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
pub type AdgintenR = crate::BitReader;
#[doc = "Field `ADGINTEN` writer - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
pub type AdgintenW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
#[inline(always)]
pub fn adintenn(&self) -> AdintennR {
AdintennR::new((self.bits & 0xff) as u8)
}
#[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
#[inline(always)]
pub fn adginten(&self) -> AdgintenR {
AdgintenR::new(((self.bits >> 8) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
#[inline(always)]
#[must_use]
pub fn adintenn(&mut self) -> AdintennW<IntenSpec> {
AdintennW::new(self, 0)
}
#[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
#[inline(always)]
#[must_use]
pub fn adginten(&mut self) -> AdgintenW<IntenSpec> {
AdgintenW::new(self, 8)
}
}
#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntenSpec;
impl crate::RegisterSpec for IntenSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`inten::R`](R) reader structure"]
impl crate::Readable for IntenSpec {}
#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
impl crate::Writable for IntenSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets INTEN to value 0x0100"]
impl crate::Resettable for IntenSpec {
const RESET_VALUE: u32 = 0x0100;
}

36
rust-embedded/lpc111x-pac/src/adc/stat.rs Normal file
View file

@ -0,0 +1,36 @@
#[doc = "Register `STAT` reader"]
pub type R = crate::R<StatSpec>;
#[doc = "Field `DONE` reader - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."]
pub type DoneR = crate::FieldReader;
#[doc = "Field `OVERRUN` reader - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."]
pub type OverrunR = crate::FieldReader;
#[doc = "Field `ADINT` reader - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
pub type AdintR = crate::BitReader;
impl R {
#[doc = "Bits 0:7 - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."]
#[inline(always)]
pub fn done(&self) -> DoneR {
DoneR::new((self.bits & 0xff) as u8)
}
#[doc = "Bits 8:15 - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."]
#[inline(always)]
pub fn overrun(&self) -> OverrunR {
OverrunR::new(((self.bits >> 8) & 0xff) as u8)
}
#[doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
#[inline(always)]
pub fn adint(&self) -> AdintR {
AdintR::new(((self.bits >> 16) & 1) != 0)
}
}
#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatSpec;
impl crate::RegisterSpec for StatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate::Readable for StatSpec {}
#[doc = "`reset()` method sets STAT to value 0"]
impl crate::Resettable for StatSpec {
const RESET_VALUE: u32 = 0;
}

164
rust-embedded/lpc111x-pac/src/ct16b0.rs Normal file
View file

@ -0,0 +1,164 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ir: Ir,
tcr: Tcr,
tc: Tc,
pr: Pr,
pc: Pc,
mcr: Mcr,
mr: [Mr; 4],
ccr: Ccr,
cr: [Cr; 2],
_reserved9: [u8; 0x08],
emr: Emr,
_reserved10: [u8; 0x30],
ctcr: Ctcr,
pwmc: Pwmc,
}
impl RegisterBlock {
#[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
#[inline(always)]
pub const fn ir(&self) -> &Ir {
&self.ir
}
#[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
#[inline(always)]
pub const fn tc(&self) -> &Tc {
&self.tc
}
#[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
#[inline(always)]
pub const fn pr(&self) -> &Pr {
&self.pr
}
#[doc = "0x10 - Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
#[inline(always)]
pub const fn pc(&self) -> &Pc {
&self.pc
}
#[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
#[inline(always)]
pub const fn mcr(&self) -> &Mcr {
&self.mcr
}
#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
#[inline(always)]
pub const fn mr(&self, n: usize) -> &Mr {
&self.mr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
#[inline(always)]
pub fn mr_iter(&self) -> impl Iterator<Item = &Mr> {
self.mr.iter()
}
#[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
#[inline(always)]
pub const fn ccr(&self) -> &Ccr {
&self.ccr
}
#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
#[inline(always)]
pub const fn cr(&self, n: usize) -> &Cr {
&self.cr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
#[inline(always)]
pub fn cr_iter(&self) -> impl Iterator<Item = &Cr> {
self.cr.iter()
}
#[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."]
#[inline(always)]
pub const fn emr(&self) -> &Emr {
&self.emr
}
#[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
#[inline(always)]
pub const fn ctcr(&self) -> &Ctcr {
&self.ctcr
}
#[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."]
#[inline(always)]
pub const fn pwmc(&self) -> &Pwmc {
&self.pwmc
}
}
#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
module"]
#[doc(alias = "IR")]
pub type Ir = crate::Reg<ir::IrSpec>;
#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
pub mod ir;
#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub mod tcr;
#[doc = "TC (rw) register accessor: Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`]
module"]
#[doc(alias = "TC")]
pub type Tc = crate::Reg<tc::TcSpec>;
#[doc = "Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub mod tc;
#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`]
module"]
#[doc(alias = "PR")]
pub type Pr = crate::Reg<pr::PrSpec>;
#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
pub mod pr;
#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`]
module"]
#[doc(alias = "PC")]
pub type Pc = crate::Reg<pc::PcSpec>;
#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
pub mod pc;
#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
module"]
#[doc(alias = "MCR")]
pub type Mcr = crate::Reg<mcr::McrSpec>;
#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
pub mod mcr;
#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`]
module"]
#[doc(alias = "MR")]
pub type Mr = crate::Reg<mr::MrSpec>;
#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
pub mod mr;
#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
module"]
#[doc(alias = "CCR")]
pub type Ccr = crate::Reg<ccr::CcrSpec>;
#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub mod ccr;
#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
pub mod cr;
#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
module"]
#[doc(alias = "EMR")]
pub type Emr = crate::Reg<emr::EmrSpec>;
#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."]
pub mod emr;
#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`]
module"]
#[doc(alias = "CTCR")]
pub type Ctcr = crate::Reg<ctcr::CtcrSpec>;
#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub mod ctcr;
#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`]
module"]
#[doc(alias = "PWMC")]
pub type Pwmc = crate::Reg<pwmc::PwmcSpec>;
#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."]
pub mod pwmc;

409
rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs Normal file
View file

@ -0,0 +1,409 @@
#[doc = "Register `CCR` reader"]
pub type R = crate::R<CcrSpec>;
#[doc = "Register `CCR` writer"]
pub type W = crate::W<CcrSpec>;
#[doc = "Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0re {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0re> for bool {
#[inline(always)]
fn from(variant: Cap0re) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0RE` reader - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0reR = crate::BitReader<Cap0re>;
impl Cap0reR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0re {
match self.bits {
true => Cap0re::Enabled,
false => Cap0re::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0re::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0re::Disabled
}
}
#[doc = "Field `CAP0RE` writer - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>;
impl<'a, REG> Cap0reW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0re::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0re::Disabled)
}
}
#[doc = "Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0fe {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0fe> for bool {
#[inline(always)]
fn from(variant: Cap0fe) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0FE` reader - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0feR = crate::BitReader<Cap0fe>;
impl Cap0feR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0fe {
match self.bits {
true => Cap0fe::Enabled,
false => Cap0fe::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0fe::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0fe::Disabled
}
}
#[doc = "Field `CAP0FE` writer - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>;
impl<'a, REG> Cap0feW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0fe::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0fe::Disabled)
}
}
#[doc = "Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0i> for bool {
#[inline(always)]
fn from(variant: Cap0i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0I` reader - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
pub type Cap0iR = crate::BitReader<Cap0i>;
impl Cap0iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0i {
match self.bits {
true => Cap0i::Enabled,
false => Cap0i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0i::Disabled
}
}
#[doc = "Field `CAP0I` writer - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>;
impl<'a, REG> Cap0iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0i::Disabled)
}
}
#[doc = "Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1re {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1re> for bool {
#[inline(always)]
fn from(variant: Cap1re) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1RE` reader - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1reR = crate::BitReader<Cap1re>;
impl Cap1reR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1re {
match self.bits {
true => Cap1re::Enabled,
false => Cap1re::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1re::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1re::Disabled
}
}
#[doc = "Field `CAP1RE` writer - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>;
impl<'a, REG> Cap1reW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1re::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1re::Disabled)
}
}
#[doc = "Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1fe {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1fe> for bool {
#[inline(always)]
fn from(variant: Cap1fe) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1FE` reader - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1feR = crate::BitReader<Cap1fe>;
impl Cap1feR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1fe {
match self.bits {
true => Cap1fe::Enabled,
false => Cap1fe::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1fe::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1fe::Disabled
}
}
#[doc = "Field `CAP1FE` writer - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>;
impl<'a, REG> Cap1feW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1fe::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1fe::Disabled)
}
}
#[doc = "Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1i> for bool {
#[inline(always)]
fn from(variant: Cap1i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1I` reader - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
pub type Cap1iR = crate::BitReader<Cap1i>;
impl Cap1iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1i {
match self.bits {
true => Cap1i::Enabled,
false => Cap1i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1i::Disabled
}
}
#[doc = "Field `CAP1I` writer - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>;
impl<'a, REG> Cap1iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1i::Disabled)
}
}
impl R {
#[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap0re(&self) -> Cap0reR {
Cap0reR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap0fe(&self) -> Cap0feR {
Cap0feR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
#[inline(always)]
pub fn cap0i(&self) -> Cap0iR {
Cap0iR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap1re(&self) -> Cap1reR {
Cap1reR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap1fe(&self) -> Cap1feR {
Cap1feR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
#[inline(always)]
pub fn cap1i(&self) -> Cap1iR {
Cap1iR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap0re(&mut self) -> Cap0reW<CcrSpec> {
Cap0reW::new(self, 0)
}
#[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap0fe(&mut self) -> Cap0feW<CcrSpec> {
Cap0feW::new(self, 1)
}
#[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
#[inline(always)]
#[must_use]
pub fn cap0i(&mut self) -> Cap0iW<CcrSpec> {
Cap0iW::new(self, 2)
}
#[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap1re(&mut self) -> Cap1reW<CcrSpec> {
Cap1reW::new(self, 3)
}
#[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap1fe(&mut self) -> Cap1feW<CcrSpec> {
Cap1feW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
#[inline(always)]
#[must_use]
pub fn cap1i(&mut self) -> Cap1iW<CcrSpec> {
Cap1iW::new(self, 5)
}
}
#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcrSpec;
impl crate::RegisterSpec for CcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
impl crate::Readable for CcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
impl crate::Writable for CcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR to value 0"]
impl crate::Resettable for CcrSpec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/ct16b0/cr.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `CR%s` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Field `CAP` reader - Timer counter capture value."]
pub type CapR = crate::FieldReader<u16>;
impl R {
#[doc = "Bits 0:15 - Timer counter capture value."]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new((self.bits & 0xffff) as u16)
}
}
#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`reset()` method sets CR%s to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}

302
rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs Normal file
View file

@ -0,0 +1,302 @@
#[doc = "Register `CTCR` reader"]
pub type R = crate::R<CtcrSpec>;
#[doc = "Register `CTCR` writer"]
pub type W = crate::W<CtcrSpec>;
#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ctm {
#[doc = "0: Increment on every rising PCLK edge"]
Timer = 0,
#[doc = "1: Increment on rising CAP pin edge"]
CounterRising = 1,
#[doc = "2: Increment on falling CAP pin edge"]
CounterFalling = 2,
#[doc = "3: Increment on both CAP pin edges"]
CounterBoth = 3,
}
impl From<Ctm> for u8 {
#[inline(always)]
fn from(variant: Ctm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ctm {
type Ux = u8;
}
#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
pub type CtmR = crate::FieldReader<Ctm>;
impl CtmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ctm {
match self.bits {
0 => Ctm::Timer,
1 => Ctm::CounterRising,
2 => Ctm::CounterFalling,
3 => Ctm::CounterBoth,
_ => unreachable!(),
}
}
#[doc = "Increment on every rising PCLK edge"]
#[inline(always)]
pub fn is_timer(&self) -> bool {
*self == Ctm::Timer
}
#[doc = "Increment on rising CAP pin edge"]
#[inline(always)]
pub fn is_counter_rising(&self) -> bool {
*self == Ctm::CounterRising
}
#[doc = "Increment on falling CAP pin edge"]
#[inline(always)]
pub fn is_counter_falling(&self) -> bool {
*self == Ctm::CounterFalling
}
#[doc = "Increment on both CAP pin edges"]
#[inline(always)]
pub fn is_counter_both(&self) -> bool {
*self == Ctm::CounterBoth
}
}
#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
pub type CtmW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctm>;
impl<'a, REG> CtmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Increment on every rising PCLK edge"]
#[inline(always)]
pub fn timer(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::Timer)
}
#[doc = "Increment on rising CAP pin edge"]
#[inline(always)]
pub fn counter_rising(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterRising)
}
#[doc = "Increment on falling CAP pin edge"]
#[inline(always)]
pub fn counter_falling(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterFalling)
}
#[doc = "Increment on both CAP pin edges"]
#[inline(always)]
pub fn counter_both(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterBoth)
}
}
#[doc = "Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cis {
#[doc = "0: CT16Bn_CAP0"]
Ct16bnCap0 = 0,
#[doc = "1: CT16Bn_CAP1"]
Ct16bnCap1 = 1,
}
impl From<Cis> for u8 {
#[inline(always)]
fn from(variant: Cis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cis {
type Ux = u8;
}
#[doc = "Field `CIS` reader - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
pub type CisR = crate::FieldReader<Cis>;
impl CisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Cis> {
match self.bits {
0 => Some(Cis::Ct16bnCap0),
1 => Some(Cis::Ct16bnCap1),
_ => None,
}
}
#[doc = "CT16Bn_CAP0"]
#[inline(always)]
pub fn is_ct16bn_cap0(&self) -> bool {
*self == Cis::Ct16bnCap0
}
#[doc = "CT16Bn_CAP1"]
#[inline(always)]
pub fn is_ct16bn_cap1(&self) -> bool {
*self == Cis::Ct16bnCap1
}
}
#[doc = "Field `CIS` writer - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
pub type CisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cis>;
impl<'a, REG> CisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "CT16Bn_CAP0"]
#[inline(always)]
pub fn ct16bn_cap0(self) -> &'a mut crate::W<REG> {
self.variant(Cis::Ct16bnCap0)
}
#[doc = "CT16Bn_CAP1"]
#[inline(always)]
pub fn ct16bn_cap1(self) -> &'a mut crate::W<REG> {
self.variant(Cis::Ct16bnCap1)
}
}
#[doc = "Field `ENCC` reader - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
pub type EnccR = crate::BitReader;
#[doc = "Field `ENCC` writer - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Selcc {
#[doc = "0: Rising Edge of CAP0 clears the timer"]
Cap0Rising = 0,
#[doc = "1: Falling Edge of CAP0 clears the timer"]
Cap0Falling = 1,
#[doc = "2: Rising Edge of CAP1 clears the timer"]
Cap1Rising = 2,
#[doc = "3: Falling Edge of CAP1 clears the timer"]
Cap1Falling = 3,
}
impl From<Selcc> for u8 {
#[inline(always)]
fn from(variant: Selcc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Selcc {
type Ux = u8;
}
#[doc = "Field `SELCC` reader - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
pub type SelccR = crate::FieldReader<Selcc>;
impl SelccR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Selcc> {
match self.bits {
0 => Some(Selcc::Cap0Rising),
1 => Some(Selcc::Cap0Falling),
2 => Some(Selcc::Cap1Rising),
3 => Some(Selcc::Cap1Falling),
_ => None,
}
}
#[doc = "Rising Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn is_cap0_rising(&self) -> bool {
*self == Selcc::Cap0Rising
}
#[doc = "Falling Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn is_cap0_falling(&self) -> bool {
*self == Selcc::Cap0Falling
}
#[doc = "Rising Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn is_cap1_rising(&self) -> bool {
*self == Selcc::Cap1Rising
}
#[doc = "Falling Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn is_cap1_falling(&self) -> bool {
*self == Selcc::Cap1Falling
}
}
#[doc = "Field `SELCC` writer - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc>;
impl<'a, REG> SelccW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Rising Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn cap0_rising(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap0Rising)
}
#[doc = "Falling Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn cap0_falling(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap0Falling)
}
#[doc = "Rising Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn cap1_rising(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap1Rising)
}
#[doc = "Falling Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn cap1_falling(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap1Falling)
}
}
impl R {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
#[inline(always)]
pub fn ctm(&self) -> CtmR {
CtmR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
#[inline(always)]
pub fn cis(&self) -> CisR {
CisR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
#[inline(always)]
pub fn encc(&self) -> EnccR {
EnccR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
#[inline(always)]
pub fn selcc(&self) -> SelccR {
SelccR::new(((self.bits >> 5) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
#[inline(always)]
#[must_use]
pub fn ctm(&mut self) -> CtmW<CtcrSpec> {
CtmW::new(self, 0)
}
#[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
#[inline(always)]
#[must_use]
pub fn cis(&mut self) -> CisW<CtcrSpec> {
CisW::new(self, 2)
}
#[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
#[inline(always)]
#[must_use]
pub fn encc(&mut self) -> EnccW<CtcrSpec> {
EnccW::new(self, 4)
}
#[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
#[inline(always)]
#[must_use]
pub fn selcc(&mut self) -> SelccW<CtcrSpec> {
SelccW::new(self, 5)
}
}
#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtcrSpec;
impl crate::RegisterSpec for CtcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"]
impl crate::Readable for CtcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"]
impl crate::Writable for CtcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTCR to value 0"]
impl crate::Resettable for CtcrSpec {
const RESET_VALUE: u32 = 0;
}

485
rust-embedded/lpc111x-pac/src/ct16b0/emr.rs Normal file
View file

@ -0,0 +1,485 @@
#[doc = "Register `EMR` reader"]
pub type R = crate::R<EmrSpec>;
#[doc = "Register `EMR` writer"]
pub type W = crate::W<EmrSpec>;
#[doc = "Field `EM0` reader - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em0R = crate::BitReader;
#[doc = "Field `EM0` writer - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM1` reader - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em1R = crate::BitReader;
#[doc = "Field `EM1` writer - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM2` reader - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em2R = crate::BitReader;
#[doc = "Field `EM2` writer - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM3` reader - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
pub type Em3R = crate::BitReader;
#[doc = "Field `EM3` writer - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
pub type Em3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "External Match Control 0. Determines the functionality of External Match 0.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc0 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc0> for u8 {
#[inline(always)]
fn from(variant: Emc0) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc0 {
type Ux = u8;
}
#[doc = "Field `EMC0` reader - External Match Control 0. Determines the functionality of External Match 0."]
pub type Emc0R = crate::FieldReader<Emc0>;
impl Emc0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc0 {
match self.bits {
0 => Emc0::DoNothing_,
1 => Emc0::ClearTheCorrespond,
2 => Emc0::SetTheCorrespondin,
3 => Emc0::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc0::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc0::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc0::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc0::ToggleTheCorrespon
}
}
#[doc = "Field `EMC0` writer - External Match Control 0. Determines the functionality of External Match 0."]
pub type Emc0W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc0>;
impl<'a, REG> Emc0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 1. Determines the functionality of External Match 1.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc1 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc1> for u8 {
#[inline(always)]
fn from(variant: Emc1) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc1 {
type Ux = u8;
}
#[doc = "Field `EMC1` reader - External Match Control 1. Determines the functionality of External Match 1."]
pub type Emc1R = crate::FieldReader<Emc1>;
impl Emc1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc1 {
match self.bits {
0 => Emc1::DoNothing_,
1 => Emc1::ClearTheCorrespond,
2 => Emc1::SetTheCorrespondin,
3 => Emc1::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc1::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc1::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc1::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc1::ToggleTheCorrespon
}
}
#[doc = "Field `EMC1` writer - External Match Control 1. Determines the functionality of External Match 1."]
pub type Emc1W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc1>;
impl<'a, REG> Emc1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 2. Determines the functionality of External Match 2.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc2 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc2> for u8 {
#[inline(always)]
fn from(variant: Emc2) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc2 {
type Ux = u8;
}
#[doc = "Field `EMC2` reader - External Match Control 2. Determines the functionality of External Match 2."]
pub type Emc2R = crate::FieldReader<Emc2>;
impl Emc2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc2 {
match self.bits {
0 => Emc2::DoNothing_,
1 => Emc2::ClearTheCorrespond,
2 => Emc2::SetTheCorrespondin,
3 => Emc2::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc2::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc2::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc2::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc2::ToggleTheCorrespon
}
}
#[doc = "Field `EMC2` writer - External Match Control 2. Determines the functionality of External Match 2."]
pub type Emc2W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc2>;
impl<'a, REG> Emc2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 3. Determines the functionality of External Match 3.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc3 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc3> for u8 {
#[inline(always)]
fn from(variant: Emc3) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc3 {
type Ux = u8;
}
#[doc = "Field `EMC3` reader - External Match Control 3. Determines the functionality of External Match 3."]
pub type Emc3R = crate::FieldReader<Emc3>;
impl Emc3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc3 {
match self.bits {
0 => Emc3::DoNothing_,
1 => Emc3::ClearTheCorrespond,
2 => Emc3::SetTheCorrespondin,
3 => Emc3::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc3::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc3::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc3::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc3::ToggleTheCorrespon
}
}
#[doc = "Field `EMC3` writer - External Match Control 3. Determines the functionality of External Match 3."]
pub type Emc3W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc3>;
impl<'a, REG> Emc3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::ToggleTheCorrespon)
}
}
impl R {
#[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em0(&self) -> Em0R {
Em0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em1(&self) -> Em1R {
Em1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em2(&self) -> Em2R {
Em2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
#[inline(always)]
pub fn em3(&self) -> Em3R {
Em3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline(always)]
pub fn emc0(&self) -> Emc0R {
Emc0R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline(always)]
pub fn emc1(&self) -> Emc1R {
Emc1R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline(always)]
pub fn emc2(&self) -> Emc2R {
Emc2R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline(always)]
pub fn emc3(&self) -> Emc3R {
Emc3R::new(((self.bits >> 10) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em0(&mut self) -> Em0W<EmrSpec> {
Em0W::new(self, 0)
}
#[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em1(&mut self) -> Em1W<EmrSpec> {
Em1W::new(self, 1)
}
#[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em2(&mut self) -> Em2W<EmrSpec> {
Em2W::new(self, 2)
}
#[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
#[inline(always)]
#[must_use]
pub fn em3(&mut self) -> Em3W<EmrSpec> {
Em3W::new(self, 3)
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline(always)]
#[must_use]
pub fn emc0(&mut self) -> Emc0W<EmrSpec> {
Emc0W::new(self, 4)
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline(always)]
#[must_use]
pub fn emc1(&mut self) -> Emc1W<EmrSpec> {
Emc1W::new(self, 6)
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline(always)]
#[must_use]
pub fn emc2(&mut self) -> Emc2W<EmrSpec> {
Emc2W::new(self, 8)
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline(always)]
#[must_use]
pub fn emc3(&mut self) -> Emc3W<EmrSpec> {
Emc3W::new(self, 10)
}
}
#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrSpec;
impl crate::RegisterSpec for EmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`emr::R`](R) reader structure"]
impl crate::Readable for EmrSpec {}
#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"]
impl crate::Writable for EmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EMR to value 0"]
impl crate::Resettable for EmrSpec {
const RESET_VALUE: u32 = 0;
}

115
rust-embedded/lpc111x-pac/src/ct16b0/ir.rs Normal file
View file

@ -0,0 +1,115 @@
#[doc = "Register `IR` reader"]
pub type R = crate::R<IrSpec>;
#[doc = "Register `IR` writer"]
pub type W = crate::W<IrSpec>;
#[doc = "Field `MR0INT` reader - Interrupt flag for match channel 0."]
pub type Mr0intR = crate::BitReader;
#[doc = "Field `MR0INT` writer - Interrupt flag for match channel 0."]
pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR1INT` reader - Interrupt flag for match channel 1."]
pub type Mr1intR = crate::BitReader;
#[doc = "Field `MR1INT` writer - Interrupt flag for match channel 1."]
pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR2INT` reader - Interrupt flag for match channel 2."]
pub type Mr2intR = crate::BitReader;
#[doc = "Field `MR2INT` writer - Interrupt flag for match channel 2."]
pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR3INT` reader - Interrupt flag for match channel 3."]
pub type Mr3intR = crate::BitReader;
#[doc = "Field `MR3INT` writer - Interrupt flag for match channel 3."]
pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CR0INT` reader - Interrupt flag for capture channel 0 event."]
pub type Cr0intR = crate::BitReader;
#[doc = "Field `CR0INT` writer - Interrupt flag for capture channel 0 event."]
pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CR1INT` reader - Interrupt flag for capture channel 1 event."]
pub type Cr1intR = crate::BitReader;
#[doc = "Field `CR1INT` writer - Interrupt flag for capture channel 1 event."]
pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline(always)]
pub fn mr0int(&self) -> Mr0intR {
Mr0intR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline(always)]
pub fn mr1int(&self) -> Mr1intR {
Mr1intR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline(always)]
pub fn mr2int(&self) -> Mr2intR {
Mr2intR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline(always)]
pub fn mr3int(&self) -> Mr3intR {
Mr3intR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline(always)]
pub fn cr0int(&self) -> Cr0intR {
Cr0intR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline(always)]
pub fn cr1int(&self) -> Cr1intR {
Cr1intR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline(always)]
#[must_use]
pub fn mr0int(&mut self) -> Mr0intW<IrSpec> {
Mr0intW::new(self, 0)
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline(always)]
#[must_use]
pub fn mr1int(&mut self) -> Mr1intW<IrSpec> {
Mr1intW::new(self, 1)
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline(always)]
#[must_use]
pub fn mr2int(&mut self) -> Mr2intW<IrSpec> {
Mr2intW::new(self, 2)
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline(always)]
#[must_use]
pub fn mr3int(&mut self) -> Mr3intW<IrSpec> {
Mr3intW::new(self, 3)
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline(always)]
#[must_use]
pub fn cr0int(&mut self) -> Cr0intW<IrSpec> {
Cr0intW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline(always)]
#[must_use]
pub fn cr1int(&mut self) -> Cr1intW<IrSpec> {
Cr1intW::new(self, 5)
}
}
#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrSpec;
impl crate::RegisterSpec for IrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ir::R`](R) reader structure"]
impl crate::Readable for IrSpec {}
#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
impl crate::Writable for IrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IR to value 0"]
impl crate::Resettable for IrSpec {
const RESET_VALUE: u32 = 0;
}

813
rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs Normal file
View file

@ -0,0 +1,813 @@
#[doc = "Register `MCR` reader"]
pub type R = crate::R<McrSpec>;
#[doc = "Register `MCR` writer"]
pub type W = crate::W<McrSpec>;
#[doc = "Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0i> for bool {
#[inline(always)]
fn from(variant: Mr0i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0I` reader - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
pub type Mr0iR = crate::BitReader<Mr0i>;
impl Mr0iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0i {
match self.bits {
true => Mr0i::Enabled,
false => Mr0i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0i::Disabled
}
}
#[doc = "Field `MR0I` writer - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>;
impl<'a, REG> Mr0iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0i::Disabled)
}
}
#[doc = "Reset on MR0: the TC will be reset if MR0 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0r> for bool {
#[inline(always)]
fn from(variant: Mr0r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0R` reader - Reset on MR0: the TC will be reset if MR0 matches it."]
pub type Mr0rR = crate::BitReader<Mr0r>;
impl Mr0rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0r {
match self.bits {
true => Mr0r::Enabled,
false => Mr0r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0r::Disabled
}
}
#[doc = "Field `MR0R` writer - Reset on MR0: the TC will be reset if MR0 matches it."]
pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>;
impl<'a, REG> Mr0rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0r::Disabled)
}
}
#[doc = "Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0s> for bool {
#[inline(always)]
fn from(variant: Mr0s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0S` reader - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
pub type Mr0sR = crate::BitReader<Mr0s>;
impl Mr0sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0s {
match self.bits {
true => Mr0s::Enabled,
false => Mr0s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0s::Disabled
}
}
#[doc = "Field `MR0S` writer - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>;
impl<'a, REG> Mr0sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0s::Disabled)
}
}
#[doc = "Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1i> for bool {
#[inline(always)]
fn from(variant: Mr1i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1I` reader - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
pub type Mr1iR = crate::BitReader<Mr1i>;
impl Mr1iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1i {
match self.bits {
true => Mr1i::Enabled,
false => Mr1i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1i::Disabled
}
}
#[doc = "Field `MR1I` writer - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>;
impl<'a, REG> Mr1iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1i::Disabled)
}
}
#[doc = "Reset on MR1: the TC will be reset if MR1 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1r> for bool {
#[inline(always)]
fn from(variant: Mr1r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1R` reader - Reset on MR1: the TC will be reset if MR1 matches it."]
pub type Mr1rR = crate::BitReader<Mr1r>;
impl Mr1rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1r {
match self.bits {
true => Mr1r::Enabled,
false => Mr1r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1r::Disabled
}
}
#[doc = "Field `MR1R` writer - Reset on MR1: the TC will be reset if MR1 matches it."]
pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>;
impl<'a, REG> Mr1rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1r::Disabled)
}
}
#[doc = "Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1s> for bool {
#[inline(always)]
fn from(variant: Mr1s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1S` reader - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
pub type Mr1sR = crate::BitReader<Mr1s>;
impl Mr1sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1s {
match self.bits {
true => Mr1s::Enabled,
false => Mr1s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1s::Disabled
}
}
#[doc = "Field `MR1S` writer - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>;
impl<'a, REG> Mr1sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1s::Disabled)
}
}
#[doc = "Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2i> for bool {
#[inline(always)]
fn from(variant: Mr2i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2I` reader - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
pub type Mr2iR = crate::BitReader<Mr2i>;
impl Mr2iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2i {
match self.bits {
true => Mr2i::Enabled,
false => Mr2i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2i::Disabled
}
}
#[doc = "Field `MR2I` writer - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>;
impl<'a, REG> Mr2iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2i::Disabled)
}
}
#[doc = "Reset on MR2: the TC will be reset if MR2 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2r> for bool {
#[inline(always)]
fn from(variant: Mr2r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2R` reader - Reset on MR2: the TC will be reset if MR2 matches it."]
pub type Mr2rR = crate::BitReader<Mr2r>;
impl Mr2rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2r {
match self.bits {
true => Mr2r::Enabled,
false => Mr2r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2r::Disabled
}
}
#[doc = "Field `MR2R` writer - Reset on MR2: the TC will be reset if MR2 matches it."]
pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>;
impl<'a, REG> Mr2rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2r::Disabled)
}
}
#[doc = "Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2s> for bool {
#[inline(always)]
fn from(variant: Mr2s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2S` reader - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
pub type Mr2sR = crate::BitReader<Mr2s>;
impl Mr2sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2s {
match self.bits {
true => Mr2s::Enabled,
false => Mr2s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2s::Disabled
}
}
#[doc = "Field `MR2S` writer - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>;
impl<'a, REG> Mr2sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2s::Disabled)
}
}
#[doc = "Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3i> for bool {
#[inline(always)]
fn from(variant: Mr3i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3I` reader - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
pub type Mr3iR = crate::BitReader<Mr3i>;
impl Mr3iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3i {
match self.bits {
true => Mr3i::Enabled,
false => Mr3i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3i::Disabled
}
}
#[doc = "Field `MR3I` writer - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>;
impl<'a, REG> Mr3iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3i::Disabled)
}
}
#[doc = "Reset on MR3: the TC will be reset if MR3 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3r> for bool {
#[inline(always)]
fn from(variant: Mr3r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3R` reader - Reset on MR3: the TC will be reset if MR3 matches it."]
pub type Mr3rR = crate::BitReader<Mr3r>;
impl Mr3rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3r {
match self.bits {
true => Mr3r::Enabled,
false => Mr3r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3r::Disabled
}
}
#[doc = "Field `MR3R` writer - Reset on MR3: the TC will be reset if MR3 matches it."]
pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>;
impl<'a, REG> Mr3rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3r::Disabled)
}
}
#[doc = "Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3s> for bool {
#[inline(always)]
fn from(variant: Mr3s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3S` reader - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
pub type Mr3sR = crate::BitReader<Mr3s>;
impl Mr3sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3s {
match self.bits {
true => Mr3s::Enabled,
false => Mr3s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3s::Disabled
}
}
#[doc = "Field `MR3S` writer - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>;
impl<'a, REG> Mr3sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3s::Disabled)
}
}
impl R {
#[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
#[inline(always)]
pub fn mr0i(&self) -> Mr0iR {
Mr0iR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
#[inline(always)]
pub fn mr0r(&self) -> Mr0rR {
Mr0rR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
#[inline(always)]
pub fn mr0s(&self) -> Mr0sR {
Mr0sR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
#[inline(always)]
pub fn mr1i(&self) -> Mr1iR {
Mr1iR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
#[inline(always)]
pub fn mr1r(&self) -> Mr1rR {
Mr1rR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
#[inline(always)]
pub fn mr1s(&self) -> Mr1sR {
Mr1sR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
#[inline(always)]
pub fn mr2i(&self) -> Mr2iR {
Mr2iR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
#[inline(always)]
pub fn mr2r(&self) -> Mr2rR {
Mr2rR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
#[inline(always)]
pub fn mr2s(&self) -> Mr2sR {
Mr2sR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
#[inline(always)]
pub fn mr3i(&self) -> Mr3iR {
Mr3iR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
#[inline(always)]
pub fn mr3r(&self) -> Mr3rR {
Mr3rR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
#[inline(always)]
pub fn mr3s(&self) -> Mr3sR {
Mr3sR::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr0i(&mut self) -> Mr0iW<McrSpec> {
Mr0iW::new(self, 0)
}
#[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
#[inline(always)]
#[must_use]
pub fn mr0r(&mut self) -> Mr0rW<McrSpec> {
Mr0rW::new(self, 1)
}
#[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr0s(&mut self) -> Mr0sW<McrSpec> {
Mr0sW::new(self, 2)
}
#[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr1i(&mut self) -> Mr1iW<McrSpec> {
Mr1iW::new(self, 3)
}
#[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
#[inline(always)]
#[must_use]
pub fn mr1r(&mut self) -> Mr1rW<McrSpec> {
Mr1rW::new(self, 4)
}
#[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr1s(&mut self) -> Mr1sW<McrSpec> {
Mr1sW::new(self, 5)
}
#[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr2i(&mut self) -> Mr2iW<McrSpec> {
Mr2iW::new(self, 6)
}
#[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
#[inline(always)]
#[must_use]
pub fn mr2r(&mut self) -> Mr2rW<McrSpec> {
Mr2rW::new(self, 7)
}
#[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr2s(&mut self) -> Mr2sW<McrSpec> {
Mr2sW::new(self, 8)
}
#[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr3i(&mut self) -> Mr3iW<McrSpec> {
Mr3iW::new(self, 9)
}
#[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
#[inline(always)]
#[must_use]
pub fn mr3r(&mut self) -> Mr3rW<McrSpec> {
Mr3rW::new(self, 10)
}
#[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr3s(&mut self) -> Mr3sW<McrSpec> {
Mr3sW::new(self, 11)
}
}
#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct McrSpec;
impl crate::RegisterSpec for McrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mcr::R`](R) reader structure"]
impl crate::Readable for McrSpec {}
#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
impl crate::Writable for McrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MCR to value 0"]
impl crate::Resettable for McrSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct16b0/mr.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `MR%s` reader"]
pub type R = crate::R<MrSpec>;
#[doc = "Register `MR%s` writer"]
pub type W = crate::W<MrSpec>;
#[doc = "Field `MATCH` reader - Timer counter match value."]
pub type MatchR = crate::FieldReader<u16>;
#[doc = "Field `MATCH` writer - Timer counter match value."]
pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Timer counter match value."]
#[inline(always)]
pub fn match_(&self) -> MatchR {
MatchR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Timer counter match value."]
#[inline(always)]
#[must_use]
pub fn match_(&mut self) -> MatchW<MrSpec> {
MatchW::new(self, 0)
}
}
#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MrSpec;
impl crate::RegisterSpec for MrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
impl crate::Readable for MrSpec {}
#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
impl crate::Writable for MrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MR%s to value 0"]
impl crate::Resettable for MrSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct16b0/pc.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `PC` reader"]
pub type R = crate::R<PcSpec>;
#[doc = "Register `PC` writer"]
pub type W = crate::W<PcSpec>;
#[doc = "Field `PC` reader - Prescale counter value."]
pub type PcR = crate::FieldReader<u16>;
#[doc = "Field `PC` writer - Prescale counter value."]
pub type PcW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescale counter value."]
#[inline(always)]
pub fn pc(&self) -> PcR {
PcR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescale counter value."]
#[inline(always)]
#[must_use]
pub fn pc(&mut self) -> PcW<PcSpec> {
PcW::new(self, 0)
}
}
#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcSpec;
impl crate::RegisterSpec for PcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pc::R`](R) reader structure"]
impl crate::Readable for PcSpec {}
#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"]
impl crate::Writable for PcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PC to value 0"]
impl crate::Resettable for PcSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct16b0/pr.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `PR` reader"]
pub type R = crate::R<PrSpec>;
#[doc = "Register `PR` writer"]
pub type W = crate::W<PrSpec>;
#[doc = "Field `PR` reader - Prescale max value."]
pub type PrR = crate::FieldReader<u16>;
#[doc = "Field `PR` writer - Prescale max value."]
pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Prescale max value."]
#[inline(always)]
pub fn pr(&self) -> PrR {
PrR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Prescale max value."]
#[inline(always)]
#[must_use]
pub fn pr(&mut self) -> PrW<PrSpec> {
PrW::new(self, 0)
}
}
#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrSpec;
impl crate::RegisterSpec for PrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pr::R`](R) reader structure"]
impl crate::Readable for PrSpec {}
#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"]
impl crate::Writable for PrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PR to value 0"]
impl crate::Resettable for PrSpec {
const RESET_VALUE: u32 = 0;
}

281
rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs Normal file
View file

@ -0,0 +1,281 @@
#[doc = "Register `PWMC` reader"]
pub type R = crate::R<PwmcSpec>;
#[doc = "Register `PWMC` writer"]
pub type W = crate::W<PwmcSpec>;
#[doc = "PWM channel0 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen0 {
#[doc = "0: CT16Bn_MAT0 is controlled by EM0."]
Ct16bnMat0IsContr = 0,
#[doc = "1: PWM mode is enabled for CT16Bn_MAT0."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen0> for bool {
#[inline(always)]
fn from(variant: Pwmen0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN0` reader - PWM channel0 enable"]
pub type Pwmen0R = crate::BitReader<Pwmen0>;
impl Pwmen0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen0 {
match self.bits {
false => Pwmen0::Ct16bnMat0IsContr,
true => Pwmen0::PwmModeIsEnabled_,
}
}
#[doc = "CT16Bn_MAT0 is controlled by EM0."]
#[inline(always)]
pub fn is_ct16bn_mat0_is_contr(&self) -> bool {
*self == Pwmen0::Ct16bnMat0IsContr
}
#[doc = "PWM mode is enabled for CT16Bn_MAT0."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen0::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN0` writer - PWM channel0 enable"]
pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>;
impl<'a, REG> Pwmen0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT16Bn_MAT0 is controlled by EM0."]
#[inline(always)]
pub fn ct16bn_mat0_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen0::Ct16bnMat0IsContr)
}
#[doc = "PWM mode is enabled for CT16Bn_MAT0."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen0::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel1 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen1 {
#[doc = "0: CT16Bn_MAT1 is controlled by EM1."]
Ct16bnMat1IsContr = 0,
#[doc = "1: PWM mode is enabled for CT16Bn_MAT1."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen1> for bool {
#[inline(always)]
fn from(variant: Pwmen1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN1` reader - PWM channel1 enable"]
pub type Pwmen1R = crate::BitReader<Pwmen1>;
impl Pwmen1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen1 {
match self.bits {
false => Pwmen1::Ct16bnMat1IsContr,
true => Pwmen1::PwmModeIsEnabled_,
}
}
#[doc = "CT16Bn_MAT1 is controlled by EM1."]
#[inline(always)]
pub fn is_ct16bn_mat1_is_contr(&self) -> bool {
*self == Pwmen1::Ct16bnMat1IsContr
}
#[doc = "PWM mode is enabled for CT16Bn_MAT1."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen1::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN1` writer - PWM channel1 enable"]
pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>;
impl<'a, REG> Pwmen1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT16Bn_MAT1 is controlled by EM1."]
#[inline(always)]
pub fn ct16bn_mat1_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen1::Ct16bnMat1IsContr)
}
#[doc = "PWM mode is enabled for CT16Bn_MAT1."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen1::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel2 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen2 {
#[doc = "0: Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."]
MatchChannel2OrP = 0,
#[doc = "1: PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen2> for bool {
#[inline(always)]
fn from(variant: Pwmen2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN2` reader - PWM channel2 enable"]
pub type Pwmen2R = crate::BitReader<Pwmen2>;
impl Pwmen2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen2 {
match self.bits {
false => Pwmen2::MatchChannel2OrP,
true => Pwmen2::PwmModeIsEnabled_,
}
}
#[doc = "Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."]
#[inline(always)]
pub fn is_match_channel_2_or_p(&self) -> bool {
*self == Pwmen2::MatchChannel2OrP
}
#[doc = "PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen2::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN2` writer - PWM channel2 enable"]
pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>;
impl<'a, REG> Pwmen2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."]
#[inline(always)]
pub fn match_channel_2_or_p(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen2::MatchChannel2OrP)
}
#[doc = "PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen2::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen3 {
#[doc = "0: Match channel 3 match channel 3 is controlled by EM3."]
MatchChannel3Matc = 0,
#[doc = "1: PWM mode is enabled for match channel 3match channel 3."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen3> for bool {
#[inline(always)]
fn from(variant: Pwmen3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN3` reader - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."]
pub type Pwmen3R = crate::BitReader<Pwmen3>;
impl Pwmen3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen3 {
match self.bits {
false => Pwmen3::MatchChannel3Matc,
true => Pwmen3::PwmModeIsEnabled_,
}
}
#[doc = "Match channel 3 match channel 3 is controlled by EM3."]
#[inline(always)]
pub fn is_match_channel_3_matc(&self) -> bool {
*self == Pwmen3::MatchChannel3Matc
}
#[doc = "PWM mode is enabled for match channel 3match channel 3."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen3::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN3` writer - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."]
pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>;
impl<'a, REG> Pwmen3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Match channel 3 match channel 3 is controlled by EM3."]
#[inline(always)]
pub fn match_channel_3_matc(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen3::MatchChannel3Matc)
}
#[doc = "PWM mode is enabled for match channel 3match channel 3."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen3::PwmModeIsEnabled_)
}
}
impl R {
#[doc = "Bit 0 - PWM channel0 enable"]
#[inline(always)]
pub fn pwmen0(&self) -> Pwmen0R {
Pwmen0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PWM channel1 enable"]
#[inline(always)]
pub fn pwmen1(&self) -> Pwmen1R {
Pwmen1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM channel2 enable"]
#[inline(always)]
pub fn pwmen2(&self) -> Pwmen2R {
Pwmen2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."]
#[inline(always)]
pub fn pwmen3(&self) -> Pwmen3R {
Pwmen3R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PWM channel0 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen0(&mut self) -> Pwmen0W<PwmcSpec> {
Pwmen0W::new(self, 0)
}
#[doc = "Bit 1 - PWM channel1 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen1(&mut self) -> Pwmen1W<PwmcSpec> {
Pwmen1W::new(self, 1)
}
#[doc = "Bit 2 - PWM channel2 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen2(&mut self) -> Pwmen2W<PwmcSpec> {
Pwmen2W::new(self, 2)
}
#[doc = "Bit 3 - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."]
#[inline(always)]
#[must_use]
pub fn pwmen3(&mut self) -> Pwmen3W<PwmcSpec> {
Pwmen3W::new(self, 3)
}
}
#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmcSpec;
impl crate::RegisterSpec for PwmcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"]
impl crate::Readable for PwmcSpec {}
#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"]
impl crate::Writable for PwmcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PWMC to value 0"]
impl crate::Resettable for PwmcSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct16b0/tc.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `TC` reader"]
pub type R = crate::R<TcSpec>;
#[doc = "Register `TC` writer"]
pub type W = crate::W<TcSpec>;
#[doc = "Field `TC` reader - Timer counter value."]
pub type TcR = crate::FieldReader<u16>;
#[doc = "Field `TC` writer - Timer counter value."]
pub type TcW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Timer counter value."]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Timer counter value."]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<TcSpec> {
TcW::new(self, 0)
}
}
#[doc = "Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcSpec;
impl crate::RegisterSpec for TcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tc::R`](R) reader structure"]
impl crate::Readable for TcSpec {}
#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"]
impl crate::Writable for TcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TC to value 0"]
impl crate::Resettable for TcSpec {
const RESET_VALUE: u32 = 0;
}

59
rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs Normal file
View file

@ -0,0 +1,59 @@
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `CEN` reader - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRST` reader - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CrstR = crate::BitReader;
#[doc = "Field `CRST` writer - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CrstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
pub fn crst(&self) -> CrstR {
CrstR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<TcrSpec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
#[must_use]
pub fn crst(&mut self) -> CrstW<TcrSpec> {
CrstW::new(self, 1)
}
}
#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}

164
rust-embedded/lpc111x-pac/src/ct32b0.rs Normal file
View file

@ -0,0 +1,164 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
ir: Ir,
tcr: Tcr,
tc: Tc,
pr: Pr,
pc: Pc,
mcr: Mcr,
mr: [Mr; 4],
ccr: Ccr,
cr: [Cr; 2],
_reserved9: [u8; 0x08],
emr: Emr,
_reserved10: [u8; 0x30],
ctcr: Ctcr,
pwmc: Pwmc,
}
impl RegisterBlock {
#[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
#[inline(always)]
pub const fn ir(&self) -> &Ir {
&self.ir
}
#[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
#[inline(always)]
pub const fn tcr(&self) -> &Tcr {
&self.tcr
}
#[doc = "0x08 - Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
#[inline(always)]
pub const fn tc(&self) -> &Tc {
&self.tc
}
#[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
#[inline(always)]
pub const fn pr(&self) -> &Pr {
&self.pr
}
#[doc = "0x10 - Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
#[inline(always)]
pub const fn pc(&self) -> &Pc {
&self.pc
}
#[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
#[inline(always)]
pub const fn mcr(&self) -> &Mcr {
&self.mcr
}
#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
#[inline(always)]
pub const fn mr(&self, n: usize) -> &Mr {
&self.mr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
#[inline(always)]
pub fn mr_iter(&self) -> impl Iterator<Item = &Mr> {
self.mr.iter()
}
#[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
#[inline(always)]
pub const fn ccr(&self) -> &Ccr {
&self.ccr
}
#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
#[inline(always)]
pub const fn cr(&self, n: usize) -> &Cr {
&self.cr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
#[inline(always)]
pub fn cr_iter(&self) -> impl Iterator<Item = &Cr> {
self.cr.iter()
}
#[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."]
#[inline(always)]
pub const fn emr(&self) -> &Emr {
&self.emr
}
#[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
#[inline(always)]
pub const fn ctcr(&self) -> &Ctcr {
&self.ctcr
}
#[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."]
#[inline(always)]
pub const fn pwmc(&self) -> &Pwmc {
&self.pwmc
}
}
#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
module"]
#[doc(alias = "IR")]
pub type Ir = crate::Reg<ir::IrSpec>;
#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
pub mod ir;
#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
module"]
#[doc(alias = "TCR")]
pub type Tcr = crate::Reg<tcr::TcrSpec>;
#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
pub mod tcr;
#[doc = "TC (rw) register accessor: Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`]
module"]
#[doc(alias = "TC")]
pub type Tc = crate::Reg<tc::TcSpec>;
#[doc = "Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
pub mod tc;
#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`]
module"]
#[doc(alias = "PR")]
pub type Pr = crate::Reg<pr::PrSpec>;
#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
pub mod pr;
#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`]
module"]
#[doc(alias = "PC")]
pub type Pc = crate::Reg<pc::PcSpec>;
#[doc = "Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
pub mod pc;
#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
module"]
#[doc(alias = "MCR")]
pub type Mcr = crate::Reg<mcr::McrSpec>;
#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
pub mod mcr;
#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`]
module"]
#[doc(alias = "MR")]
pub type Mr = crate::Reg<mr::MrSpec>;
#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
pub mod mr;
#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
module"]
#[doc(alias = "CCR")]
pub type Ccr = crate::Reg<ccr::CcrSpec>;
#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
pub mod ccr;
#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
#[doc(alias = "CR")]
pub type Cr = crate::Reg<cr::CrSpec>;
#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
pub mod cr;
#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
module"]
#[doc(alias = "EMR")]
pub type Emr = crate::Reg<emr::EmrSpec>;
#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."]
pub mod emr;
#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`]
module"]
#[doc(alias = "CTCR")]
pub type Ctcr = crate::Reg<ctcr::CtcrSpec>;
#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
pub mod ctcr;
#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`]
module"]
#[doc(alias = "PWMC")]
pub type Pwmc = crate::Reg<pwmc::PwmcSpec>;
#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."]
pub mod pwmc;

409
rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs Normal file
View file

@ -0,0 +1,409 @@
#[doc = "Register `CCR` reader"]
pub type R = crate::R<CcrSpec>;
#[doc = "Register `CCR` writer"]
pub type W = crate::W<CcrSpec>;
#[doc = "Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0re {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0re> for bool {
#[inline(always)]
fn from(variant: Cap0re) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0RE` reader - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0reR = crate::BitReader<Cap0re>;
impl Cap0reR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0re {
match self.bits {
true => Cap0re::Enabled,
false => Cap0re::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0re::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0re::Disabled
}
}
#[doc = "Field `CAP0RE` writer - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>;
impl<'a, REG> Cap0reW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0re::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0re::Disabled)
}
}
#[doc = "Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0fe {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0fe> for bool {
#[inline(always)]
fn from(variant: Cap0fe) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0FE` reader - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0feR = crate::BitReader<Cap0fe>;
impl Cap0feR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0fe {
match self.bits {
true => Cap0fe::Enabled,
false => Cap0fe::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0fe::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0fe::Disabled
}
}
#[doc = "Field `CAP0FE` writer - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>;
impl<'a, REG> Cap0feW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0fe::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0fe::Disabled)
}
}
#[doc = "Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap0i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap0i> for bool {
#[inline(always)]
fn from(variant: Cap0i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP0I` reader - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."]
pub type Cap0iR = crate::BitReader<Cap0i>;
impl Cap0iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap0i {
match self.bits {
true => Cap0i::Enabled,
false => Cap0i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap0i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap0i::Disabled
}
}
#[doc = "Field `CAP0I` writer - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."]
pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>;
impl<'a, REG> Cap0iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap0i::Disabled)
}
}
#[doc = "Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1re {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1re> for bool {
#[inline(always)]
fn from(variant: Cap1re) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1RE` reader - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1reR = crate::BitReader<Cap1re>;
impl Cap1reR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1re {
match self.bits {
true => Cap1re::Enabled,
false => Cap1re::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1re::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1re::Disabled
}
}
#[doc = "Field `CAP1RE` writer - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>;
impl<'a, REG> Cap1reW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1re::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1re::Disabled)
}
}
#[doc = "Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1fe {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1fe> for bool {
#[inline(always)]
fn from(variant: Cap1fe) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1FE` reader - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1feR = crate::BitReader<Cap1fe>;
impl Cap1feR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1fe {
match self.bits {
true => Cap1fe::Enabled,
false => Cap1fe::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1fe::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1fe::Disabled
}
}
#[doc = "Field `CAP1FE` writer - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>;
impl<'a, REG> Cap1feW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1fe::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1fe::Disabled)
}
}
#[doc = "Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Cap1i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Cap1i> for bool {
#[inline(always)]
fn from(variant: Cap1i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `CAP1I` reader - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."]
pub type Cap1iR = crate::BitReader<Cap1i>;
impl Cap1iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cap1i {
match self.bits {
true => Cap1i::Enabled,
false => Cap1i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Cap1i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Cap1i::Disabled
}
}
#[doc = "Field `CAP1I` writer - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."]
pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>;
impl<'a, REG> Cap1iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Cap1i::Disabled)
}
}
impl R {
#[doc = "Bit 0 - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap0re(&self) -> Cap0reR {
Cap0reR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap0fe(&self) -> Cap0feR {
Cap0feR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."]
#[inline(always)]
pub fn cap0i(&self) -> Cap0iR {
Cap0iR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap1re(&self) -> Cap1reR {
Cap1reR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
pub fn cap1fe(&self) -> Cap1feR {
Cap1feR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."]
#[inline(always)]
pub fn cap1i(&self) -> Cap1iR {
Cap1iR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap0re(&mut self) -> Cap0reW<CcrSpec> {
Cap0reW::new(self, 0)
}
#[doc = "Bit 1 - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap0fe(&mut self) -> Cap0feW<CcrSpec> {
Cap0feW::new(self, 1)
}
#[doc = "Bit 2 - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."]
#[inline(always)]
#[must_use]
pub fn cap0i(&mut self) -> Cap0iW<CcrSpec> {
Cap0iW::new(self, 2)
}
#[doc = "Bit 3 - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap1re(&mut self) -> Cap1reW<CcrSpec> {
Cap1reW::new(self, 3)
}
#[doc = "Bit 4 - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
#[inline(always)]
#[must_use]
pub fn cap1fe(&mut self) -> Cap1feW<CcrSpec> {
Cap1feW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."]
#[inline(always)]
#[must_use]
pub fn cap1i(&mut self) -> Cap1iW<CcrSpec> {
Cap1iW::new(self, 5)
}
}
#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CcrSpec;
impl crate::RegisterSpec for CcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
impl crate::Readable for CcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
impl crate::Writable for CcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CCR to value 0"]
impl crate::Resettable for CcrSpec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/ct32b0/cr.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `CR%s` reader"]
pub type R = crate::R<CrSpec>;
#[doc = "Field `CAP` reader - Timer counter capture value."]
pub type CapR = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Timer counter capture value."]
#[inline(always)]
pub fn cap(&self) -> CapR {
CapR::new(self.bits)
}
}
#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CrSpec;
impl crate::RegisterSpec for CrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
impl crate::Readable for CrSpec {}
#[doc = "`reset()` method sets CR%s to value 0"]
impl crate::Resettable for CrSpec {
const RESET_VALUE: u32 = 0;
}

315
rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs Normal file
View file

@ -0,0 +1,315 @@
#[doc = "Register `CTCR` reader"]
pub type R = crate::R<CtcrSpec>;
#[doc = "Register `CTCR` writer"]
pub type W = crate::W<CtcrSpec>;
#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ctm {
#[doc = "0: Increment on every rising PCLK edge"]
Timer = 0,
#[doc = "1: Increment on rising CAP pin edge"]
CounterRising = 1,
#[doc = "2: Increment on falling CAP pin edge"]
CounterFalling = 2,
#[doc = "3: Increment on both CAP pin edges"]
CounterBoth = 3,
}
impl From<Ctm> for u8 {
#[inline(always)]
fn from(variant: Ctm) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ctm {
type Ux = u8;
}
#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
pub type CtmR = crate::FieldReader<Ctm>;
impl CtmR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Ctm {
match self.bits {
0 => Ctm::Timer,
1 => Ctm::CounterRising,
2 => Ctm::CounterFalling,
3 => Ctm::CounterBoth,
_ => unreachable!(),
}
}
#[doc = "Increment on every rising PCLK edge"]
#[inline(always)]
pub fn is_timer(&self) -> bool {
*self == Ctm::Timer
}
#[doc = "Increment on rising CAP pin edge"]
#[inline(always)]
pub fn is_counter_rising(&self) -> bool {
*self == Ctm::CounterRising
}
#[doc = "Increment on falling CAP pin edge"]
#[inline(always)]
pub fn is_counter_falling(&self) -> bool {
*self == Ctm::CounterFalling
}
#[doc = "Increment on both CAP pin edges"]
#[inline(always)]
pub fn is_counter_both(&self) -> bool {
*self == Ctm::CounterBoth
}
}
#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
pub type CtmW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctm>;
impl<'a, REG> CtmW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Increment on every rising PCLK edge"]
#[inline(always)]
pub fn timer(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::Timer)
}
#[doc = "Increment on rising CAP pin edge"]
#[inline(always)]
pub fn counter_rising(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterRising)
}
#[doc = "Increment on falling CAP pin edge"]
#[inline(always)]
pub fn counter_falling(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterFalling)
}
#[doc = "Increment on both CAP pin edges"]
#[inline(always)]
pub fn counter_both(self) -> &'a mut crate::W<REG> {
self.variant(Ctm::CounterBoth)
}
}
#[doc = "Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Cis {
#[doc = "0: CT32Bn_CAP0"]
Ct32bnCap0 = 0,
#[doc = "1: CT32Bn_CAP1"]
Ct32bnCap1 = 1,
#[doc = "3: Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."]
ReservedNoteIfCo = 3,
}
impl From<Cis> for u8 {
#[inline(always)]
fn from(variant: Cis) -> Self {
variant as _
}
}
impl crate::FieldSpec for Cis {
type Ux = u8;
}
#[doc = "Field `CIS` reader - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
pub type CisR = crate::FieldReader<Cis>;
impl CisR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Cis {
match self.bits {
0 => Cis::Ct32bnCap0,
1 => Cis::Ct32bnCap1,
3 => Cis::ReservedNoteIfCo,
_ => unreachable!(),
}
}
#[doc = "CT32Bn_CAP0"]
#[inline(always)]
pub fn is_ct32bn_cap0(&self) -> bool {
*self == Cis::Ct32bnCap0
}
#[doc = "CT32Bn_CAP1"]
#[inline(always)]
pub fn is_ct32bn_cap1(&self) -> bool {
*self == Cis::Ct32bnCap1
}
#[doc = "Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."]
#[inline(always)]
pub fn is_reserved_note_if_co(&self) -> bool {
*self == Cis::ReservedNoteIfCo
}
}
#[doc = "Field `CIS` writer - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
pub type CisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cis>;
impl<'a, REG> CisW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "CT32Bn_CAP0"]
#[inline(always)]
pub fn ct32bn_cap0(self) -> &'a mut crate::W<REG> {
self.variant(Cis::Ct32bnCap0)
}
#[doc = "CT32Bn_CAP1"]
#[inline(always)]
pub fn ct32bn_cap1(self) -> &'a mut crate::W<REG> {
self.variant(Cis::Ct32bnCap1)
}
#[doc = "Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."]
#[inline(always)]
pub fn reserved_note_if_co(self) -> &'a mut crate::W<REG> {
self.variant(Cis::ReservedNoteIfCo)
}
}
#[doc = "Field `ENCC` reader - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
pub type EnccR = crate::BitReader;
#[doc = "Field `ENCC` writer - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Selcc {
#[doc = "0: Rising Edge of CAP0 clears the timer"]
Cap0Rising = 0,
#[doc = "1: Falling Edge of CAP0 clears the timer"]
Cap0Falling = 1,
#[doc = "2: Rising Edge of CAP1 clears the timer"]
Cap1Rising = 2,
#[doc = "3: Falling Edge of CAP1 clears the timer"]
Cap1Falling = 3,
}
impl From<Selcc> for u8 {
#[inline(always)]
fn from(variant: Selcc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Selcc {
type Ux = u8;
}
#[doc = "Field `SELCC` reader - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
pub type SelccR = crate::FieldReader<Selcc>;
impl SelccR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Selcc> {
match self.bits {
0 => Some(Selcc::Cap0Rising),
1 => Some(Selcc::Cap0Falling),
2 => Some(Selcc::Cap1Rising),
3 => Some(Selcc::Cap1Falling),
_ => None,
}
}
#[doc = "Rising Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn is_cap0_rising(&self) -> bool {
*self == Selcc::Cap0Rising
}
#[doc = "Falling Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn is_cap0_falling(&self) -> bool {
*self == Selcc::Cap0Falling
}
#[doc = "Rising Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn is_cap1_rising(&self) -> bool {
*self == Selcc::Cap1Rising
}
#[doc = "Falling Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn is_cap1_falling(&self) -> bool {
*self == Selcc::Cap1Falling
}
}
#[doc = "Field `SELCC` writer - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc>;
impl<'a, REG> SelccW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Rising Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn cap0_rising(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap0Rising)
}
#[doc = "Falling Edge of CAP0 clears the timer"]
#[inline(always)]
pub fn cap0_falling(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap0Falling)
}
#[doc = "Rising Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn cap1_rising(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap1Rising)
}
#[doc = "Falling Edge of CAP1 clears the timer"]
#[inline(always)]
pub fn cap1_falling(self) -> &'a mut crate::W<REG> {
self.variant(Selcc::Cap1Falling)
}
}
impl R {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
#[inline(always)]
pub fn ctm(&self) -> CtmR {
CtmR::new((self.bits & 3) as u8)
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
#[inline(always)]
pub fn cis(&self) -> CisR {
CisR::new(((self.bits >> 2) & 3) as u8)
}
#[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
#[inline(always)]
pub fn encc(&self) -> EnccR {
EnccR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
#[inline(always)]
pub fn selcc(&self) -> SelccR {
SelccR::new(((self.bits >> 5) & 7) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"]
#[inline(always)]
#[must_use]
pub fn ctm(&mut self) -> CtmW<CtcrSpec> {
CtmW::new(self, 0)
}
#[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"]
#[inline(always)]
#[must_use]
pub fn cis(&mut self) -> CisW<CtcrSpec> {
CisW::new(self, 2)
}
#[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
#[inline(always)]
#[must_use]
pub fn encc(&mut self) -> EnccW<CtcrSpec> {
EnccW::new(self, 4)
}
#[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
#[inline(always)]
#[must_use]
pub fn selcc(&mut self) -> SelccW<CtcrSpec> {
SelccW::new(self, 5)
}
}
#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtcrSpec;
impl crate::RegisterSpec for CtcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"]
impl crate::Readable for CtcrSpec {}
#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"]
impl crate::Writable for CtcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CTCR to value 0"]
impl crate::Resettable for CtcrSpec {
const RESET_VALUE: u32 = 0;
}

485
rust-embedded/lpc111x-pac/src/ct32b0/emr.rs Normal file
View file

@ -0,0 +1,485 @@
#[doc = "Register `EMR` reader"]
pub type R = crate::R<EmrSpec>;
#[doc = "Register `EMR` writer"]
pub type W = crate::W<EmrSpec>;
#[doc = "Field `EM0` reader - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em0R = crate::BitReader;
#[doc = "Field `EM0` writer - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM1` reader - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em1R = crate::BitReader;
#[doc = "Field `EM1` writer - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM2` reader - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em2R = crate::BitReader;
#[doc = "Field `EM2` writer - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `EM3` reader - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em3R = crate::BitReader;
#[doc = "Field `EM3` writer - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
pub type Em3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "External Match Control 0. Determines the functionality of External Match 0.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc0 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc0> for u8 {
#[inline(always)]
fn from(variant: Emc0) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc0 {
type Ux = u8;
}
#[doc = "Field `EMC0` reader - External Match Control 0. Determines the functionality of External Match 0."]
pub type Emc0R = crate::FieldReader<Emc0>;
impl Emc0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc0 {
match self.bits {
0 => Emc0::DoNothing_,
1 => Emc0::ClearTheCorrespond,
2 => Emc0::SetTheCorrespondin,
3 => Emc0::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc0::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc0::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc0::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc0::ToggleTheCorrespon
}
}
#[doc = "Field `EMC0` writer - External Match Control 0. Determines the functionality of External Match 0."]
pub type Emc0W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc0>;
impl<'a, REG> Emc0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc0::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 1. Determines the functionality of External Match 1.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc1 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc1> for u8 {
#[inline(always)]
fn from(variant: Emc1) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc1 {
type Ux = u8;
}
#[doc = "Field `EMC1` reader - External Match Control 1. Determines the functionality of External Match 1."]
pub type Emc1R = crate::FieldReader<Emc1>;
impl Emc1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc1 {
match self.bits {
0 => Emc1::DoNothing_,
1 => Emc1::ClearTheCorrespond,
2 => Emc1::SetTheCorrespondin,
3 => Emc1::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc1::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc1::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc1::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc1::ToggleTheCorrespon
}
}
#[doc = "Field `EMC1` writer - External Match Control 1. Determines the functionality of External Match 1."]
pub type Emc1W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc1>;
impl<'a, REG> Emc1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc1::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 2. Determines the functionality of External Match 2.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc2 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc2> for u8 {
#[inline(always)]
fn from(variant: Emc2) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc2 {
type Ux = u8;
}
#[doc = "Field `EMC2` reader - External Match Control 2. Determines the functionality of External Match 2."]
pub type Emc2R = crate::FieldReader<Emc2>;
impl Emc2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc2 {
match self.bits {
0 => Emc2::DoNothing_,
1 => Emc2::ClearTheCorrespond,
2 => Emc2::SetTheCorrespondin,
3 => Emc2::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc2::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc2::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc2::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc2::ToggleTheCorrespon
}
}
#[doc = "Field `EMC2` writer - External Match Control 2. Determines the functionality of External Match 2."]
pub type Emc2W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc2>;
impl<'a, REG> Emc2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc2::ToggleTheCorrespon)
}
}
#[doc = "External Match Control 3. Determines the functionality of External Match 3.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Emc3 {
#[doc = "0: Do Nothing."]
DoNothing_ = 0,
#[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
ClearTheCorrespond = 1,
#[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
SetTheCorrespondin = 2,
#[doc = "3: Toggle the corresponding External Match bit/output."]
ToggleTheCorrespon = 3,
}
impl From<Emc3> for u8 {
#[inline(always)]
fn from(variant: Emc3) -> Self {
variant as _
}
}
impl crate::FieldSpec for Emc3 {
type Ux = u8;
}
#[doc = "Field `EMC3` reader - External Match Control 3. Determines the functionality of External Match 3."]
pub type Emc3R = crate::FieldReader<Emc3>;
impl Emc3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Emc3 {
match self.bits {
0 => Emc3::DoNothing_,
1 => Emc3::ClearTheCorrespond,
2 => Emc3::SetTheCorrespondin,
3 => Emc3::ToggleTheCorrespon,
_ => unreachable!(),
}
}
#[doc = "Do Nothing."]
#[inline(always)]
pub fn is_do_nothing_(&self) -> bool {
*self == Emc3::DoNothing_
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn is_clear_the_correspond(&self) -> bool {
*self == Emc3::ClearTheCorrespond
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn is_set_the_correspondin(&self) -> bool {
*self == Emc3::SetTheCorrespondin
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn is_toggle_the_correspon(&self) -> bool {
*self == Emc3::ToggleTheCorrespon
}
}
#[doc = "Field `EMC3` writer - External Match Control 3. Determines the functionality of External Match 3."]
pub type Emc3W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc3>;
impl<'a, REG> Emc3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Do Nothing."]
#[inline(always)]
pub fn do_nothing_(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::DoNothing_)
}
#[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."]
#[inline(always)]
pub fn clear_the_correspond(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::ClearTheCorrespond)
}
#[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."]
#[inline(always)]
pub fn set_the_correspondin(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::SetTheCorrespondin)
}
#[doc = "Toggle the corresponding External Match bit/output."]
#[inline(always)]
pub fn toggle_the_correspon(self) -> &'a mut crate::W<REG> {
self.variant(Emc3::ToggleTheCorrespon)
}
}
impl R {
#[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em0(&self) -> Em0R {
Em0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em1(&self) -> Em1R {
Em1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em2(&self) -> Em2R {
Em2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
pub fn em3(&self) -> Em3R {
Em3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline(always)]
pub fn emc0(&self) -> Emc0R {
Emc0R::new(((self.bits >> 4) & 3) as u8)
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline(always)]
pub fn emc1(&self) -> Emc1R {
Emc1R::new(((self.bits >> 6) & 3) as u8)
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline(always)]
pub fn emc2(&self) -> Emc2R {
Emc2R::new(((self.bits >> 8) & 3) as u8)
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline(always)]
pub fn emc3(&self) -> Emc3R {
Emc3R::new(((self.bits >> 10) & 3) as u8)
}
}
impl W {
#[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em0(&mut self) -> Em0W<EmrSpec> {
Em0W::new(self, 0)
}
#[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em1(&mut self) -> Em1W<EmrSpec> {
Em1W::new(self, 1)
}
#[doc = "Bit 2 - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em2(&mut self) -> Em2W<EmrSpec> {
Em2W::new(self, 2)
}
#[doc = "Bit 3 - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
#[inline(always)]
#[must_use]
pub fn em3(&mut self) -> Em3W<EmrSpec> {
Em3W::new(self, 3)
}
#[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
#[inline(always)]
#[must_use]
pub fn emc0(&mut self) -> Emc0W<EmrSpec> {
Emc0W::new(self, 4)
}
#[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
#[inline(always)]
#[must_use]
pub fn emc1(&mut self) -> Emc1W<EmrSpec> {
Emc1W::new(self, 6)
}
#[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
#[inline(always)]
#[must_use]
pub fn emc2(&mut self) -> Emc2W<EmrSpec> {
Emc2W::new(self, 8)
}
#[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
#[inline(always)]
#[must_use]
pub fn emc3(&mut self) -> Emc3W<EmrSpec> {
Emc3W::new(self, 10)
}
}
#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EmrSpec;
impl crate::RegisterSpec for EmrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`emr::R`](R) reader structure"]
impl crate::Readable for EmrSpec {}
#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"]
impl crate::Writable for EmrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets EMR to value 0"]
impl crate::Resettable for EmrSpec {
const RESET_VALUE: u32 = 0;
}

115
rust-embedded/lpc111x-pac/src/ct32b0/ir.rs Normal file
View file

@ -0,0 +1,115 @@
#[doc = "Register `IR` reader"]
pub type R = crate::R<IrSpec>;
#[doc = "Register `IR` writer"]
pub type W = crate::W<IrSpec>;
#[doc = "Field `MR0INT` reader - Interrupt flag for match channel 0."]
pub type Mr0intR = crate::BitReader;
#[doc = "Field `MR0INT` writer - Interrupt flag for match channel 0."]
pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR1INT` reader - Interrupt flag for match channel 1."]
pub type Mr1intR = crate::BitReader;
#[doc = "Field `MR1INT` writer - Interrupt flag for match channel 1."]
pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR2INT` reader - Interrupt flag for match channel 2."]
pub type Mr2intR = crate::BitReader;
#[doc = "Field `MR2INT` writer - Interrupt flag for match channel 2."]
pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MR3INT` reader - Interrupt flag for match channel 3."]
pub type Mr3intR = crate::BitReader;
#[doc = "Field `MR3INT` writer - Interrupt flag for match channel 3."]
pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CR0INT` reader - Interrupt flag for capture channel 0 event."]
pub type Cr0intR = crate::BitReader;
#[doc = "Field `CR0INT` writer - Interrupt flag for capture channel 0 event."]
pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CR1INT` reader - Interrupt flag for capture channel 1 event."]
pub type Cr1intR = crate::BitReader;
#[doc = "Field `CR1INT` writer - Interrupt flag for capture channel 1 event."]
pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline(always)]
pub fn mr0int(&self) -> Mr0intR {
Mr0intR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline(always)]
pub fn mr1int(&self) -> Mr1intR {
Mr1intR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline(always)]
pub fn mr2int(&self) -> Mr2intR {
Mr2intR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline(always)]
pub fn mr3int(&self) -> Mr3intR {
Mr3intR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline(always)]
pub fn cr0int(&self) -> Cr0intR {
Cr0intR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline(always)]
pub fn cr1int(&self) -> Cr1intR {
Cr1intR::new(((self.bits >> 5) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt flag for match channel 0."]
#[inline(always)]
#[must_use]
pub fn mr0int(&mut self) -> Mr0intW<IrSpec> {
Mr0intW::new(self, 0)
}
#[doc = "Bit 1 - Interrupt flag for match channel 1."]
#[inline(always)]
#[must_use]
pub fn mr1int(&mut self) -> Mr1intW<IrSpec> {
Mr1intW::new(self, 1)
}
#[doc = "Bit 2 - Interrupt flag for match channel 2."]
#[inline(always)]
#[must_use]
pub fn mr2int(&mut self) -> Mr2intW<IrSpec> {
Mr2intW::new(self, 2)
}
#[doc = "Bit 3 - Interrupt flag for match channel 3."]
#[inline(always)]
#[must_use]
pub fn mr3int(&mut self) -> Mr3intW<IrSpec> {
Mr3intW::new(self, 3)
}
#[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
#[inline(always)]
#[must_use]
pub fn cr0int(&mut self) -> Cr0intW<IrSpec> {
Cr0intW::new(self, 4)
}
#[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
#[inline(always)]
#[must_use]
pub fn cr1int(&mut self) -> Cr1intW<IrSpec> {
Cr1intW::new(self, 5)
}
}
#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrSpec;
impl crate::RegisterSpec for IrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ir::R`](R) reader structure"]
impl crate::Readable for IrSpec {}
#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
impl crate::Writable for IrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IR to value 0"]
impl crate::Resettable for IrSpec {
const RESET_VALUE: u32 = 0;
}

813
rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs Normal file
View file

@ -0,0 +1,813 @@
#[doc = "Register `MCR` reader"]
pub type R = crate::R<McrSpec>;
#[doc = "Register `MCR` writer"]
pub type W = crate::W<McrSpec>;
#[doc = "Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0i> for bool {
#[inline(always)]
fn from(variant: Mr0i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0I` reader - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
pub type Mr0iR = crate::BitReader<Mr0i>;
impl Mr0iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0i {
match self.bits {
true => Mr0i::Enabled,
false => Mr0i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0i::Disabled
}
}
#[doc = "Field `MR0I` writer - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>;
impl<'a, REG> Mr0iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0i::Disabled)
}
}
#[doc = "Reset on MR0: the TC will be reset if MR0 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0r> for bool {
#[inline(always)]
fn from(variant: Mr0r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0R` reader - Reset on MR0: the TC will be reset if MR0 matches it."]
pub type Mr0rR = crate::BitReader<Mr0r>;
impl Mr0rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0r {
match self.bits {
true => Mr0r::Enabled,
false => Mr0r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0r::Disabled
}
}
#[doc = "Field `MR0R` writer - Reset on MR0: the TC will be reset if MR0 matches it."]
pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>;
impl<'a, REG> Mr0rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0r::Disabled)
}
}
#[doc = "Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr0s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr0s> for bool {
#[inline(always)]
fn from(variant: Mr0s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR0S` reader - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
pub type Mr0sR = crate::BitReader<Mr0s>;
impl Mr0sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr0s {
match self.bits {
true => Mr0s::Enabled,
false => Mr0s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr0s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr0s::Disabled
}
}
#[doc = "Field `MR0S` writer - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>;
impl<'a, REG> Mr0sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr0s::Disabled)
}
}
#[doc = "Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1i> for bool {
#[inline(always)]
fn from(variant: Mr1i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1I` reader - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
pub type Mr1iR = crate::BitReader<Mr1i>;
impl Mr1iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1i {
match self.bits {
true => Mr1i::Enabled,
false => Mr1i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1i::Disabled
}
}
#[doc = "Field `MR1I` writer - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>;
impl<'a, REG> Mr1iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1i::Disabled)
}
}
#[doc = "Reset on MR1: the TC will be reset if MR1 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1r> for bool {
#[inline(always)]
fn from(variant: Mr1r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1R` reader - Reset on MR1: the TC will be reset if MR1 matches it."]
pub type Mr1rR = crate::BitReader<Mr1r>;
impl Mr1rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1r {
match self.bits {
true => Mr1r::Enabled,
false => Mr1r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1r::Disabled
}
}
#[doc = "Field `MR1R` writer - Reset on MR1: the TC will be reset if MR1 matches it."]
pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>;
impl<'a, REG> Mr1rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1r::Disabled)
}
}
#[doc = "Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr1s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr1s> for bool {
#[inline(always)]
fn from(variant: Mr1s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR1S` reader - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
pub type Mr1sR = crate::BitReader<Mr1s>;
impl Mr1sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr1s {
match self.bits {
true => Mr1s::Enabled,
false => Mr1s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr1s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr1s::Disabled
}
}
#[doc = "Field `MR1S` writer - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>;
impl<'a, REG> Mr1sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr1s::Disabled)
}
}
#[doc = "Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2i> for bool {
#[inline(always)]
fn from(variant: Mr2i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2I` reader - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
pub type Mr2iR = crate::BitReader<Mr2i>;
impl Mr2iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2i {
match self.bits {
true => Mr2i::Enabled,
false => Mr2i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2i::Disabled
}
}
#[doc = "Field `MR2I` writer - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>;
impl<'a, REG> Mr2iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2i::Disabled)
}
}
#[doc = "Reset on MR2: the TC will be reset if MR2 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2r> for bool {
#[inline(always)]
fn from(variant: Mr2r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2R` reader - Reset on MR2: the TC will be reset if MR2 matches it."]
pub type Mr2rR = crate::BitReader<Mr2r>;
impl Mr2rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2r {
match self.bits {
true => Mr2r::Enabled,
false => Mr2r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2r::Disabled
}
}
#[doc = "Field `MR2R` writer - Reset on MR2: the TC will be reset if MR2 matches it."]
pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>;
impl<'a, REG> Mr2rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2r::Disabled)
}
}
#[doc = "Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr2s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr2s> for bool {
#[inline(always)]
fn from(variant: Mr2s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR2S` reader - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
pub type Mr2sR = crate::BitReader<Mr2s>;
impl Mr2sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr2s {
match self.bits {
true => Mr2s::Enabled,
false => Mr2s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr2s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr2s::Disabled
}
}
#[doc = "Field `MR2S` writer - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>;
impl<'a, REG> Mr2sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr2s::Disabled)
}
}
#[doc = "Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3i {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3i> for bool {
#[inline(always)]
fn from(variant: Mr3i) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3I` reader - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
pub type Mr3iR = crate::BitReader<Mr3i>;
impl Mr3iR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3i {
match self.bits {
true => Mr3i::Enabled,
false => Mr3i::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3i::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3i::Disabled
}
}
#[doc = "Field `MR3I` writer - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>;
impl<'a, REG> Mr3iW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3i::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3i::Disabled)
}
}
#[doc = "Reset on MR3: the TC will be reset if MR3 matches it.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3r {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3r> for bool {
#[inline(always)]
fn from(variant: Mr3r) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3R` reader - Reset on MR3: the TC will be reset if MR3 matches it."]
pub type Mr3rR = crate::BitReader<Mr3r>;
impl Mr3rR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3r {
match self.bits {
true => Mr3r::Enabled,
false => Mr3r::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3r::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3r::Disabled
}
}
#[doc = "Field `MR3R` writer - Reset on MR3: the TC will be reset if MR3 matches it."]
pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>;
impl<'a, REG> Mr3rW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3r::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3r::Disabled)
}
}
#[doc = "Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Mr3s {
#[doc = "1: Enabled"]
Enabled = 1,
#[doc = "0: Disabled"]
Disabled = 0,
}
impl From<Mr3s> for bool {
#[inline(always)]
fn from(variant: Mr3s) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MR3S` reader - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
pub type Mr3sR = crate::BitReader<Mr3s>;
impl Mr3sR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mr3s {
match self.bits {
true => Mr3s::Enabled,
false => Mr3s::Disabled,
}
}
#[doc = "Enabled"]
#[inline(always)]
pub fn is_enabled(&self) -> bool {
*self == Mr3s::Enabled
}
#[doc = "Disabled"]
#[inline(always)]
pub fn is_disabled(&self) -> bool {
*self == Mr3s::Disabled
}
}
#[doc = "Field `MR3S` writer - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>;
impl<'a, REG> Mr3sW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Enabled"]
#[inline(always)]
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3s::Enabled)
}
#[doc = "Disabled"]
#[inline(always)]
pub fn disabled(self) -> &'a mut crate::W<REG> {
self.variant(Mr3s::Disabled)
}
}
impl R {
#[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
#[inline(always)]
pub fn mr0i(&self) -> Mr0iR {
Mr0iR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
#[inline(always)]
pub fn mr0r(&self) -> Mr0rR {
Mr0rR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
#[inline(always)]
pub fn mr0s(&self) -> Mr0sR {
Mr0sR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
#[inline(always)]
pub fn mr1i(&self) -> Mr1iR {
Mr1iR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
#[inline(always)]
pub fn mr1r(&self) -> Mr1rR {
Mr1rR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
#[inline(always)]
pub fn mr1s(&self) -> Mr1sR {
Mr1sR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
#[inline(always)]
pub fn mr2i(&self) -> Mr2iR {
Mr2iR::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
#[inline(always)]
pub fn mr2r(&self) -> Mr2rR {
Mr2rR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
#[inline(always)]
pub fn mr2s(&self) -> Mr2sR {
Mr2sR::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
#[inline(always)]
pub fn mr3i(&self) -> Mr3iR {
Mr3iR::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
#[inline(always)]
pub fn mr3r(&self) -> Mr3rR {
Mr3rR::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
#[inline(always)]
pub fn mr3s(&self) -> Mr3sR {
Mr3sR::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr0i(&mut self) -> Mr0iW<McrSpec> {
Mr0iW::new(self, 0)
}
#[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
#[inline(always)]
#[must_use]
pub fn mr0r(&mut self) -> Mr0rW<McrSpec> {
Mr0rW::new(self, 1)
}
#[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR0 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr0s(&mut self) -> Mr0sW<McrSpec> {
Mr0sW::new(self, 2)
}
#[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr1i(&mut self) -> Mr1iW<McrSpec> {
Mr1iW::new(self, 3)
}
#[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
#[inline(always)]
#[must_use]
pub fn mr1r(&mut self) -> Mr1rW<McrSpec> {
Mr1rW::new(self, 4)
}
#[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR1 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr1s(&mut self) -> Mr1sW<McrSpec> {
Mr1sW::new(self, 5)
}
#[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr2i(&mut self) -> Mr2iW<McrSpec> {
Mr2iW::new(self, 6)
}
#[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
#[inline(always)]
#[must_use]
pub fn mr2r(&mut self) -> Mr2rW<McrSpec> {
Mr2rW::new(self, 7)
}
#[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR2 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr2s(&mut self) -> Mr2sW<McrSpec> {
Mr2sW::new(self, 8)
}
#[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
#[inline(always)]
#[must_use]
pub fn mr3i(&mut self) -> Mr3iW<McrSpec> {
Mr3iW::new(self, 9)
}
#[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
#[inline(always)]
#[must_use]
pub fn mr3r(&mut self) -> Mr3rW<McrSpec> {
Mr3rW::new(self, 10)
}
#[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
will be set to 0 if MR3 matches the TC."]
#[inline(always)]
#[must_use]
pub fn mr3s(&mut self) -> Mr3sW<McrSpec> {
Mr3sW::new(self, 11)
}
}
#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct McrSpec;
impl crate::RegisterSpec for McrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mcr::R`](R) reader structure"]
impl crate::Readable for McrSpec {}
#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
impl crate::Writable for McrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MCR to value 0"]
impl crate::Resettable for McrSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct32b0/mr.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `MR%s` reader"]
pub type R = crate::R<MrSpec>;
#[doc = "Register `MR%s` writer"]
pub type W = crate::W<MrSpec>;
#[doc = "Field `MATCH` reader - Timer counter match value."]
pub type MatchR = crate::FieldReader<u32>;
#[doc = "Field `MATCH` writer - Timer counter match value."]
pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline(always)]
pub fn match_(&self) -> MatchR {
MatchR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Timer counter match value."]
#[inline(always)]
#[must_use]
pub fn match_(&mut self) -> MatchW<MrSpec> {
MatchW::new(self, 0)
}
}
#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MrSpec;
impl crate::RegisterSpec for MrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
impl crate::Readable for MrSpec {}
#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
impl crate::Writable for MrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MR%s to value 0"]
impl crate::Resettable for MrSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct32b0/pc.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `PC` reader"]
pub type R = crate::R<PcSpec>;
#[doc = "Register `PC` writer"]
pub type W = crate::W<PcSpec>;
#[doc = "Field `PC` reader - Prescale counter value."]
pub type PcR = crate::FieldReader<u32>;
#[doc = "Field `PC` writer - Prescale counter value."]
pub type PcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline(always)]
pub fn pc(&self) -> PcR {
PcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Prescale counter value."]
#[inline(always)]
#[must_use]
pub fn pc(&mut self) -> PcW<PcSpec> {
PcW::new(self, 0)
}
}
#[doc = "Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PcSpec;
impl crate::RegisterSpec for PcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pc::R`](R) reader structure"]
impl crate::Readable for PcSpec {}
#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"]
impl crate::Writable for PcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PC to value 0"]
impl crate::Resettable for PcSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct32b0/pr.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `PR` reader"]
pub type R = crate::R<PrSpec>;
#[doc = "Register `PR` writer"]
pub type W = crate::W<PrSpec>;
#[doc = "Field `PR` reader - Prescale value."]
pub type PrR = crate::FieldReader<u32>;
#[doc = "Field `PR` writer - Prescale value."]
pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Prescale value."]
#[inline(always)]
pub fn pr(&self) -> PrR {
PrR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Prescale value."]
#[inline(always)]
#[must_use]
pub fn pr(&mut self) -> PrW<PrSpec> {
PrW::new(self, 0)
}
}
#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PrSpec;
impl crate::RegisterSpec for PrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pr::R`](R) reader structure"]
impl crate::Readable for PrSpec {}
#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"]
impl crate::Writable for PrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PR to value 0"]
impl crate::Resettable for PrSpec {
const RESET_VALUE: u32 = 0;
}

281
rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs Normal file
View file

@ -0,0 +1,281 @@
#[doc = "Register `PWMC` reader"]
pub type R = crate::R<PwmcSpec>;
#[doc = "Register `PWMC` writer"]
pub type W = crate::W<PwmcSpec>;
#[doc = "PWM channel 0 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen0 {
#[doc = "0: CT32Bn_MAT0 is controlled by EM0."]
Ct32bnMat0IsContr = 0,
#[doc = "1: PWM mode is enabled for CT32Bn_MAT0."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen0> for bool {
#[inline(always)]
fn from(variant: Pwmen0) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN0` reader - PWM channel 0 enable"]
pub type Pwmen0R = crate::BitReader<Pwmen0>;
impl Pwmen0R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen0 {
match self.bits {
false => Pwmen0::Ct32bnMat0IsContr,
true => Pwmen0::PwmModeIsEnabled_,
}
}
#[doc = "CT32Bn_MAT0 is controlled by EM0."]
#[inline(always)]
pub fn is_ct32bn_mat0_is_contr(&self) -> bool {
*self == Pwmen0::Ct32bnMat0IsContr
}
#[doc = "PWM mode is enabled for CT32Bn_MAT0."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen0::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN0` writer - PWM channel 0 enable"]
pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>;
impl<'a, REG> Pwmen0W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT32Bn_MAT0 is controlled by EM0."]
#[inline(always)]
pub fn ct32bn_mat0_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen0::Ct32bnMat0IsContr)
}
#[doc = "PWM mode is enabled for CT32Bn_MAT0."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen0::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel 1 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen1 {
#[doc = "0: CT32Bn_MAT1 is controlled by EM1."]
Ct32bnMat1IsContr = 0,
#[doc = "1: PWM mode is enabled for CT32Bn_MAT1."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen1> for bool {
#[inline(always)]
fn from(variant: Pwmen1) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN1` reader - PWM channel 1 enable"]
pub type Pwmen1R = crate::BitReader<Pwmen1>;
impl Pwmen1R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen1 {
match self.bits {
false => Pwmen1::Ct32bnMat1IsContr,
true => Pwmen1::PwmModeIsEnabled_,
}
}
#[doc = "CT32Bn_MAT1 is controlled by EM1."]
#[inline(always)]
pub fn is_ct32bn_mat1_is_contr(&self) -> bool {
*self == Pwmen1::Ct32bnMat1IsContr
}
#[doc = "PWM mode is enabled for CT32Bn_MAT1."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen1::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN1` writer - PWM channel 1 enable"]
pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>;
impl<'a, REG> Pwmen1W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT32Bn_MAT1 is controlled by EM1."]
#[inline(always)]
pub fn ct32bn_mat1_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen1::Ct32bnMat1IsContr)
}
#[doc = "PWM mode is enabled for CT32Bn_MAT1."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen1::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel 2 enable\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen2 {
#[doc = "0: CT32Bn_MAT2 is controlled by EM2."]
Ct32bnMat2IsContr = 0,
#[doc = "1: PWM mode is enabled for CT32Bn_MAT2."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen2> for bool {
#[inline(always)]
fn from(variant: Pwmen2) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN2` reader - PWM channel 2 enable"]
pub type Pwmen2R = crate::BitReader<Pwmen2>;
impl Pwmen2R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen2 {
match self.bits {
false => Pwmen2::Ct32bnMat2IsContr,
true => Pwmen2::PwmModeIsEnabled_,
}
}
#[doc = "CT32Bn_MAT2 is controlled by EM2."]
#[inline(always)]
pub fn is_ct32bn_mat2_is_contr(&self) -> bool {
*self == Pwmen2::Ct32bnMat2IsContr
}
#[doc = "PWM mode is enabled for CT32Bn_MAT2."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen2::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN2` writer - PWM channel 2 enable"]
pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>;
impl<'a, REG> Pwmen2W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT32Bn_MAT2 is controlled by EM2."]
#[inline(always)]
pub fn ct32bn_mat2_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen2::Ct32bnMat2IsContr)
}
#[doc = "PWM mode is enabled for CT32Bn_MAT2."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen2::PwmModeIsEnabled_)
}
}
#[doc = "PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Pwmen3 {
#[doc = "0: CT32Bn_MAT3 is controlled by EM3."]
Ct32bnMat3IsContr = 0,
#[doc = "1: PWM mode is enabled for CT32Bn_MAT3."]
PwmModeIsEnabled_ = 1,
}
impl From<Pwmen3> for bool {
#[inline(always)]
fn from(variant: Pwmen3) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `PWMEN3` reader - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."]
pub type Pwmen3R = crate::BitReader<Pwmen3>;
impl Pwmen3R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Pwmen3 {
match self.bits {
false => Pwmen3::Ct32bnMat3IsContr,
true => Pwmen3::PwmModeIsEnabled_,
}
}
#[doc = "CT32Bn_MAT3 is controlled by EM3."]
#[inline(always)]
pub fn is_ct32bn_mat3_is_contr(&self) -> bool {
*self == Pwmen3::Ct32bnMat3IsContr
}
#[doc = "PWM mode is enabled for CT32Bn_MAT3."]
#[inline(always)]
pub fn is_pwm_mode_is_enabled_(&self) -> bool {
*self == Pwmen3::PwmModeIsEnabled_
}
}
#[doc = "Field `PWMEN3` writer - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."]
pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>;
impl<'a, REG> Pwmen3W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "CT32Bn_MAT3 is controlled by EM3."]
#[inline(always)]
pub fn ct32bn_mat3_is_contr(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen3::Ct32bnMat3IsContr)
}
#[doc = "PWM mode is enabled for CT32Bn_MAT3."]
#[inline(always)]
pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W<REG> {
self.variant(Pwmen3::PwmModeIsEnabled_)
}
}
impl R {
#[doc = "Bit 0 - PWM channel 0 enable"]
#[inline(always)]
pub fn pwmen0(&self) -> Pwmen0R {
Pwmen0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - PWM channel 1 enable"]
#[inline(always)]
pub fn pwmen1(&self) -> Pwmen1R {
Pwmen1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - PWM channel 2 enable"]
#[inline(always)]
pub fn pwmen2(&self) -> Pwmen2R {
Pwmen2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."]
#[inline(always)]
pub fn pwmen3(&self) -> Pwmen3R {
Pwmen3R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - PWM channel 0 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen0(&mut self) -> Pwmen0W<PwmcSpec> {
Pwmen0W::new(self, 0)
}
#[doc = "Bit 1 - PWM channel 1 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen1(&mut self) -> Pwmen1W<PwmcSpec> {
Pwmen1W::new(self, 1)
}
#[doc = "Bit 2 - PWM channel 2 enable"]
#[inline(always)]
#[must_use]
pub fn pwmen2(&mut self) -> Pwmen2W<PwmcSpec> {
Pwmen2W::new(self, 2)
}
#[doc = "Bit 3 - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."]
#[inline(always)]
#[must_use]
pub fn pwmen3(&mut self) -> Pwmen3W<PwmcSpec> {
Pwmen3W::new(self, 3)
}
}
#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmcSpec;
impl crate::RegisterSpec for PwmcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"]
impl crate::Readable for PwmcSpec {}
#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"]
impl crate::Writable for PwmcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PWMC to value 0"]
impl crate::Resettable for PwmcSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/ct32b0/tc.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `TC` reader"]
pub type R = crate::R<TcSpec>;
#[doc = "Register `TC` writer"]
pub type W = crate::W<TcSpec>;
#[doc = "Field `TC` reader - Timer counter value."]
pub type TcR = crate::FieldReader<u32>;
#[doc = "Field `TC` writer - Timer counter value."]
pub type TcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
impl R {
#[doc = "Bits 0:31 - Timer counter value."]
#[inline(always)]
pub fn tc(&self) -> TcR {
TcR::new(self.bits)
}
}
impl W {
#[doc = "Bits 0:31 - Timer counter value."]
#[inline(always)]
#[must_use]
pub fn tc(&mut self) -> TcW<TcSpec> {
TcW::new(self, 0)
}
}
#[doc = "Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcSpec;
impl crate::RegisterSpec for TcSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tc::R`](R) reader structure"]
impl crate::Readable for TcSpec {}
#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"]
impl crate::Writable for TcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TC to value 0"]
impl crate::Resettable for TcSpec {
const RESET_VALUE: u32 = 0;
}

59
rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs Normal file
View file

@ -0,0 +1,59 @@
#[doc = "Register `TCR` reader"]
pub type R = crate::R<TcrSpec>;
#[doc = "Register `TCR` writer"]
pub type W = crate::W<TcrSpec>;
#[doc = "Field `CEN` reader - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CenR = crate::BitReader;
#[doc = "Field `CEN` writer - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
pub type CenW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CRST` reader - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CrstR = crate::BitReader;
#[doc = "Field `CRST` writer - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
pub type CrstW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
pub fn cen(&self) -> CenR {
CenR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
pub fn crst(&self) -> CrstR {
CrstR::new(((self.bits >> 1) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."]
#[inline(always)]
#[must_use]
pub fn cen(&mut self) -> CenW<TcrSpec> {
CenW::new(self, 0)
}
#[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\]
is returned to zero."]
#[inline(always)]
#[must_use]
pub fn crst(&mut self) -> CrstW<TcrSpec> {
CrstW::new(self, 1)
}
}
#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TcrSpec;
impl crate::RegisterSpec for TcrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`tcr::R`](R) reader structure"]
impl crate::Readable for TcrSpec {}
#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"]
impl crate::Writable for TcrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets TCR to value 0"]
impl crate::Resettable for TcrSpec {
const RESET_VALUE: u32 = 0;
}

119
rust-embedded/lpc111x-pac/src/flashctrl.rs Normal file
View file

@ -0,0 +1,119 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x10],
flashcfg: Flashcfg,
_reserved1: [u8; 0x0c],
fmsstart: Fmsstart,
fmsstop: Fmsstop,
_reserved3: [u8; 0x04],
fmsw0: Fmsw0,
fmsw1: Fmsw1,
fmsw2: Fmsw2,
fmsw3: Fmsw3,
_reserved7: [u8; 0x0fa4],
fmstat: Fmstat,
_reserved8: [u8; 0x04],
fmstatclr: Fmstatclr,
}
impl RegisterBlock {
#[doc = "0x10 - Flash memory access time configuration register"]
#[inline(always)]
pub const fn flashcfg(&self) -> &Flashcfg {
&self.flashcfg
}
#[doc = "0x20 - Signature start address register"]
#[inline(always)]
pub const fn fmsstart(&self) -> &Fmsstart {
&self.fmsstart
}
#[doc = "0x24 - Signature stop-address register"]
#[inline(always)]
pub const fn fmsstop(&self) -> &Fmsstop {
&self.fmsstop
}
#[doc = "0x2c - Word 0 \\[31:0\\]"]
#[inline(always)]
pub const fn fmsw0(&self) -> &Fmsw0 {
&self.fmsw0
}
#[doc = "0x30 - Word 1 \\[63:32\\]"]
#[inline(always)]
pub const fn fmsw1(&self) -> &Fmsw1 {
&self.fmsw1
}
#[doc = "0x34 - Word 2 \\[95:64\\]"]
#[inline(always)]
pub const fn fmsw2(&self) -> &Fmsw2 {
&self.fmsw2
}
#[doc = "0x38 - Word 3 \\[127:96\\]"]
#[inline(always)]
pub const fn fmsw3(&self) -> &Fmsw3 {
&self.fmsw3
}
#[doc = "0xfe0 - Signature generation status register"]
#[inline(always)]
pub const fn fmstat(&self) -> &Fmstat {
&self.fmstat
}
#[doc = "0xfe8 - Signature generation status clear register"]
#[inline(always)]
pub const fn fmstatclr(&self) -> &Fmstatclr {
&self.fmstatclr
}
}
#[doc = "FLASHCFG (rw) register accessor: Flash memory access time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flashcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flashcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashcfg`]
module"]
#[doc(alias = "FLASHCFG")]
pub type Flashcfg = crate::Reg<flashcfg::FlashcfgSpec>;
#[doc = "Flash memory access time configuration register"]
pub mod flashcfg;
#[doc = "FMSSTART (rw) register accessor: Signature start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstart::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstart::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsstart`]
module"]
#[doc(alias = "FMSSTART")]
pub type Fmsstart = crate::Reg<fmsstart::FmsstartSpec>;
#[doc = "Signature start address register"]
pub mod fmsstart;
#[doc = "FMSSTOP (rw) register accessor: Signature stop-address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstop::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsstop`]
module"]
#[doc(alias = "FMSSTOP")]
pub type Fmsstop = crate::Reg<fmsstop::FmsstopSpec>;
#[doc = "Signature stop-address register"]
pub mod fmsstop;
#[doc = "FMSW0 (r) register accessor: Word 0 \\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw0`]
module"]
#[doc(alias = "FMSW0")]
pub type Fmsw0 = crate::Reg<fmsw0::Fmsw0Spec>;
#[doc = "Word 0 \\[31:0\\]"]
pub mod fmsw0;
#[doc = "FMSW1 (r) register accessor: Word 1 \\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw1`]
module"]
#[doc(alias = "FMSW1")]
pub type Fmsw1 = crate::Reg<fmsw1::Fmsw1Spec>;
#[doc = "Word 1 \\[63:32\\]"]
pub mod fmsw1;
#[doc = "FMSW2 (r) register accessor: Word 2 \\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw2`]
module"]
#[doc(alias = "FMSW2")]
pub type Fmsw2 = crate::Reg<fmsw2::Fmsw2Spec>;
#[doc = "Word 2 \\[95:64\\]"]
pub mod fmsw2;
#[doc = "FMSW3 (r) register accessor: Word 3 \\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw3`]
module"]
#[doc(alias = "FMSW3")]
pub type Fmsw3 = crate::Reg<fmsw3::Fmsw3Spec>;
#[doc = "Word 3 \\[127:96\\]"]
pub mod fmsw3;
#[doc = "FMSTAT (r) register accessor: Signature generation status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmstat`]
module"]
#[doc(alias = "FMSTAT")]
pub type Fmstat = crate::Reg<fmstat::FmstatSpec>;
#[doc = "Signature generation status register"]
pub mod fmstat;
#[doc = "FMSTATCLR (w) register accessor: Signature generation status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmstatclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmstatclr`]
module"]
#[doc(alias = "FMSTATCLR")]
pub type Fmstatclr = crate::Reg<fmstatclr::FmstatclrSpec>;
#[doc = "Signature generation status clear register"]
pub mod fmstatclr;

108
rust-embedded/lpc111x-pac/src/flashctrl/flashcfg.rs Normal file
View file

@ -0,0 +1,108 @@
#[doc = "Register `FLASHCFG` reader"]
pub type R = crate::R<FlashcfgSpec>;
#[doc = "Register `FLASHCFG` writer"]
pub type W = crate::W<FlashcfgSpec>;
#[doc = "Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Flashtim {
#[doc = "1: 1 system clock flash access time (for system clock frequencies of up to 20 MHz)."]
_1SystemClockFlash = 1,
#[doc = "2: 2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."]
_2SystemClocksFlas = 2,
#[doc = "3: 3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."]
_3SystemClocksFlas = 3,
}
impl From<Flashtim> for u8 {
#[inline(always)]
fn from(variant: Flashtim) -> Self {
variant as _
}
}
impl crate::FieldSpec for Flashtim {
type Ux = u8;
}
#[doc = "Field `FLASHTIM` reader - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."]
pub type FlashtimR = crate::FieldReader<Flashtim>;
impl FlashtimR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Flashtim> {
match self.bits {
1 => Some(Flashtim::_1SystemClockFlash),
2 => Some(Flashtim::_2SystemClocksFlas),
3 => Some(Flashtim::_3SystemClocksFlas),
_ => None,
}
}
#[doc = "1 system clock flash access time (for system clock frequencies of up to 20 MHz)."]
#[inline(always)]
pub fn is_1_system_clock_flash(&self) -> bool {
*self == Flashtim::_1SystemClockFlash
}
#[doc = "2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."]
#[inline(always)]
pub fn is_2_system_clocks_flas(&self) -> bool {
*self == Flashtim::_2SystemClocksFlas
}
#[doc = "3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."]
#[inline(always)]
pub fn is_3_system_clocks_flas(&self) -> bool {
*self == Flashtim::_3SystemClocksFlas
}
}
#[doc = "Field `FLASHTIM` writer - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."]
pub type FlashtimW<'a, REG> = crate::FieldWriter<'a, REG, 2, Flashtim>;
impl<'a, REG> FlashtimW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "1 system clock flash access time (for system clock frequencies of up to 20 MHz)."]
#[inline(always)]
pub fn _1_system_clock_flash(self) -> &'a mut crate::W<REG> {
self.variant(Flashtim::_1SystemClockFlash)
}
#[doc = "2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."]
#[inline(always)]
pub fn _2_system_clocks_flas(self) -> &'a mut crate::W<REG> {
self.variant(Flashtim::_2SystemClocksFlas)
}
#[doc = "3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."]
#[inline(always)]
pub fn _3_system_clocks_flas(self) -> &'a mut crate::W<REG> {
self.variant(Flashtim::_3SystemClocksFlas)
}
}
impl R {
#[doc = "Bits 0:1 - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."]
#[inline(always)]
pub fn flashtim(&self) -> FlashtimR {
FlashtimR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."]
#[inline(always)]
#[must_use]
pub fn flashtim(&mut self) -> FlashtimW<FlashcfgSpec> {
FlashtimW::new(self, 0)
}
}
#[doc = "Flash memory access time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flashcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flashcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FlashcfgSpec;
impl crate::RegisterSpec for FlashcfgSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`flashcfg::R`](R) reader structure"]
impl crate::Readable for FlashcfgSpec {}
#[doc = "`write(|w| ..)` method takes [`flashcfg::W`](W) writer structure"]
impl crate::Writable for FlashcfgSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FLASHCFG to value 0"]
impl crate::Resettable for FlashcfgSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/flashctrl/fmsstart.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `FMSSTART` reader"]
pub type R = crate::R<FmsstartSpec>;
#[doc = "Register `FMSSTART` writer"]
pub type W = crate::W<FmsstartSpec>;
#[doc = "Field `START` reader - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."]
pub type StartR = crate::FieldReader<u32>;
#[doc = "Field `START` writer - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."]
pub type StartW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
impl R {
#[doc = "Bits 0:16 - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."]
#[inline(always)]
pub fn start(&self) -> StartR {
StartR::new(self.bits & 0x0001_ffff)
}
}
impl W {
#[doc = "Bits 0:16 - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."]
#[inline(always)]
#[must_use]
pub fn start(&mut self) -> StartW<FmsstartSpec> {
StartW::new(self, 0)
}
}
#[doc = "Signature start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstart::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstart::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FmsstartSpec;
impl crate::RegisterSpec for FmsstartSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsstart::R`](R) reader structure"]
impl crate::Readable for FmsstartSpec {}
#[doc = "`write(|w| ..)` method takes [`fmsstart::W`](W) writer structure"]
impl crate::Writable for FmsstartSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FMSSTART to value 0"]
impl crate::Resettable for FmsstartSpec {
const RESET_VALUE: u32 = 0;
}

104
rust-embedded/lpc111x-pac/src/flashctrl/fmsstop.rs Normal file
View file

@ -0,0 +1,104 @@
#[doc = "Register `FMSSTOP` reader"]
pub type R = crate::R<FmsstopSpec>;
#[doc = "Register `FMSSTOP` writer"]
pub type W = crate::W<FmsstopSpec>;
#[doc = "Field `STOP` reader - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."]
pub type StopR = crate::FieldReader<u32>;
#[doc = "Field `STOP` writer - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."]
pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
#[doc = "Start control bit for signature generation.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum SigStart {
#[doc = "0: Signature generation is stopped"]
SignatureGeneration = 0,
#[doc = "1: Initiate signature generation"]
InitiateSignatureG = 1,
}
impl From<SigStart> for bool {
#[inline(always)]
fn from(variant: SigStart) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `SIG_START` reader - Start control bit for signature generation."]
pub type SigStartR = crate::BitReader<SigStart>;
impl SigStartR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> SigStart {
match self.bits {
false => SigStart::SignatureGeneration,
true => SigStart::InitiateSignatureG,
}
}
#[doc = "Signature generation is stopped"]
#[inline(always)]
pub fn is_signature_generation(&self) -> bool {
*self == SigStart::SignatureGeneration
}
#[doc = "Initiate signature generation"]
#[inline(always)]
pub fn is_initiate_signature_g(&self) -> bool {
*self == SigStart::InitiateSignatureG
}
}
#[doc = "Field `SIG_START` writer - Start control bit for signature generation."]
pub type SigStartW<'a, REG> = crate::BitWriter<'a, REG, SigStart>;
impl<'a, REG> SigStartW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Signature generation is stopped"]
#[inline(always)]
pub fn signature_generation(self) -> &'a mut crate::W<REG> {
self.variant(SigStart::SignatureGeneration)
}
#[doc = "Initiate signature generation"]
#[inline(always)]
pub fn initiate_signature_g(self) -> &'a mut crate::W<REG> {
self.variant(SigStart::InitiateSignatureG)
}
}
impl R {
#[doc = "Bits 0:16 - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."]
#[inline(always)]
pub fn stop(&self) -> StopR {
StopR::new(self.bits & 0x0001_ffff)
}
#[doc = "Bit 17 - Start control bit for signature generation."]
#[inline(always)]
pub fn sig_start(&self) -> SigStartR {
SigStartR::new(((self.bits >> 17) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:16 - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."]
#[inline(always)]
#[must_use]
pub fn stop(&mut self) -> StopW<FmsstopSpec> {
StopW::new(self, 0)
}
#[doc = "Bit 17 - Start control bit for signature generation."]
#[inline(always)]
#[must_use]
pub fn sig_start(&mut self) -> SigStartW<FmsstopSpec> {
SigStartW::new(self, 17)
}
}
#[doc = "Signature stop-address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstop::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FmsstopSpec;
impl crate::RegisterSpec for FmsstopSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsstop::R`](R) reader structure"]
impl crate::Readable for FmsstopSpec {}
#[doc = "`write(|w| ..)` method takes [`fmsstop::W`](W) writer structure"]
impl crate::Writable for FmsstopSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FMSSTOP to value 0"]
impl crate::Resettable for FmsstopSpec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/flashctrl/fmstat.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `FMSTAT` reader"]
pub type R = crate::R<FmstatSpec>;
#[doc = "Field `SIG_DONE` reader - When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag."]
pub type SigDoneR = crate::BitReader;
impl R {
#[doc = "Bit 2 - When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag."]
#[inline(always)]
pub fn sig_done(&self) -> SigDoneR {
SigDoneR::new(((self.bits >> 2) & 1) != 0)
}
}
#[doc = "Signature generation status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FmstatSpec;
impl crate::RegisterSpec for FmstatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmstat::R`](R) reader structure"]
impl crate::Readable for FmstatSpec {}
#[doc = "`reset()` method sets FMSTAT to value 0"]
impl crate::Resettable for FmstatSpec {
const RESET_VALUE: u32 = 0;
}

27
rust-embedded/lpc111x-pac/src/flashctrl/fmstatclr.rs Normal file
View file

@ -0,0 +1,27 @@
#[doc = "Register `FMSTATCLR` writer"]
pub type W = crate::W<FmstatclrSpec>;
#[doc = "Field `SIG_DONE_CLR` writer - Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register."]
pub type SigDoneClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 2 - Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register."]
#[inline(always)]
#[must_use]
pub fn sig_done_clr(&mut self) -> SigDoneClrW<FmstatclrSpec> {
SigDoneClrW::new(self, 2)
}
}
#[doc = "Signature generation status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmstatclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FmstatclrSpec;
impl crate::RegisterSpec for FmstatclrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`fmstatclr::W`](W) writer structure"]
impl crate::Writable for FmstatclrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets FMSTATCLR to value 0"]
impl crate::Resettable for FmstatclrSpec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/flashctrl/fmsw0.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `FMSW0` reader"]
pub type R = crate::R<Fmsw0Spec>;
#[doc = "Field `SW0_31_0` reader - Word 0 of 128-bit signature (bits 31 to 0)."]
pub type Sw0_31_0R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Word 0 of 128-bit signature (bits 31 to 0)."]
#[inline(always)]
pub fn sw0_31_0(&self) -> Sw0_31_0R {
Sw0_31_0R::new(self.bits)
}
}
#[doc = "Word 0 \\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Fmsw0Spec;
impl crate::RegisterSpec for Fmsw0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsw0::R`](R) reader structure"]
impl crate::Readable for Fmsw0Spec {}
#[doc = "`reset()` method sets FMSW0 to value 0"]
impl crate::Resettable for Fmsw0Spec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/flashctrl/fmsw1.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `FMSW1` reader"]
pub type R = crate::R<Fmsw1Spec>;
#[doc = "Field `SW1_63_32` reader - Word 1 of 128-bit signature (bits 63 to 32)."]
pub type Sw1_63_32R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Word 1 of 128-bit signature (bits 63 to 32)."]
#[inline(always)]
pub fn sw1_63_32(&self) -> Sw1_63_32R {
Sw1_63_32R::new(self.bits)
}
}
#[doc = "Word 1 \\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Fmsw1Spec;
impl crate::RegisterSpec for Fmsw1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsw1::R`](R) reader structure"]
impl crate::Readable for Fmsw1Spec {}
#[doc = "`reset()` method sets FMSW1 to value 0"]
impl crate::Resettable for Fmsw1Spec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/flashctrl/fmsw2.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `FMSW2` reader"]
pub type R = crate::R<Fmsw2Spec>;
#[doc = "Field `SW2_95_64` reader - Word 2 of 128-bit signature (bits 95 to 64)."]
pub type Sw2_95_64R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Word 2 of 128-bit signature (bits 95 to 64)."]
#[inline(always)]
pub fn sw2_95_64(&self) -> Sw2_95_64R {
Sw2_95_64R::new(self.bits)
}
}
#[doc = "Word 2 \\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Fmsw2Spec;
impl crate::RegisterSpec for Fmsw2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsw2::R`](R) reader structure"]
impl crate::Readable for Fmsw2Spec {}
#[doc = "`reset()` method sets FMSW2 to value 0"]
impl crate::Resettable for Fmsw2Spec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/flashctrl/fmsw3.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `FMSW3` reader"]
pub type R = crate::R<Fmsw3Spec>;
#[doc = "Field `SW3_127_96` reader - Word 3 of 128-bit signature (bits 127 to 96)."]
pub type Sw3_127_96R = crate::FieldReader<u32>;
impl R {
#[doc = "Bits 0:31 - Word 3 of 128-bit signature (bits 127 to 96)."]
#[inline(always)]
pub fn sw3_127_96(&self) -> Sw3_127_96R {
Sw3_127_96R::new(self.bits)
}
}
#[doc = "Word 3 \\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Fmsw3Spec;
impl crate::RegisterSpec for Fmsw3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`fmsw3::R`](R) reader structure"]
impl crate::Readable for Fmsw3Spec {}
#[doc = "`reset()` method sets FMSW3 to value 0"]
impl crate::Resettable for Fmsw3Spec {
const RESET_VALUE: u32 = 0;
}

547
rust-embedded/lpc111x-pac/src/generic.rs Normal file
View file

@ -0,0 +1,547 @@
use core::marker;
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg:
Copy
+ Default
+ From<bool>
+ core::ops::BitOr<Output = Self>
+ core::ops::BitAnd<Output = Self>
+ core::ops::BitOrAssign
+ core::ops::BitAndAssign
+ core::ops::Not<Output = Self>
+ core::ops::Shl<u8, Output = Self>
{
#[doc = " Mask for bits of width `WI`"]
fn mask<const WI: u8>() -> Self;
#[doc = " Mask for bits of width 1"]
fn one() -> Self;
}
macro_rules! raw_reg {
($ U : ty , $ size : literal , $ mask : ident) => {
impl RawReg for $U {
#[inline(always)]
fn mask<const WI: u8>() -> Self {
$mask::<WI>()
}
#[inline(always)]
fn one() -> Self {
1
}
}
const fn $mask<const WI: u8>() -> $U {
<$U>::MAX >> ($size - WI)
}
impl FieldSpec for $U {
type Ux = $U;
}
};
}
raw_reg!(u8, 8, mask_u8);
raw_reg!(u16, 16, mask_u16);
raw_reg!(u32, 32, mask_u32);
raw_reg!(u64, 64, mask_u64);
#[doc = " Raw register type"]
pub trait RegisterSpec {
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux: RawReg;
}
#[doc = " Raw field type"]
pub trait FieldSpec: Sized {
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux: Copy + PartialEq + From<Self>;
}
#[doc = " Trait implemented by readable registers to enable the `read` method."]
#[doc = ""]
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable: RegisterSpec {}
#[doc = " Trait implemented by writeable registers."]
#[doc = ""]
#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
#[doc = ""]
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable: RegisterSpec {
#[doc = " Is it safe to write any bits to register"]
type Safety;
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
}
#[doc = " Reset value of the register."]
#[doc = ""]
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
#[doc = " register by using the `reset` method."]
pub trait Resettable: RegisterSpec {
#[doc = " Reset value of the register."]
const RESET_VALUE: Self::Ux;
#[doc = " Reset value of the register."]
#[inline(always)]
fn reset_value() -> Self::Ux {
Self::RESET_VALUE
}
}
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
self.register.set(
f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits,
);
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
self.register.set(
f(&mut W {
bits: REG::Ux::default(),
_reg: marker::PhantomData,
})
.bits,
);
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
self.register.set(
f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits,
);
}
}
#[doc(hidden)]
pub mod raw;
#[doc = " Register reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
#[doc = " method."]
pub type R<REG> = raw::R<REG>;
impl<REG: RegisterSpec> R<REG> {
#[doc = " Reads raw bits from register."]
#[inline(always)]
pub const fn bits(&self) -> REG::Ux {
self.bits
}
}
impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
where
REG::Ux: PartialEq,
FI: Copy,
REG::Ux: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&REG::Ux::from(*other))
}
}
#[doc = " Register writer."]
#[doc = ""]
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W<REG> = raw::W<REG>;
impl<REG: Writable> W<REG> {
#[doc = " Writes raw bits to the register."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
impl<REG> W<REG>
where
REG: Writable<Safety = Safe>,
{
#[doc = " Writes raw bits to the register."]
#[inline(always)]
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = " Field reader."]
#[doc = ""]
#[doc = " Result of the `read` methods of fields."]
pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
#[doc = " Bit-wise field reader"]
pub type BitReader<FI = bool> = raw::BitReader<FI>;
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Reads raw bits from field."]
#[inline(always)]
pub const fn bits(&self) -> FI::Ux {
self.bits
}
}
impl<FI> PartialEq<FI> for FieldReader<FI>
where
FI: FieldSpec + Copy,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&FI::Ux::from(*other))
}
}
impl<FI> PartialEq<FI> for BitReader<FI>
where
FI: Copy,
bool: From<FI>,
{
#[inline(always)]
fn eq(&self, other: &FI) -> bool {
self.bits.eq(&bool::from(*other))
}
}
impl<FI> BitReader<FI> {
#[doc = " Value of the field as raw bits."]
#[inline(always)]
pub const fn bit(&self) -> bool {
self.bits
}
#[doc = " Returns `true` if the bit is clear (0)."]
#[inline(always)]
pub const fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = " Returns `true` if the bit is set (1)."]
#[inline(always)]
pub const fn bit_is_set(&self) -> bool {
self.bit()
}
}
#[doc = " Marker for register/field writers which can take any value of specified width"]
pub struct Safe;
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
pub struct Unsafe;
#[doc = " Write field Proxy with unsafe `bits`"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>;
#[doc = " Write field Proxy with safe `bits`"]
pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>;
impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
WI
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes raw bits to the field"]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
unsafe { self.bits(FI::Ux::from(variant)) }
}
}
impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
REG::Ux: From<FI::Ux>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = WI;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
WI
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
self.bits(FI::Ux::from(variant))
}
}
macro_rules! bit_proxy {
($ writer : ident , $ mwv : ident) => {
#[doc(hidden)]
pub struct $mwv;
#[doc = " Bit-wise write field proxy"]
pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
impl<'a, REG, FI> $writer<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Field width"]
pub const WIDTH: u8 = 1;
#[doc = " Field width"]
#[inline(always)]
pub const fn width(&self) -> u8 {
Self::WIDTH
}
#[doc = " Field offset"]
#[inline(always)]
pub const fn offset(&self) -> u8 {
self.o
}
#[doc = " Writes bit to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::one() << self.o);
self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
self.w
}
#[doc = " Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
self.bit(bool::from(variant))
}
}
};
}
bit_proxy!(BitWriter, BitM);
bit_proxy!(BitWriter1S, Bit1S);
bit_proxy!(BitWriter0C, Bit0C);
bit_proxy!(BitWriter1C, Bit1C);
bit_proxy!(BitWriter0S, Bit0S);
bit_proxy!(BitWriter1T, Bit1T);
bit_proxy!(BitWriter0T, Bit0T);
impl<'a, REG, FI> BitWriter<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::one() << self.o;
self.w
}
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::one() << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::one() << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::one() << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Clears the field bit by passing one"]
#[inline(always)]
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::one() << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Sets the field bit by passing zero"]
#[inline(always)]
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::one() << self.o);
self.w
}
}
impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing one"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits |= REG::Ux::one() << self.o;
self.w
}
}
impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = "Toggle the field bit by passing zero"]
#[inline(always)]
pub fn toggle_bit(self) -> &'a mut W<REG> {
self.w.bits &= !(REG::Ux::one() << self.o);
self.w
}
}

93
rust-embedded/lpc111x-pac/src/generic/raw.rs Normal file
View file

@ -0,0 +1,93 @@
use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable};
pub struct R<REG: RegisterSpec> {
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct W<REG: RegisterSpec> {
#[doc = "Writable bits"]
pub(crate) bits: REG::Ux,
pub(super) _reg: marker::PhantomData<REG>,
}
pub struct FieldReader<FI = u8>
where
FI: FieldSpec,
{
pub(crate) bits: FI::Ux,
_reg: marker::PhantomData<FI>,
}
impl<FI: FieldSpec> FieldReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: FI::Ux) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
pub struct BitReader<FI = bool> {
pub(crate) bits: bool,
_reg: marker::PhantomData<FI>,
}
impl<FI> BitReader<FI> {
#[doc = " Creates a new instance of the reader."]
#[allow(unused)]
#[inline(always)]
pub(crate) const fn new(bits: bool) -> Self {
Self {
bits,
_reg: marker::PhantomData,
}
}
}
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, Safety)>,
}
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
pub(crate) w: &'a mut W<REG>,
pub(crate) o: u8,
_field: marker::PhantomData<(FI, M)>,
}
impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
where
REG: Writable + RegisterSpec,
bool: From<FI>,
{
#[doc = " Creates a new instance of the writer"]
#[allow(unused)]
#[inline(always)]
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
Self {
w,
o,
_field: marker::PhantomData,
}
}
}

116
rust-embedded/lpc111x-pac/src/gpio0.rs Normal file
View file

@ -0,0 +1,116 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
_reserved0: [u8; 0x3ffc],
data: Data,
_reserved1: [u8; 0x4000],
dir: Dir,
is: Is,
ibe: Ibe,
iev: Iev,
ie: Ie,
ris: Ris,
mis: Mis,
ic: Ic,
}
impl RegisterBlock {
#[doc = "0x3ffc - Port n data register for pins PIOn_0 to PIOn_11"]
#[inline(always)]
pub const fn data(&self) -> &Data {
&self.data
}
#[doc = "0x8000 - Data direction register for port n"]
#[inline(always)]
pub const fn dir(&self) -> &Dir {
&self.dir
}
#[doc = "0x8004 - Interrupt sense register for port n"]
#[inline(always)]
pub const fn is(&self) -> &Is {
&self.is
}
#[doc = "0x8008 - Interrupt both edges register for port n"]
#[inline(always)]
pub const fn ibe(&self) -> &Ibe {
&self.ibe
}
#[doc = "0x800c - Interrupt event register for port n"]
#[inline(always)]
pub const fn iev(&self) -> &Iev {
&self.iev
}
#[doc = "0x8010 - Interrupt mask register for port n"]
#[inline(always)]
pub const fn ie(&self) -> &Ie {
&self.ie
}
#[doc = "0x8014 - Raw interrupt status register for port n"]
#[inline(always)]
pub const fn ris(&self) -> &Ris {
&self.ris
}
#[doc = "0x8018 - Masked interrupt status register for port n"]
#[inline(always)]
pub const fn mis(&self) -> &Mis {
&self.mis
}
#[doc = "0x801c - Interrupt clear register for port n"]
#[inline(always)]
pub const fn ic(&self) -> &Ic {
&self.ic
}
}
#[doc = "DATA (rw) register accessor: Port n data register for pins PIOn_0 to PIOn_11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Port n data register for pins PIOn_0 to PIOn_11"]
pub mod data;
#[doc = "DIR (rw) register accessor: Data direction register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dir`]
module"]
#[doc(alias = "DIR")]
pub type Dir = crate::Reg<dir::DirSpec>;
#[doc = "Data direction register for port n"]
pub mod dir;
#[doc = "IS (rw) register accessor: Interrupt sense register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`is::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`is::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@is`]
module"]
#[doc(alias = "IS")]
pub type Is = crate::Reg<is::IsSpec>;
#[doc = "Interrupt sense register for port n"]
pub mod is;
#[doc = "IBE (rw) register accessor: Interrupt both edges register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibe`]
module"]
#[doc(alias = "IBE")]
pub type Ibe = crate::Reg<ibe::IbeSpec>;
#[doc = "Interrupt both edges register for port n"]
pub mod ibe;
#[doc = "IEV (rw) register accessor: Interrupt event register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iev::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iev`]
module"]
#[doc(alias = "IEV")]
pub type Iev = crate::Reg<iev::IevSpec>;
#[doc = "Interrupt event register for port n"]
pub mod iev;
#[doc = "IE (rw) register accessor: Interrupt mask register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`]
module"]
#[doc(alias = "IE")]
pub type Ie = crate::Reg<ie::IeSpec>;
#[doc = "Interrupt mask register for port n"]
pub mod ie;
#[doc = "RIS (r) register accessor: Raw interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
#[doc(alias = "RIS")]
pub type Ris = crate::Reg<ris::RisSpec>;
#[doc = "Raw interrupt status register for port n"]
pub mod ris;
#[doc = "MIS (r) register accessor: Masked interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
#[doc(alias = "MIS")]
pub type Mis = crate::Reg<mis::MisSpec>;
#[doc = "Masked interrupt status register for port n"]
pub mod mis;
#[doc = "IC (w) register accessor: Interrupt clear register for port n\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic`]
module"]
#[doc(alias = "IC")]
pub type Ic = crate::Reg<ic::IcSpec>;
#[doc = "Interrupt clear register for port n"]
pub mod ic;

205
rust-embedded/lpc111x-pac/src/gpio0/data.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `DATA` reader"]
pub type R = crate::R<DataSpec>;
#[doc = "Register `DATA` writer"]
pub type W = crate::W<DataSpec>;
#[doc = "Field `DATA0` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data0R = crate::BitReader;
#[doc = "Field `DATA0` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA1` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data1R = crate::BitReader;
#[doc = "Field `DATA1` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA2` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data2R = crate::BitReader;
#[doc = "Field `DATA2` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA3` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data3R = crate::BitReader;
#[doc = "Field `DATA3` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA4` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data4R = crate::BitReader;
#[doc = "Field `DATA4` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA5` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data5R = crate::BitReader;
#[doc = "Field `DATA5` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA6` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data6R = crate::BitReader;
#[doc = "Field `DATA6` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA7` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data7R = crate::BitReader;
#[doc = "Field `DATA7` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA8` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data8R = crate::BitReader;
#[doc = "Field `DATA8` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA9` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data9R = crate::BitReader;
#[doc = "Field `DATA9` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA10` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data10R = crate::BitReader;
#[doc = "Field `DATA10` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `DATA11` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data11R = crate::BitReader;
#[doc = "Field `DATA11` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
pub type Data11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data0(&self) -> Data0R {
Data0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data1(&self) -> Data1R {
Data1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data2(&self) -> Data2R {
Data2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data3(&self) -> Data3R {
Data3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data4(&self) -> Data4R {
Data4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data5(&self) -> Data5R {
Data5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data6(&self) -> Data6R {
Data6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data7(&self) -> Data7R {
Data7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data8(&self) -> Data8R {
Data8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data9(&self) -> Data9R {
Data9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data10(&self) -> Data10R {
Data10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
pub fn data11(&self) -> Data11R {
Data11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data0(&mut self) -> Data0W<DataSpec> {
Data0W::new(self, 0)
}
#[doc = "Bit 1 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data1(&mut self) -> Data1W<DataSpec> {
Data1W::new(self, 1)
}
#[doc = "Bit 2 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data2(&mut self) -> Data2W<DataSpec> {
Data2W::new(self, 2)
}
#[doc = "Bit 3 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data3(&mut self) -> Data3W<DataSpec> {
Data3W::new(self, 3)
}
#[doc = "Bit 4 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data4(&mut self) -> Data4W<DataSpec> {
Data4W::new(self, 4)
}
#[doc = "Bit 5 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data5(&mut self) -> Data5W<DataSpec> {
Data5W::new(self, 5)
}
#[doc = "Bit 6 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data6(&mut self) -> Data6W<DataSpec> {
Data6W::new(self, 6)
}
#[doc = "Bit 7 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data7(&mut self) -> Data7W<DataSpec> {
Data7W::new(self, 7)
}
#[doc = "Bit 8 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data8(&mut self) -> Data8W<DataSpec> {
Data8W::new(self, 8)
}
#[doc = "Bit 9 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data9(&mut self) -> Data9W<DataSpec> {
Data9W::new(self, 9)
}
#[doc = "Bit 10 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data10(&mut self) -> Data10W<DataSpec> {
Data10W::new(self, 10)
}
#[doc = "Bit 11 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."]
#[inline(always)]
#[must_use]
pub fn data11(&mut self) -> Data11W<DataSpec> {
Data11W::new(self, 11)
}
}
#[doc = "Port n data register for pins PIOn_0 to PIOn_11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data::R`](R) reader structure"]
impl crate::Readable for DataSpec {}
#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
impl crate::Writable for DataSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DATA to value 0"]
impl crate::Resettable for DataSpec {
const RESET_VALUE: u32 = 0;
}

205
rust-embedded/lpc111x-pac/src/gpio0/dir.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `DIR` reader"]
pub type R = crate::R<DirSpec>;
#[doc = "Register `DIR` writer"]
pub type W = crate::W<DirSpec>;
#[doc = "Field `IO0` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io0R = crate::BitReader;
#[doc = "Field `IO0` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO1` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io1R = crate::BitReader;
#[doc = "Field `IO1` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO2` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io2R = crate::BitReader;
#[doc = "Field `IO2` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO3` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io3R = crate::BitReader;
#[doc = "Field `IO3` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO4` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io4R = crate::BitReader;
#[doc = "Field `IO4` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO5` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io5R = crate::BitReader;
#[doc = "Field `IO5` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO6` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io6R = crate::BitReader;
#[doc = "Field `IO6` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO7` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io7R = crate::BitReader;
#[doc = "Field `IO7` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO8` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io8R = crate::BitReader;
#[doc = "Field `IO8` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO9` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io9R = crate::BitReader;
#[doc = "Field `IO9` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO10` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io10R = crate::BitReader;
#[doc = "Field `IO10` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IO11` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io11R = crate::BitReader;
#[doc = "Field `IO11` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
pub type Io11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io0(&self) -> Io0R {
Io0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io1(&self) -> Io1R {
Io1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io2(&self) -> Io2R {
Io2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io3(&self) -> Io3R {
Io3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io4(&self) -> Io4R {
Io4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io5(&self) -> Io5R {
Io5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io6(&self) -> Io6R {
Io6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io7(&self) -> Io7R {
Io7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io8(&self) -> Io8R {
Io8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io9(&self) -> Io9R {
Io9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io10(&self) -> Io10R {
Io10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
pub fn io11(&self) -> Io11R {
Io11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io0(&mut self) -> Io0W<DirSpec> {
Io0W::new(self, 0)
}
#[doc = "Bit 1 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io1(&mut self) -> Io1W<DirSpec> {
Io1W::new(self, 1)
}
#[doc = "Bit 2 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io2(&mut self) -> Io2W<DirSpec> {
Io2W::new(self, 2)
}
#[doc = "Bit 3 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io3(&mut self) -> Io3W<DirSpec> {
Io3W::new(self, 3)
}
#[doc = "Bit 4 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io4(&mut self) -> Io4W<DirSpec> {
Io4W::new(self, 4)
}
#[doc = "Bit 5 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io5(&mut self) -> Io5W<DirSpec> {
Io5W::new(self, 5)
}
#[doc = "Bit 6 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io6(&mut self) -> Io6W<DirSpec> {
Io6W::new(self, 6)
}
#[doc = "Bit 7 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io7(&mut self) -> Io7W<DirSpec> {
Io7W::new(self, 7)
}
#[doc = "Bit 8 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io8(&mut self) -> Io8W<DirSpec> {
Io8W::new(self, 8)
}
#[doc = "Bit 9 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io9(&mut self) -> Io9W<DirSpec> {
Io9W::new(self, 9)
}
#[doc = "Bit 10 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io10(&mut self) -> Io10W<DirSpec> {
Io10W::new(self, 10)
}
#[doc = "Bit 11 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."]
#[inline(always)]
#[must_use]
pub fn io11(&mut self) -> Io11W<DirSpec> {
Io11W::new(self, 11)
}
}
#[doc = "Data direction register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DirSpec;
impl crate::RegisterSpec for DirSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dir::R`](R) reader structure"]
impl crate::Readable for DirSpec {}
#[doc = "`write(|w| ..)` method takes [`dir::W`](W) writer structure"]
impl crate::Writable for DirSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DIR to value 0"]
impl crate::Resettable for DirSpec {
const RESET_VALUE: u32 = 0;
}

205
rust-embedded/lpc111x-pac/src/gpio0/ibe.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `IBE` reader"]
pub type R = crate::R<IbeSpec>;
#[doc = "Register `IBE` writer"]
pub type W = crate::W<IbeSpec>;
#[doc = "Field `IBE0` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe0R = crate::BitReader;
#[doc = "Field `IBE0` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE1` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe1R = crate::BitReader;
#[doc = "Field `IBE1` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE2` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe2R = crate::BitReader;
#[doc = "Field `IBE2` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE3` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe3R = crate::BitReader;
#[doc = "Field `IBE3` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE4` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe4R = crate::BitReader;
#[doc = "Field `IBE4` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE5` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe5R = crate::BitReader;
#[doc = "Field `IBE5` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE6` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe6R = crate::BitReader;
#[doc = "Field `IBE6` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE7` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe7R = crate::BitReader;
#[doc = "Field `IBE7` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE8` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe8R = crate::BitReader;
#[doc = "Field `IBE8` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE9` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe9R = crate::BitReader;
#[doc = "Field `IBE9` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE10` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe10R = crate::BitReader;
#[doc = "Field `IBE10` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IBE11` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe11R = crate::BitReader;
#[doc = "Field `IBE11` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
pub type Ibe11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe0(&self) -> Ibe0R {
Ibe0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe1(&self) -> Ibe1R {
Ibe1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe2(&self) -> Ibe2R {
Ibe2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe3(&self) -> Ibe3R {
Ibe3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe4(&self) -> Ibe4R {
Ibe4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe5(&self) -> Ibe5R {
Ibe5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe6(&self) -> Ibe6R {
Ibe6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe7(&self) -> Ibe7R {
Ibe7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe8(&self) -> Ibe8R {
Ibe8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe9(&self) -> Ibe9R {
Ibe9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe10(&self) -> Ibe10R {
Ibe10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn ibe11(&self) -> Ibe11R {
Ibe11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe0(&mut self) -> Ibe0W<IbeSpec> {
Ibe0W::new(self, 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe1(&mut self) -> Ibe1W<IbeSpec> {
Ibe1W::new(self, 1)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe2(&mut self) -> Ibe2W<IbeSpec> {
Ibe2W::new(self, 2)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe3(&mut self) -> Ibe3W<IbeSpec> {
Ibe3W::new(self, 3)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe4(&mut self) -> Ibe4W<IbeSpec> {
Ibe4W::new(self, 4)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe5(&mut self) -> Ibe5W<IbeSpec> {
Ibe5W::new(self, 5)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe6(&mut self) -> Ibe6W<IbeSpec> {
Ibe6W::new(self, 6)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe7(&mut self) -> Ibe7W<IbeSpec> {
Ibe7W::new(self, 7)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe8(&mut self) -> Ibe8W<IbeSpec> {
Ibe8W::new(self, 8)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe9(&mut self) -> Ibe9W<IbeSpec> {
Ibe9W::new(self, 9)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe10(&mut self) -> Ibe10W<IbeSpec> {
Ibe10W::new(self, 10)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn ibe11(&mut self) -> Ibe11W<IbeSpec> {
Ibe11W::new(self, 11)
}
}
#[doc = "Interrupt both edges register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IbeSpec;
impl crate::RegisterSpec for IbeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ibe::R`](R) reader structure"]
impl crate::Readable for IbeSpec {}
#[doc = "`write(|w| ..)` method takes [`ibe::W`](W) writer structure"]
impl crate::Writable for IbeSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IBE to value 0"]
impl crate::Resettable for IbeSpec {
const RESET_VALUE: u32 = 0;
}

115
rust-embedded/lpc111x-pac/src/gpio0/ic.rs Normal file
View file

@ -0,0 +1,115 @@
#[doc = "Register `IC` writer"]
pub type W = crate::W<IcSpec>;
#[doc = "Field `CLR0` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR1` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR2` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR3` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR4` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR5` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR6` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR7` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR8` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR9` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR10` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `CLR11` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
pub type Clr11W<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr0(&mut self) -> Clr0W<IcSpec> {
Clr0W::new(self, 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr1(&mut self) -> Clr1W<IcSpec> {
Clr1W::new(self, 1)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr2(&mut self) -> Clr2W<IcSpec> {
Clr2W::new(self, 2)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr3(&mut self) -> Clr3W<IcSpec> {
Clr3W::new(self, 3)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr4(&mut self) -> Clr4W<IcSpec> {
Clr4W::new(self, 4)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr5(&mut self) -> Clr5W<IcSpec> {
Clr5W::new(self, 5)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr6(&mut self) -> Clr6W<IcSpec> {
Clr6W::new(self, 6)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr7(&mut self) -> Clr7W<IcSpec> {
Clr7W::new(self, 7)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr8(&mut self) -> Clr8W<IcSpec> {
Clr8W::new(self, 8)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr9(&mut self) -> Clr9W<IcSpec> {
Clr9W::new(self, 9)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr10(&mut self) -> Clr10W<IcSpec> {
Clr10W::new(self, 10)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."]
#[inline(always)]
#[must_use]
pub fn clr11(&mut self) -> Clr11W<IcSpec> {
Clr11W::new(self, 11)
}
}
#[doc = "Interrupt clear register for port n\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IcSpec;
impl crate::RegisterSpec for IcSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`ic::W`](W) writer structure"]
impl crate::Writable for IcSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IC to value 0"]
impl crate::Resettable for IcSpec {
const RESET_VALUE: u32 = 0;
}

205
rust-embedded/lpc111x-pac/src/gpio0/ie.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `IE` reader"]
pub type R = crate::R<IeSpec>;
#[doc = "Register `IE` writer"]
pub type W = crate::W<IeSpec>;
#[doc = "Field `MASK0` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask0R = crate::BitReader;
#[doc = "Field `MASK0` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK1` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask1R = crate::BitReader;
#[doc = "Field `MASK1` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK2` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask2R = crate::BitReader;
#[doc = "Field `MASK2` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK3` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask3R = crate::BitReader;
#[doc = "Field `MASK3` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK4` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask4R = crate::BitReader;
#[doc = "Field `MASK4` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK5` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask5R = crate::BitReader;
#[doc = "Field `MASK5` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK6` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask6R = crate::BitReader;
#[doc = "Field `MASK6` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK7` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask7R = crate::BitReader;
#[doc = "Field `MASK7` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK8` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask8R = crate::BitReader;
#[doc = "Field `MASK8` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK9` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask9R = crate::BitReader;
#[doc = "Field `MASK9` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK10` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask10R = crate::BitReader;
#[doc = "Field `MASK10` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MASK11` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask11R = crate::BitReader;
#[doc = "Field `MASK11` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
pub type Mask11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask0(&self) -> Mask0R {
Mask0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask1(&self) -> Mask1R {
Mask1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask2(&self) -> Mask2R {
Mask2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask3(&self) -> Mask3R {
Mask3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask4(&self) -> Mask4R {
Mask4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask5(&self) -> Mask5R {
Mask5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask6(&self) -> Mask6R {
Mask6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask7(&self) -> Mask7R {
Mask7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask8(&self) -> Mask8R {
Mask8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask9(&self) -> Mask9R {
Mask9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask10(&self) -> Mask10R {
Mask10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
pub fn mask11(&self) -> Mask11R {
Mask11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask0(&mut self) -> Mask0W<IeSpec> {
Mask0W::new(self, 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask1(&mut self) -> Mask1W<IeSpec> {
Mask1W::new(self, 1)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask2(&mut self) -> Mask2W<IeSpec> {
Mask2W::new(self, 2)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask3(&mut self) -> Mask3W<IeSpec> {
Mask3W::new(self, 3)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask4(&mut self) -> Mask4W<IeSpec> {
Mask4W::new(self, 4)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask5(&mut self) -> Mask5W<IeSpec> {
Mask5W::new(self, 5)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask6(&mut self) -> Mask6W<IeSpec> {
Mask6W::new(self, 6)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask7(&mut self) -> Mask7W<IeSpec> {
Mask7W::new(self, 7)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask8(&mut self) -> Mask8W<IeSpec> {
Mask8W::new(self, 8)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask9(&mut self) -> Mask9W<IeSpec> {
Mask9W::new(self, 9)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask10(&mut self) -> Mask10W<IeSpec> {
Mask10W::new(self, 10)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."]
#[inline(always)]
#[must_use]
pub fn mask11(&mut self) -> Mask11W<IeSpec> {
Mask11W::new(self, 11)
}
}
#[doc = "Interrupt mask register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IeSpec;
impl crate::RegisterSpec for IeSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ie::R`](R) reader structure"]
impl crate::Readable for IeSpec {}
#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"]
impl crate::Writable for IeSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IE to value 0"]
impl crate::Resettable for IeSpec {
const RESET_VALUE: u32 = 0;
}

205
rust-embedded/lpc111x-pac/src/gpio0/iev.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `IEV` reader"]
pub type R = crate::R<IevSpec>;
#[doc = "Register `IEV` writer"]
pub type W = crate::W<IevSpec>;
#[doc = "Field `IEV0` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev0R = crate::BitReader;
#[doc = "Field `IEV0` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV1` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev1R = crate::BitReader;
#[doc = "Field `IEV1` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV2` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev2R = crate::BitReader;
#[doc = "Field `IEV2` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV3` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev3R = crate::BitReader;
#[doc = "Field `IEV3` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV4` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev4R = crate::BitReader;
#[doc = "Field `IEV4` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV5` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev5R = crate::BitReader;
#[doc = "Field `IEV5` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV6` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev6R = crate::BitReader;
#[doc = "Field `IEV6` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV7` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev7R = crate::BitReader;
#[doc = "Field `IEV7` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV8` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev8R = crate::BitReader;
#[doc = "Field `IEV8` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV9` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev9R = crate::BitReader;
#[doc = "Field `IEV9` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV10` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev10R = crate::BitReader;
#[doc = "Field `IEV10` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `IEV11` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev11R = crate::BitReader;
#[doc = "Field `IEV11` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
pub type Iev11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev0(&self) -> Iev0R {
Iev0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev1(&self) -> Iev1R {
Iev1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev2(&self) -> Iev2R {
Iev2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev3(&self) -> Iev3R {
Iev3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev4(&self) -> Iev4R {
Iev4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev5(&self) -> Iev5R {
Iev5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev6(&self) -> Iev6R {
Iev6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev7(&self) -> Iev7R {
Iev7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev8(&self) -> Iev8R {
Iev8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev9(&self) -> Iev9R {
Iev9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev10(&self) -> Iev10R {
Iev10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
pub fn iev11(&self) -> Iev11R {
Iev11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev0(&mut self) -> Iev0W<IevSpec> {
Iev0W::new(self, 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev1(&mut self) -> Iev1W<IevSpec> {
Iev1W::new(self, 1)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev2(&mut self) -> Iev2W<IevSpec> {
Iev2W::new(self, 2)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev3(&mut self) -> Iev3W<IevSpec> {
Iev3W::new(self, 3)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev4(&mut self) -> Iev4W<IevSpec> {
Iev4W::new(self, 4)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev5(&mut self) -> Iev5W<IevSpec> {
Iev5W::new(self, 5)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev6(&mut self) -> Iev6W<IevSpec> {
Iev6W::new(self, 6)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev7(&mut self) -> Iev7W<IevSpec> {
Iev7W::new(self, 7)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev8(&mut self) -> Iev8W<IevSpec> {
Iev8W::new(self, 8)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev9(&mut self) -> Iev9W<IevSpec> {
Iev9W::new(self, 9)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev10(&mut self) -> Iev10W<IevSpec> {
Iev10W::new(self, 10)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."]
#[inline(always)]
#[must_use]
pub fn iev11(&mut self) -> Iev11W<IevSpec> {
Iev11W::new(self, 11)
}
}
#[doc = "Interrupt event register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iev::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IevSpec;
impl crate::RegisterSpec for IevSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`iev::R`](R) reader structure"]
impl crate::Readable for IevSpec {}
#[doc = "`write(|w| ..)` method takes [`iev::W`](W) writer structure"]
impl crate::Writable for IevSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IEV to value 0"]
impl crate::Resettable for IevSpec {
const RESET_VALUE: u32 = 0;
}

205
rust-embedded/lpc111x-pac/src/gpio0/is.rs Normal file
View file

@ -0,0 +1,205 @@
#[doc = "Register `IS` reader"]
pub type R = crate::R<IsSpec>;
#[doc = "Register `IS` writer"]
pub type W = crate::W<IsSpec>;
#[doc = "Field `ISENSE0` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense0R = crate::BitReader;
#[doc = "Field `ISENSE0` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense0W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE1` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense1R = crate::BitReader;
#[doc = "Field `ISENSE1` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense1W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE2` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense2R = crate::BitReader;
#[doc = "Field `ISENSE2` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense2W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE3` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense3R = crate::BitReader;
#[doc = "Field `ISENSE3` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense3W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE4` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense4R = crate::BitReader;
#[doc = "Field `ISENSE4` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense4W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE5` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense5R = crate::BitReader;
#[doc = "Field `ISENSE5` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense5W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE6` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense6R = crate::BitReader;
#[doc = "Field `ISENSE6` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense6W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE7` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense7R = crate::BitReader;
#[doc = "Field `ISENSE7` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense7W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE8` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense8R = crate::BitReader;
#[doc = "Field `ISENSE8` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense8W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE9` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense9R = crate::BitReader;
#[doc = "Field `ISENSE9` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense9W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE10` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense10R = crate::BitReader;
#[doc = "Field `ISENSE10` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense10W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `ISENSE11` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense11R = crate::BitReader;
#[doc = "Field `ISENSE11` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
pub type Isense11W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 0 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense0(&self) -> Isense0R {
Isense0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense1(&self) -> Isense1R {
Isense1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense2(&self) -> Isense2R {
Isense2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense3(&self) -> Isense3R {
Isense3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense4(&self) -> Isense4R {
Isense4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense5(&self) -> Isense5R {
Isense5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense6(&self) -> Isense6R {
Isense6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense7(&self) -> Isense7R {
Isense7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense8(&self) -> Isense8R {
Isense8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense9(&self) -> Isense9R {
Isense9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense10(&self) -> Isense10R {
Isense10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
pub fn isense11(&self) -> Isense11R {
Isense11R::new(((self.bits >> 11) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense0(&mut self) -> Isense0W<IsSpec> {
Isense0W::new(self, 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense1(&mut self) -> Isense1W<IsSpec> {
Isense1W::new(self, 1)
}
#[doc = "Bit 2 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense2(&mut self) -> Isense2W<IsSpec> {
Isense2W::new(self, 2)
}
#[doc = "Bit 3 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense3(&mut self) -> Isense3W<IsSpec> {
Isense3W::new(self, 3)
}
#[doc = "Bit 4 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense4(&mut self) -> Isense4W<IsSpec> {
Isense4W::new(self, 4)
}
#[doc = "Bit 5 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense5(&mut self) -> Isense5W<IsSpec> {
Isense5W::new(self, 5)
}
#[doc = "Bit 6 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense6(&mut self) -> Isense6W<IsSpec> {
Isense6W::new(self, 6)
}
#[doc = "Bit 7 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense7(&mut self) -> Isense7W<IsSpec> {
Isense7W::new(self, 7)
}
#[doc = "Bit 8 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense8(&mut self) -> Isense8W<IsSpec> {
Isense8W::new(self, 8)
}
#[doc = "Bit 9 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense9(&mut self) -> Isense9W<IsSpec> {
Isense9W::new(self, 9)
}
#[doc = "Bit 10 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense10(&mut self) -> Isense10W<IsSpec> {
Isense10W::new(self, 10)
}
#[doc = "Bit 11 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."]
#[inline(always)]
#[must_use]
pub fn isense11(&mut self) -> Isense11W<IsSpec> {
Isense11W::new(self, 11)
}
}
#[doc = "Interrupt sense register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`is::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`is::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IsSpec;
impl crate::RegisterSpec for IsSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`is::R`](R) reader structure"]
impl crate::Readable for IsSpec {}
#[doc = "`write(|w| ..)` method takes [`is::W`](W) writer structure"]
impl crate::Writable for IsSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets IS to value 0"]
impl crate::Resettable for IsSpec {
const RESET_VALUE: u32 = 0;
}

99
rust-embedded/lpc111x-pac/src/gpio0/mis.rs Normal file
View file

@ -0,0 +1,99 @@
#[doc = "Register `MIS` reader"]
pub type R = crate::R<MisSpec>;
#[doc = "Field `MASK0` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask0R = crate::BitReader;
#[doc = "Field `MASK1` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask1R = crate::BitReader;
#[doc = "Field `MASK2` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask2R = crate::BitReader;
#[doc = "Field `MASK3` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask3R = crate::BitReader;
#[doc = "Field `MASK4` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask4R = crate::BitReader;
#[doc = "Field `MASK5` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask5R = crate::BitReader;
#[doc = "Field `MASK6` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask6R = crate::BitReader;
#[doc = "Field `MASK7` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask7R = crate::BitReader;
#[doc = "Field `MASK8` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask8R = crate::BitReader;
#[doc = "Field `MASK9` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask9R = crate::BitReader;
#[doc = "Field `MASK10` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask10R = crate::BitReader;
#[doc = "Field `MASK11` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
pub type Mask11R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask0(&self) -> Mask0R {
Mask0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask1(&self) -> Mask1R {
Mask1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask2(&self) -> Mask2R {
Mask2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask3(&self) -> Mask3R {
Mask3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask4(&self) -> Mask4R {
Mask4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask5(&self) -> Mask5R {
Mask5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask6(&self) -> Mask6R {
Mask6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask7(&self) -> Mask7R {
Mask7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask8(&self) -> Mask8R {
Mask8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask9(&self) -> Mask9R {
Mask9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask10(&self) -> Mask10R {
Mask10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."]
#[inline(always)]
pub fn mask11(&self) -> Mask11R {
Mask11R::new(((self.bits >> 11) & 1) != 0)
}
}
#[doc = "Masked interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MisSpec;
impl crate::RegisterSpec for MisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate::Readable for MisSpec {}
#[doc = "`reset()` method sets MIS to value 0"]
impl crate::Resettable for MisSpec {
const RESET_VALUE: u32 = 0;
}

99
rust-embedded/lpc111x-pac/src/gpio0/ris.rs Normal file
View file

@ -0,0 +1,99 @@
#[doc = "Register `RIS` reader"]
pub type R = crate::R<RisSpec>;
#[doc = "Field `RAWST0` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst0R = crate::BitReader;
#[doc = "Field `RAWST1` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst1R = crate::BitReader;
#[doc = "Field `RAWST2` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst2R = crate::BitReader;
#[doc = "Field `RAWST3` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst3R = crate::BitReader;
#[doc = "Field `RAWST4` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst4R = crate::BitReader;
#[doc = "Field `RAWST5` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst5R = crate::BitReader;
#[doc = "Field `RAWST6` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst6R = crate::BitReader;
#[doc = "Field `RAWST7` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst7R = crate::BitReader;
#[doc = "Field `RAWST8` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst8R = crate::BitReader;
#[doc = "Field `RAWST9` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst9R = crate::BitReader;
#[doc = "Field `RAWST10` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst10R = crate::BitReader;
#[doc = "Field `RAWST11` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
pub type Rawst11R = crate::BitReader;
impl R {
#[doc = "Bit 0 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst0(&self) -> Rawst0R {
Rawst0R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst1(&self) -> Rawst1R {
Rawst1R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst2(&self) -> Rawst2R {
Rawst2R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst3(&self) -> Rawst3R {
Rawst3R::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst4(&self) -> Rawst4R {
Rawst4R::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst5(&self) -> Rawst5R {
Rawst5R::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst6(&self) -> Rawst6R {
Rawst6R::new(((self.bits >> 6) & 1) != 0)
}
#[doc = "Bit 7 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst7(&self) -> Rawst7R {
Rawst7R::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 8 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst8(&self) -> Rawst8R {
Rawst8R::new(((self.bits >> 8) & 1) != 0)
}
#[doc = "Bit 9 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst9(&self) -> Rawst9R {
Rawst9R::new(((self.bits >> 9) & 1) != 0)
}
#[doc = "Bit 10 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst10(&self) -> Rawst10R {
Rawst10R::new(((self.bits >> 10) & 1) != 0)
}
#[doc = "Bit 11 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."]
#[inline(always)]
pub fn rawst11(&self) -> Rawst11R {
Rawst11R::new(((self.bits >> 11) & 1) != 0)
}
}
#[doc = "Raw interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RisSpec;
impl crate::RegisterSpec for RisSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate::Readable for RisSpec {}
#[doc = "`reset()` method sets RIS to value 0"]
impl crate::Resettable for RisSpec {
const RESET_VALUE: u32 = 0;
}

161
rust-embedded/lpc111x-pac/src/i2c.rs Normal file
View file

@ -0,0 +1,161 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
conset: Conset,
stat: Stat,
dat: Dat,
adr0: Adr0,
sclh: Sclh,
scll: Scll,
conclr: Conclr,
mmctrl: Mmctrl,
adr: [Adr; 3],
data_buffer: DataBuffer,
mask: [Mask; 4],
}
impl RegisterBlock {
#[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
#[inline(always)]
pub const fn conset(&self) -> &Conset {
&self.conset
}
#[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
#[inline(always)]
pub const fn stat(&self) -> &Stat {
&self.stat
}
#[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
#[inline(always)]
pub const fn dat(&self) -> &Dat {
&self.dat
}
#[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub const fn adr0(&self) -> &Adr0 {
&self.adr0
}
#[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
#[inline(always)]
pub const fn sclh(&self) -> &Sclh {
&self.sclh
}
#[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
#[inline(always)]
pub const fn scll(&self) -> &Scll {
&self.scll
}
#[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
#[inline(always)]
pub const fn conclr(&self) -> &Conclr {
&self.conclr
}
#[doc = "0x1c - Monitor mode control register."]
#[inline(always)]
pub const fn mmctrl(&self) -> &Mmctrl {
&self.mmctrl
}
#[doc = "0x20..0x2c - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub const fn adr(&self, n: usize) -> &Adr {
&self.adr[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x20..0x2c - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub fn adr_iter(&self) -> impl Iterator<Item = &Adr> {
self.adr.iter()
}
#[doc = "0x20 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub const fn adr1(&self) -> &Adr {
self.adr(0)
}
#[doc = "0x24 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub const fn adr2(&self) -> &Adr {
self.adr(1)
}
#[doc = "0x28 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub const fn adr3(&self) -> &Adr {
self.adr(2)
}
#[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
#[inline(always)]
pub const fn data_buffer(&self) -> &DataBuffer {
&self.data_buffer
}
#[doc = "0x30..0x40 - I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."]
#[inline(always)]
pub const fn mask(&self, n: usize) -> &Mask {
&self.mask[n]
}
#[doc = "Iterator for array of:"]
#[doc = "0x30..0x40 - I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."]
#[inline(always)]
pub fn mask_iter(&self) -> impl Iterator<Item = &Mask> {
self.mask.iter()
}
}
#[doc = "CONSET (rw) register accessor: I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conset`]
module"]
#[doc(alias = "CONSET")]
pub type Conset = crate::Reg<conset::ConsetSpec>;
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conset;
#[doc = "STAT (r) register accessor: I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
#[doc(alias = "STAT")]
pub type Stat = crate::Reg<stat::StatSpec>;
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub mod stat;
#[doc = "DAT (rw) register accessor: I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat`]
module"]
#[doc(alias = "DAT")]
pub type Dat = crate::Reg<dat::DatSpec>;
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub mod dat;
pub use adr as adr0;
pub use Adr as Adr0;
#[doc = "SCLH (rw) register accessor: SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sclh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sclh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sclh`]
module"]
#[doc(alias = "SCLH")]
pub type Sclh = crate::Reg<sclh::SclhSpec>;
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub mod sclh;
#[doc = "SCLL (rw) register accessor: SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scll`]
module"]
#[doc(alias = "SCLL")]
pub type Scll = crate::Reg<scll::ScllSpec>;
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub mod scll;
#[doc = "CONCLR (w) register accessor: I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conclr`]
module"]
#[doc(alias = "CONCLR")]
pub type Conclr = crate::Reg<conclr::ConclrSpec>;
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conclr;
#[doc = "MMCTRL (rw) register accessor: Monitor mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmctrl`]
module"]
#[doc(alias = "MMCTRL")]
pub type Mmctrl = crate::Reg<mmctrl::MmctrlSpec>;
#[doc = "Monitor mode control register."]
pub mod mmctrl;
#[doc = "ADR (rw) register accessor: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adr`]
module"]
#[doc(alias = "ADR")]
pub type Adr = crate::Reg<adr::AdrSpec>;
#[doc = "I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr;
#[doc = "DATA_BUFFER (r) register accessor: Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_buffer`]
module"]
#[doc(alias = "DATA_BUFFER")]
pub type DataBuffer = crate::Reg<data_buffer::DataBufferSpec>;
#[doc = "Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub mod data_buffer;
#[doc = "MASK (rw) register accessor: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask`]
module"]
#[doc(alias = "MASK")]
pub type Mask = crate::Reg<mask::MaskSpec>;
#[doc = "I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."]
pub mod mask;

55
rust-embedded/lpc111x-pac/src/i2c/adr.rs Normal file
View file

@ -0,0 +1,55 @@
#[doc = "Register `ADR%s` reader"]
pub type R = crate::R<AdrSpec>;
#[doc = "Register `ADR%s` writer"]
pub type W = crate::W<AdrSpec>;
#[doc = "Field `GC` reader - General Call enable bit."]
pub type GcR = crate::BitReader;
#[doc = "Field `GC` writer - General Call enable bit."]
pub type GcW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `Address` reader - The I2C device address for slave mode."]
pub type AddressR = crate::FieldReader;
#[doc = "Field `Address` writer - The I2C device address for slave mode."]
pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bit 0 - General Call enable bit."]
#[inline(always)]
pub fn gc(&self) -> GcR {
GcR::new((self.bits & 1) != 0)
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline(always)]
pub fn address(&self) -> AddressR {
AddressR::new(((self.bits >> 1) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bit 0 - General Call enable bit."]
#[inline(always)]
#[must_use]
pub fn gc(&mut self) -> GcW<AdrSpec> {
GcW::new(self, 0)
}
#[doc = "Bits 1:7 - The I2C device address for slave mode."]
#[inline(always)]
#[must_use]
pub fn address(&mut self) -> AddressW<AdrSpec> {
AddressW::new(self, 1)
}
}
#[doc = "I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdrSpec;
impl crate::RegisterSpec for AdrSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`adr::R`](R) reader structure"]
impl crate::Readable for AdrSpec {}
#[doc = "`write(|w| ..)` method takes [`adr::W`](W) writer structure"]
impl crate::Writable for AdrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets ADR%s to value 0"]
impl crate::Resettable for AdrSpec {
const RESET_VALUE: u32 = 0;
}

51
rust-embedded/lpc111x-pac/src/i2c/conclr.rs Normal file
View file

@ -0,0 +1,51 @@
#[doc = "Register `CONCLR` writer"]
pub type W = crate::W<ConclrSpec>;
#[doc = "Field `AAC` writer - Assert acknowledge Clear bit."]
pub type AacW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SIC` writer - I2C interrupt Clear bit."]
pub type SicW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STAC` writer - START flag Clear bit."]
pub type StacW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2ENC` writer - I2C interface Disable bit."]
pub type I2encW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 2 - Assert acknowledge Clear bit."]
#[inline(always)]
#[must_use]
pub fn aac(&mut self) -> AacW<ConclrSpec> {
AacW::new(self, 2)
}
#[doc = "Bit 3 - I2C interrupt Clear bit."]
#[inline(always)]
#[must_use]
pub fn sic(&mut self) -> SicW<ConclrSpec> {
SicW::new(self, 3)
}
#[doc = "Bit 5 - START flag Clear bit."]
#[inline(always)]
#[must_use]
pub fn stac(&mut self) -> StacW<ConclrSpec> {
StacW::new(self, 5)
}
#[doc = "Bit 6 - I2C interface Disable bit."]
#[inline(always)]
#[must_use]
pub fn i2enc(&mut self) -> I2encW<ConclrSpec> {
I2encW::new(self, 6)
}
}
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ConclrSpec;
impl crate::RegisterSpec for ConclrSpec {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [`conclr::W`](W) writer structure"]
impl crate::Writable for ConclrSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONCLR to value 0"]
impl crate::Resettable for ConclrSpec {
const RESET_VALUE: u32 = 0;
}

100
rust-embedded/lpc111x-pac/src/i2c/conset.rs Normal file
View file

@ -0,0 +1,100 @@
#[doc = "Register `CONSET` reader"]
pub type R = crate::R<ConsetSpec>;
#[doc = "Register `CONSET` writer"]
pub type W = crate::W<ConsetSpec>;
#[doc = "Field `AA` reader - Assert acknowledge flag."]
pub type AaR = crate::BitReader;
#[doc = "Field `AA` writer - Assert acknowledge flag."]
pub type AaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SI` reader - I2C interrupt flag."]
pub type SiR = crate::BitReader;
#[doc = "Field `SI` writer - I2C interrupt flag."]
pub type SiW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STO` reader - STOP flag."]
pub type StoR = crate::BitReader;
#[doc = "Field `STO` writer - STOP flag."]
pub type StoW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `STA` reader - START flag."]
pub type StaR = crate::BitReader;
#[doc = "Field `STA` writer - START flag."]
pub type StaW<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `I2EN` reader - I2C interface enable."]
pub type I2enR = crate::BitReader;
#[doc = "Field `I2EN` writer - I2C interface enable."]
pub type I2enW<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
#[doc = "Bit 2 - Assert acknowledge flag."]
#[inline(always)]
pub fn aa(&self) -> AaR {
AaR::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - I2C interrupt flag."]
#[inline(always)]
pub fn si(&self) -> SiR {
SiR::new(((self.bits >> 3) & 1) != 0)
}
#[doc = "Bit 4 - STOP flag."]
#[inline(always)]
pub fn sto(&self) -> StoR {
StoR::new(((self.bits >> 4) & 1) != 0)
}
#[doc = "Bit 5 - START flag."]
#[inline(always)]
pub fn sta(&self) -> StaR {
StaR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 6 - I2C interface enable."]
#[inline(always)]
pub fn i2en(&self) -> I2enR {
I2enR::new(((self.bits >> 6) & 1) != 0)
}
}
impl W {
#[doc = "Bit 2 - Assert acknowledge flag."]
#[inline(always)]
#[must_use]
pub fn aa(&mut self) -> AaW<ConsetSpec> {
AaW::new(self, 2)
}
#[doc = "Bit 3 - I2C interrupt flag."]
#[inline(always)]
#[must_use]
pub fn si(&mut self) -> SiW<ConsetSpec> {
SiW::new(self, 3)
}
#[doc = "Bit 4 - STOP flag."]
#[inline(always)]
#[must_use]
pub fn sto(&mut self) -> StoW<ConsetSpec> {
StoW::new(self, 4)
}
#[doc = "Bit 5 - START flag."]
#[inline(always)]
#[must_use]
pub fn sta(&mut self) -> StaW<ConsetSpec> {
StaW::new(self, 5)
}
#[doc = "Bit 6 - I2C interface enable."]
#[inline(always)]
#[must_use]
pub fn i2en(&mut self) -> I2enW<ConsetSpec> {
I2enW::new(self, 6)
}
}
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ConsetSpec;
impl crate::RegisterSpec for ConsetSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`conset::R`](R) reader structure"]
impl crate::Readable for ConsetSpec {}
#[doc = "`write(|w| ..)` method takes [`conset::W`](W) writer structure"]
impl crate::Writable for ConsetSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CONSET to value 0"]
impl crate::Resettable for ConsetSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/i2c/dat.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `DAT` reader"]
pub type R = crate::R<DatSpec>;
#[doc = "Register `DAT` writer"]
pub type W = crate::W<DatSpec>;
#[doc = "Field `Data` reader - This register holds data values that have been received or are to be transmitted."]
pub type DataR = crate::FieldReader;
#[doc = "Field `Data` writer - This register holds data values that have been received or are to be transmitted."]
pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
impl R {
#[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."]
#[inline(always)]
#[must_use]
pub fn data(&mut self) -> DataW<DatSpec> {
DataW::new(self, 0)
}
}
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatSpec;
impl crate::RegisterSpec for DatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dat::R`](R) reader structure"]
impl crate::Readable for DatSpec {}
#[doc = "`write(|w| ..)` method takes [`dat::W`](W) writer structure"]
impl crate::Writable for DatSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DAT to value 0"]
impl crate::Resettable for DatSpec {
const RESET_VALUE: u32 = 0;
}

22
rust-embedded/lpc111x-pac/src/i2c/data_buffer.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `DATA_BUFFER` reader"]
pub type R = crate::R<DataBufferSpec>;
#[doc = "Field `Data` reader - This register holds contents of the 8 MSBs of the DAT shift register."]
pub type DataR = crate::FieldReader;
impl R {
#[doc = "Bits 0:7 - This register holds contents of the 8 MSBs of the DAT shift register."]
#[inline(always)]
pub fn data(&self) -> DataR {
DataR::new((self.bits & 0xff) as u8)
}
}
#[doc = "Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataBufferSpec;
impl crate::RegisterSpec for DataBufferSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`data_buffer::R`](R) reader structure"]
impl crate::Readable for DataBufferSpec {}
#[doc = "`reset()` method sets DATA_BUFFER to value 0"]
impl crate::Resettable for DataBufferSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/i2c/mask.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `MASK%s` reader"]
pub type R = crate::R<MaskSpec>;
#[doc = "Register `MASK%s` writer"]
pub type W = crate::W<MaskSpec>;
#[doc = "Field `MASK` reader - Mask bits."]
pub type MaskR = crate::FieldReader;
#[doc = "Field `MASK` writer - Mask bits."]
pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
impl R {
#[doc = "Bits 1:7 - Mask bits."]
#[inline(always)]
pub fn mask(&self) -> MaskR {
MaskR::new(((self.bits >> 1) & 0x7f) as u8)
}
}
impl W {
#[doc = "Bits 1:7 - Mask bits."]
#[inline(always)]
#[must_use]
pub fn mask(&mut self) -> MaskW<MaskSpec> {
MaskW::new(self, 1)
}
}
#[doc = "I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MaskSpec;
impl crate::RegisterSpec for MaskSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mask::R`](R) reader structure"]
impl crate::Readable for MaskSpec {}
#[doc = "`write(|w| ..)` method takes [`mask::W`](W) writer structure"]
impl crate::Writable for MaskSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MASK%s to value 0"]
impl crate::Resettable for MaskSpec {
const RESET_VALUE: u32 = 0;
}

217
rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs Normal file
View file

@ -0,0 +1,217 @@
#[doc = "Register `MMCTRL` reader"]
pub type R = crate::R<MmctrlSpec>;
#[doc = "Register `MMCTRL` writer"]
pub type W = crate::W<MmctrlSpec>;
#[doc = "Monitor mode enable.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MmEna {
#[doc = "0: Monitor mode disabled."]
MonitorModeDisable = 0,
#[doc = "1: The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
TheI2cModuleWill_ = 1,
}
impl From<MmEna> for bool {
#[inline(always)]
fn from(variant: MmEna) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MM_ENA` reader - Monitor mode enable."]
pub type MmEnaR = crate::BitReader<MmEna>;
impl MmEnaR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MmEna {
match self.bits {
false => MmEna::MonitorModeDisable,
true => MmEna::TheI2cModuleWill_,
}
}
#[doc = "Monitor mode disabled."]
#[inline(always)]
pub fn is_monitor_mode_disable(&self) -> bool {
*self == MmEna::MonitorModeDisable
}
#[doc = "The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
#[inline(always)]
pub fn is_the_i2c_module_will_(&self) -> bool {
*self == MmEna::TheI2cModuleWill_
}
}
#[doc = "Field `MM_ENA` writer - Monitor mode enable."]
pub type MmEnaW<'a, REG> = crate::BitWriter<'a, REG, MmEna>;
impl<'a, REG> MmEnaW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Monitor mode disabled."]
#[inline(always)]
pub fn monitor_mode_disable(self) -> &'a mut crate::W<REG> {
self.variant(MmEna::MonitorModeDisable)
}
#[doc = "The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."]
#[inline(always)]
pub fn the_i2c_module_will_(self) -> &'a mut crate::W<REG> {
self.variant(MmEna::TheI2cModuleWill_)
}
}
#[doc = "SCL output enable.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum EnaScl {
#[doc = "0: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
High = 0,
#[doc = "1: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
Normal = 1,
}
impl From<EnaScl> for bool {
#[inline(always)]
fn from(variant: EnaScl) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ENA_SCL` reader - SCL output enable."]
pub type EnaSclR = crate::BitReader<EnaScl>;
impl EnaSclR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> EnaScl {
match self.bits {
false => EnaScl::High,
true => EnaScl::Normal,
}
}
#[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
#[inline(always)]
pub fn is_high(&self) -> bool {
*self == EnaScl::High
}
#[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
#[inline(always)]
pub fn is_normal(&self) -> bool {
*self == EnaScl::Normal
}
}
#[doc = "Field `ENA_SCL` writer - SCL output enable."]
pub type EnaSclW<'a, REG> = crate::BitWriter<'a, REG, EnaScl>;
impl<'a, REG> EnaSclW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."]
#[inline(always)]
pub fn high(self) -> &'a mut crate::W<REG> {
self.variant(EnaScl::High)
}
#[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"]
#[inline(always)]
pub fn normal(self) -> &'a mut crate::W<REG> {
self.variant(EnaScl::Normal)
}
}
#[doc = "Select interrupt register match.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum MatchAll {
#[doc = "0: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
Match = 0,
#[doc = "1: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
Anyaddress = 1,
}
impl From<MatchAll> for bool {
#[inline(always)]
fn from(variant: MatchAll) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `MATCH_ALL` reader - Select interrupt register match."]
pub type MatchAllR = crate::BitReader<MatchAll>;
impl MatchAllR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> MatchAll {
match self.bits {
false => MatchAll::Match,
true => MatchAll::Anyaddress,
}
}
#[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
#[inline(always)]
pub fn is_match(&self) -> bool {
*self == MatchAll::Match
}
#[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
#[inline(always)]
pub fn is_anyaddress(&self) -> bool {
*self == MatchAll::Anyaddress
}
}
#[doc = "Field `MATCH_ALL` writer - Select interrupt register match."]
pub type MatchAllW<'a, REG> = crate::BitWriter<'a, REG, MatchAll>;
impl<'a, REG> MatchAllW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."]
#[inline(always)]
pub fn match_(self) -> &'a mut crate::W<REG> {
self.variant(MatchAll::Match)
}
#[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."]
#[inline(always)]
pub fn anyaddress(self) -> &'a mut crate::W<REG> {
self.variant(MatchAll::Anyaddress)
}
}
impl R {
#[doc = "Bit 0 - Monitor mode enable."]
#[inline(always)]
pub fn mm_ena(&self) -> MmEnaR {
MmEnaR::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - SCL output enable."]
#[inline(always)]
pub fn ena_scl(&self) -> EnaSclR {
EnaSclR::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Select interrupt register match."]
#[inline(always)]
pub fn match_all(&self) -> MatchAllR {
MatchAllR::new(((self.bits >> 2) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Monitor mode enable."]
#[inline(always)]
#[must_use]
pub fn mm_ena(&mut self) -> MmEnaW<MmctrlSpec> {
MmEnaW::new(self, 0)
}
#[doc = "Bit 1 - SCL output enable."]
#[inline(always)]
#[must_use]
pub fn ena_scl(&mut self) -> EnaSclW<MmctrlSpec> {
EnaSclW::new(self, 1)
}
#[doc = "Bit 2 - Select interrupt register match."]
#[inline(always)]
#[must_use]
pub fn match_all(&mut self) -> MatchAllW<MmctrlSpec> {
MatchAllW::new(self, 2)
}
}
#[doc = "Monitor mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MmctrlSpec;
impl crate::RegisterSpec for MmctrlSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mmctrl::R`](R) reader structure"]
impl crate::Readable for MmctrlSpec {}
#[doc = "`write(|w| ..)` method takes [`mmctrl::W`](W) writer structure"]
impl crate::Writable for MmctrlSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MMCTRL to value 0"]
impl crate::Resettable for MmctrlSpec {
const RESET_VALUE: u32 = 0;
}

40
rust-embedded/lpc111x-pac/src/i2c/sclh.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `SCLH` reader"]
pub type R = crate::R<SclhSpec>;
#[doc = "Register `SCLH` writer"]
pub type W = crate::W<SclhSpec>;
#[doc = "Field `SCLH` reader - Count for SCL HIGH time period selection."]
pub type SclhR = crate::FieldReader<u16>;
#[doc = "Field `SCLH` writer - Count for SCL HIGH time period selection."]
pub type SclhW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Count for SCL HIGH time period selection."]
#[inline(always)]
pub fn sclh(&self) -> SclhR {
SclhR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Count for SCL HIGH time period selection."]
#[inline(always)]
#[must_use]
pub fn sclh(&mut self) -> SclhW<SclhSpec> {
SclhW::new(self, 0)
}
}
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sclh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sclh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SclhSpec;
impl crate::RegisterSpec for SclhSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`sclh::R`](R) reader structure"]
impl crate::Readable for SclhSpec {}
#[doc = "`write(|w| ..)` method takes [`sclh::W`](W) writer structure"]
impl crate::Writable for SclhSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCLH to value 0x04"]
impl crate::Resettable for SclhSpec {
const RESET_VALUE: u32 = 0x04;
}

40
rust-embedded/lpc111x-pac/src/i2c/scll.rs Normal file
View file

@ -0,0 +1,40 @@
#[doc = "Register `SCLL` reader"]
pub type R = crate::R<ScllSpec>;
#[doc = "Register `SCLL` writer"]
pub type W = crate::W<ScllSpec>;
#[doc = "Field `SCLL` reader - Count for SCL low time period selection."]
pub type ScllR = crate::FieldReader<u16>;
#[doc = "Field `SCLL` writer - Count for SCL low time period selection."]
pub type ScllW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
impl R {
#[doc = "Bits 0:15 - Count for SCL low time period selection."]
#[inline(always)]
pub fn scll(&self) -> ScllR {
ScllR::new((self.bits & 0xffff) as u16)
}
}
impl W {
#[doc = "Bits 0:15 - Count for SCL low time period selection."]
#[inline(always)]
#[must_use]
pub fn scll(&mut self) -> ScllW<ScllSpec> {
ScllW::new(self, 0)
}
}
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scll::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ScllSpec;
impl crate::RegisterSpec for ScllSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`scll::R`](R) reader structure"]
impl crate::Readable for ScllSpec {}
#[doc = "`write(|w| ..)` method takes [`scll::W`](W) writer structure"]
impl crate::Writable for ScllSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SCLL to value 0x04"]
impl crate::Resettable for ScllSpec {
const RESET_VALUE: u32 = 0x04;
}

22
rust-embedded/lpc111x-pac/src/i2c/stat.rs Normal file
View file

@ -0,0 +1,22 @@
#[doc = "Register `STAT` reader"]
pub type R = crate::R<StatSpec>;
#[doc = "Field `Status` reader - These bits give the actual status information about the I 2C interface."]
pub type StatusR = crate::FieldReader;
impl R {
#[doc = "Bits 3:7 - These bits give the actual status information about the I 2C interface."]
#[inline(always)]
pub fn status(&self) -> StatusR {
StatusR::new(((self.bits >> 3) & 0x1f) as u8)
}
}
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatSpec;
impl crate::RegisterSpec for StatSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate::Readable for StatSpec {}
#[doc = "`reset()` method sets STAT to value 0xf8"]
impl crate::Resettable for StatSpec {
const RESET_VALUE: u32 = 0xf8;
}

643
rust-embedded/lpc111x-pac/src/iocon.rs Normal file
View file

@ -0,0 +1,643 @@
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
pio2_6: Pio2_6,
_reserved1: [u8; 0x04],
pio2_0: Pio2_0,
reset_pio0_0: ResetPio0_0,
pio0_1: Pio0_1,
pio1_8: Pio1_8,
ssel1_loc: Ssel1Loc,
pio0_2: Pio0_2,
pio2_7: Pio2_7,
pio2_8: Pio2_8,
pio2_1: Pio2_1,
pio0_3: Pio0_3,
pio0_4: Pio0_4,
pio0_5: Pio0_5,
pio1_9: Pio1_9,
pio3_4: Pio3_4,
pio2_4: Pio2_4,
pio2_5: Pio2_5,
pio3_5: Pio3_5,
pio0_6: Pio0_6,
pio0_7: Pio0_7,
pio2_9: Pio2_9,
pio2_10: Pio2_10,
pio2_2: Pio2_2,
pio0_8: Pio0_8,
pio0_9: Pio0_9,
swclk_pio0_10: SwclkPio0_10,
pio1_10: Pio1_10,
pio2_11: Pio2_11,
r_pio0_11: RPio0_11,
r_pio1_0: RPio1_0,
r_pio1_1: RPio1_1,
r_pio1_2: RPio1_2,
pio3_0: Pio3_0,
pio3_1: Pio3_1,
pio2_3: Pio2_3,
swdio_pio1_3: SwdioPio1_3,
pio1_4: Pio1_4,
pio1_11: Pio1_11,
pio3_2: Pio3_2,
pio1_5: Pio1_5,
pio1_6: Pio1_6,
pio1_7: Pio1_7,
pio3_3: Pio3_3,
sck0_loc: Sck0Loc,
dsr_loc: DsrLoc,
dcd_loc: DcdLoc,
ri_loc: RiLoc,
ct16b0_cap0_loc: Ct16b0Cap0Loc,
sck1_loc: Sck1Loc,
miso1_loc: Miso1Loc,
mosi1_loc: Mosi1Loc,
ct32b0_cap0_loc: Ct32b0Cap0Loc,
rxd_loc: RxdLoc,
}
impl RegisterBlock {
#[doc = "0x00 - I/O configuration for pin PIO2_6/ CT32B0_MAT1"]
#[inline(always)]
pub const fn pio2_6(&self) -> &Pio2_6 {
&self.pio2_6
}
#[doc = "0x08 - I/O configuration for pin PIO2_0/DTR/SSEL1"]
#[inline(always)]
pub const fn pio2_0(&self) -> &Pio2_0 {
&self.pio2_0
}
#[doc = "0x0c - I/O configuration for pin RESET/PIO0_0"]
#[inline(always)]
pub const fn reset_pio0_0(&self) -> &ResetPio0_0 {
&self.reset_pio0_0
}
#[doc = "0x10 - I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2"]
#[inline(always)]
pub const fn pio0_1(&self) -> &Pio0_1 {
&self.pio0_1
}
#[doc = "0x14 - I/O configuration for pin PIO1_8/CT16B1_CAP0"]
#[inline(always)]
pub const fn pio1_8(&self) -> &Pio1_8 {
&self.pio1_8
}
#[doc = "0x18 - SSEL1 pin location select register"]
#[inline(always)]
pub const fn ssel1_loc(&self) -> &Ssel1Loc {
&self.ssel1_loc
}
#[doc = "0x1c - I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0"]
#[inline(always)]
pub const fn pio0_2(&self) -> &Pio0_2 {
&self.pio0_2
}
#[doc = "0x20 - I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD"]
#[inline(always)]
pub const fn pio2_7(&self) -> &Pio2_7 {
&self.pio2_7
}
#[doc = "0x24 - I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD"]
#[inline(always)]
pub const fn pio2_8(&self) -> &Pio2_8 {
&self.pio2_8
}
#[doc = "0x28 - I/O configuration for pin PIO2_1/DSR/SCK1"]
#[inline(always)]
pub const fn pio2_1(&self) -> &Pio2_1 {
&self.pio2_1
}
#[doc = "0x2c - I/O configuration for pin PIO0_3"]
#[inline(always)]
pub const fn pio0_3(&self) -> &Pio0_3 {
&self.pio0_3
}
#[doc = "0x30 - I/O configuration for pin PIO0_4/SCL"]
#[inline(always)]
pub const fn pio0_4(&self) -> &Pio0_4 {
&self.pio0_4
}
#[doc = "0x34 - I/O configuration for pin PIO0_5/SDA"]
#[inline(always)]
pub const fn pio0_5(&self) -> &Pio0_5 {
&self.pio0_5
}
#[doc = "0x38 - I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1"]
#[inline(always)]
pub const fn pio1_9(&self) -> &Pio1_9 {
&self.pio1_9
}
#[doc = "0x3c - I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD"]
#[inline(always)]
pub const fn pio3_4(&self) -> &Pio3_4 {
&self.pio3_4
}
#[doc = "0x40 - I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1"]
#[inline(always)]
pub const fn pio2_4(&self) -> &Pio2_4 {
&self.pio2_4
}
#[doc = "0x44 - I/O configuration for pin PIO2_5/ CT32B0_MAT0"]
#[inline(always)]
pub const fn pio2_5(&self) -> &Pio2_5 {
&self.pio2_5
}
#[doc = "0x48 - I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD"]
#[inline(always)]
pub const fn pio3_5(&self) -> &Pio3_5 {
&self.pio3_5
}
#[doc = "0x4c - I/O configuration for pin PIO0_6/SCK0"]
#[inline(always)]
pub const fn pio0_6(&self) -> &Pio0_6 {
&self.pio0_6
}
#[doc = "0x50 - I/O configuration for pin PIO0_7/CTS"]
#[inline(always)]
pub const fn pio0_7(&self) -> &Pio0_7 {
&self.pio0_7
}
#[doc = "0x54 - I/O configuration for pin PIO2_9/ CT32B0_CAP0"]
#[inline(always)]
pub const fn pio2_9(&self) -> &Pio2_9 {
&self.pio2_9
}
#[doc = "0x58 - I/O configuration for pin PIO2_10"]
#[inline(always)]
pub const fn pio2_10(&self) -> &Pio2_10 {
&self.pio2_10
}
#[doc = "0x5c - I/O configuration for pin PIO2_2/DCD/MISO1"]
#[inline(always)]
pub const fn pio2_2(&self) -> &Pio2_2 {
&self.pio2_2
}
#[doc = "0x60 - I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0"]
#[inline(always)]
pub const fn pio0_8(&self) -> &Pio0_8 {
&self.pio0_8
}
#[doc = "0x64 - I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1"]
#[inline(always)]
pub const fn pio0_9(&self) -> &Pio0_9 {
&self.pio0_9
}
#[doc = "0x68 - I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2"]
#[inline(always)]
pub const fn swclk_pio0_10(&self) -> &SwclkPio0_10 {
&self.swclk_pio0_10
}
#[doc = "0x6c - I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1"]
#[inline(always)]
pub const fn pio1_10(&self) -> &Pio1_10 {
&self.pio1_10
}
#[doc = "0x70 - I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1"]
#[inline(always)]
pub const fn pio2_11(&self) -> &Pio2_11 {
&self.pio2_11
}
#[doc = "0x74 - I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3"]
#[inline(always)]
pub const fn r_pio0_11(&self) -> &RPio0_11 {
&self.r_pio0_11
}
#[doc = "0x78 - I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0"]
#[inline(always)]
pub const fn r_pio1_0(&self) -> &RPio1_0 {
&self.r_pio1_0
}
#[doc = "0x7c - I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0"]
#[inline(always)]
pub const fn r_pio1_1(&self) -> &RPio1_1 {
&self.r_pio1_1
}
#[doc = "0x80 - I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1"]
#[inline(always)]
pub const fn r_pio1_2(&self) -> &RPio1_2 {
&self.r_pio1_2
}
#[doc = "0x84 - I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD"]
#[inline(always)]
pub const fn pio3_0(&self) -> &Pio3_0 {
&self.pio3_0
}
#[doc = "0x88 - I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD"]
#[inline(always)]
pub const fn pio3_1(&self) -> &Pio3_1 {
&self.pio3_1
}
#[doc = "0x8c - I/O configuration for pin PIO2_3/RI/MOSI1"]
#[inline(always)]
pub const fn pio2_3(&self) -> &Pio2_3 {
&self.pio2_3
}
#[doc = "0x90 - I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2"]
#[inline(always)]
pub const fn swdio_pio1_3(&self) -> &SwdioPio1_3 {
&self.swdio_pio1_3
}
#[doc = "0x94 - I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3"]
#[inline(always)]
pub const fn pio1_4(&self) -> &Pio1_4 {
&self.pio1_4
}
#[doc = "0x98 - I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1"]
#[inline(always)]
pub const fn pio1_11(&self) -> &Pio1_11 {
&self.pio1_11
}
#[doc = "0x9c - I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1"]
#[inline(always)]
pub const fn pio3_2(&self) -> &Pio3_2 {
&self.pio3_2
}
#[doc = "0xa0 - I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0"]
#[inline(always)]
pub const fn pio1_5(&self) -> &Pio1_5 {
&self.pio1_5
}
#[doc = "0xa4 - I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0"]
#[inline(always)]
pub const fn pio1_6(&self) -> &Pio1_6 {
&self.pio1_6
}
#[doc = "0xa8 - I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1"]
#[inline(always)]
pub const fn pio1_7(&self) -> &Pio1_7 {
&self.pio1_7
}
#[doc = "0xac - I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0"]
#[inline(always)]
pub const fn pio3_3(&self) -> &Pio3_3 {
&self.pio3_3
}
#[doc = "0xb0 - SCK0 pin location select register"]
#[inline(always)]
pub const fn sck0_loc(&self) -> &Sck0Loc {
&self.sck0_loc
}
#[doc = "0xb4 - DSR pin location select register"]
#[inline(always)]
pub const fn dsr_loc(&self) -> &DsrLoc {
&self.dsr_loc
}
#[doc = "0xb8 - DCD pin location select register"]
#[inline(always)]
pub const fn dcd_loc(&self) -> &DcdLoc {
&self.dcd_loc
}
#[doc = "0xbc - RI pin location select register"]
#[inline(always)]
pub const fn ri_loc(&self) -> &RiLoc {
&self.ri_loc
}
#[doc = "0xc0 - CT16B0_CAP0 pin location select register"]
#[inline(always)]
pub const fn ct16b0_cap0_loc(&self) -> &Ct16b0Cap0Loc {
&self.ct16b0_cap0_loc
}
#[doc = "0xc4 - SCK1 pin location select register"]
#[inline(always)]
pub const fn sck1_loc(&self) -> &Sck1Loc {
&self.sck1_loc
}
#[doc = "0xc8 - MISO1 pin location select register"]
#[inline(always)]
pub const fn miso1_loc(&self) -> &Miso1Loc {
&self.miso1_loc
}
#[doc = "0xcc - MOSI1 pin location select register"]
#[inline(always)]
pub const fn mosi1_loc(&self) -> &Mosi1Loc {
&self.mosi1_loc
}
#[doc = "0xd0 - CT32B0_CAP0 pin location select register"]
#[inline(always)]
pub const fn ct32b0_cap0_loc(&self) -> &Ct32b0Cap0Loc {
&self.ct32b0_cap0_loc
}
#[doc = "0xd4 - RXD pin location select register"]
#[inline(always)]
pub const fn rxd_loc(&self) -> &RxdLoc {
&self.rxd_loc
}
}
#[doc = "PIO2_6 (rw) register accessor: I/O configuration for pin PIO2_6/ CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_6`]
module"]
#[doc(alias = "PIO2_6")]
pub type Pio2_6 = crate::Reg<pio2_6::Pio2_6Spec>;
#[doc = "I/O configuration for pin PIO2_6/ CT32B0_MAT1"]
pub mod pio2_6;
#[doc = "PIO2_0 (rw) register accessor: I/O configuration for pin PIO2_0/DTR/SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_0`]
module"]
#[doc(alias = "PIO2_0")]
pub type Pio2_0 = crate::Reg<pio2_0::Pio2_0Spec>;
#[doc = "I/O configuration for pin PIO2_0/DTR/SSEL1"]
pub mod pio2_0;
#[doc = "RESET_PIO0_0 (rw) register accessor: I/O configuration for pin RESET/PIO0_0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_pio0_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_pio0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_pio0_0`]
module"]
#[doc(alias = "RESET_PIO0_0")]
pub type ResetPio0_0 = crate::Reg<reset_pio0_0::ResetPio0_0Spec>;
#[doc = "I/O configuration for pin RESET/PIO0_0"]
pub mod reset_pio0_0;
#[doc = "PIO0_1 (rw) register accessor: I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_1`]
module"]
#[doc(alias = "PIO0_1")]
pub type Pio0_1 = crate::Reg<pio0_1::Pio0_1Spec>;
#[doc = "I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2"]
pub mod pio0_1;
#[doc = "PIO1_8 (rw) register accessor: I/O configuration for pin PIO1_8/CT16B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_8`]
module"]
#[doc(alias = "PIO1_8")]
pub type Pio1_8 = crate::Reg<pio1_8::Pio1_8Spec>;
#[doc = "I/O configuration for pin PIO1_8/CT16B1_CAP0"]
pub mod pio1_8;
#[doc = "PIO0_2 (rw) register accessor: I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_2`]
module"]
#[doc(alias = "PIO0_2")]
pub type Pio0_2 = crate::Reg<pio0_2::Pio0_2Spec>;
#[doc = "I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0"]
pub mod pio0_2;
#[doc = "PIO2_7 (rw) register accessor: I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_7`]
module"]
#[doc(alias = "PIO2_7")]
pub type Pio2_7 = crate::Reg<pio2_7::Pio2_7Spec>;
#[doc = "I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD"]
pub mod pio2_7;
#[doc = "PIO2_8 (rw) register accessor: I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_8`]
module"]
#[doc(alias = "PIO2_8")]
pub type Pio2_8 = crate::Reg<pio2_8::Pio2_8Spec>;
#[doc = "I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD"]
pub mod pio2_8;
#[doc = "PIO2_1 (rw) register accessor: I/O configuration for pin PIO2_1/DSR/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_1`]
module"]
#[doc(alias = "PIO2_1")]
pub type Pio2_1 = crate::Reg<pio2_1::Pio2_1Spec>;
#[doc = "I/O configuration for pin PIO2_1/DSR/SCK1"]
pub mod pio2_1;
#[doc = "PIO0_3 (rw) register accessor: I/O configuration for pin PIO0_3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_3`]
module"]
#[doc(alias = "PIO0_3")]
pub type Pio0_3 = crate::Reg<pio0_3::Pio0_3Spec>;
#[doc = "I/O configuration for pin PIO0_3"]
pub mod pio0_3;
#[doc = "PIO0_4 (rw) register accessor: I/O configuration for pin PIO0_4/SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_4`]
module"]
#[doc(alias = "PIO0_4")]
pub type Pio0_4 = crate::Reg<pio0_4::Pio0_4Spec>;
#[doc = "I/O configuration for pin PIO0_4/SCL"]
pub mod pio0_4;
#[doc = "PIO0_5 (rw) register accessor: I/O configuration for pin PIO0_5/SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_5`]
module"]
#[doc(alias = "PIO0_5")]
pub type Pio0_5 = crate::Reg<pio0_5::Pio0_5Spec>;
#[doc = "I/O configuration for pin PIO0_5/SDA"]
pub mod pio0_5;
#[doc = "PIO1_9 (rw) register accessor: I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_9`]
module"]
#[doc(alias = "PIO1_9")]
pub type Pio1_9 = crate::Reg<pio1_9::Pio1_9Spec>;
#[doc = "I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1"]
pub mod pio1_9;
#[doc = "PIO3_4 (rw) register accessor: I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_4`]
module"]
#[doc(alias = "PIO3_4")]
pub type Pio3_4 = crate::Reg<pio3_4::Pio3_4Spec>;
#[doc = "I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD"]
pub mod pio3_4;
#[doc = "PIO2_4 (rw) register accessor: I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_4`]
module"]
#[doc(alias = "PIO2_4")]
pub type Pio2_4 = crate::Reg<pio2_4::Pio2_4Spec>;
#[doc = "I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1"]
pub mod pio2_4;
#[doc = "PIO2_5 (rw) register accessor: I/O configuration for pin PIO2_5/ CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_5`]
module"]
#[doc(alias = "PIO2_5")]
pub type Pio2_5 = crate::Reg<pio2_5::Pio2_5Spec>;
#[doc = "I/O configuration for pin PIO2_5/ CT32B0_MAT0"]
pub mod pio2_5;
#[doc = "PIO3_5 (rw) register accessor: I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_5`]
module"]
#[doc(alias = "PIO3_5")]
pub type Pio3_5 = crate::Reg<pio3_5::Pio3_5Spec>;
#[doc = "I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD"]
pub mod pio3_5;
#[doc = "PIO0_6 (rw) register accessor: I/O configuration for pin PIO0_6/SCK0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_6`]
module"]
#[doc(alias = "PIO0_6")]
pub type Pio0_6 = crate::Reg<pio0_6::Pio0_6Spec>;
#[doc = "I/O configuration for pin PIO0_6/SCK0"]
pub mod pio0_6;
#[doc = "PIO0_7 (rw) register accessor: I/O configuration for pin PIO0_7/CTS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_7`]
module"]
#[doc(alias = "PIO0_7")]
pub type Pio0_7 = crate::Reg<pio0_7::Pio0_7Spec>;
#[doc = "I/O configuration for pin PIO0_7/CTS"]
pub mod pio0_7;
#[doc = "PIO2_9 (rw) register accessor: I/O configuration for pin PIO2_9/ CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_9`]
module"]
#[doc(alias = "PIO2_9")]
pub type Pio2_9 = crate::Reg<pio2_9::Pio2_9Spec>;
#[doc = "I/O configuration for pin PIO2_9/ CT32B0_CAP0"]
pub mod pio2_9;
#[doc = "PIO2_10 (rw) register accessor: I/O configuration for pin PIO2_10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_10`]
module"]
#[doc(alias = "PIO2_10")]
pub type Pio2_10 = crate::Reg<pio2_10::Pio2_10Spec>;
#[doc = "I/O configuration for pin PIO2_10"]
pub mod pio2_10;
#[doc = "PIO2_2 (rw) register accessor: I/O configuration for pin PIO2_2/DCD/MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_2`]
module"]
#[doc(alias = "PIO2_2")]
pub type Pio2_2 = crate::Reg<pio2_2::Pio2_2Spec>;
#[doc = "I/O configuration for pin PIO2_2/DCD/MISO1"]
pub mod pio2_2;
#[doc = "PIO0_8 (rw) register accessor: I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_8`]
module"]
#[doc(alias = "PIO0_8")]
pub type Pio0_8 = crate::Reg<pio0_8::Pio0_8Spec>;
#[doc = "I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0"]
pub mod pio0_8;
#[doc = "PIO0_9 (rw) register accessor: I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_9`]
module"]
#[doc(alias = "PIO0_9")]
pub type Pio0_9 = crate::Reg<pio0_9::Pio0_9Spec>;
#[doc = "I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1"]
pub mod pio0_9;
#[doc = "SWCLK_PIO0_10 (rw) register accessor: I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swclk_pio0_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk_pio0_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swclk_pio0_10`]
module"]
#[doc(alias = "SWCLK_PIO0_10")]
pub type SwclkPio0_10 = crate::Reg<swclk_pio0_10::SwclkPio0_10Spec>;
#[doc = "I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2"]
pub mod swclk_pio0_10;
#[doc = "PIO1_10 (rw) register accessor: I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_10`]
module"]
#[doc(alias = "PIO1_10")]
pub type Pio1_10 = crate::Reg<pio1_10::Pio1_10Spec>;
#[doc = "I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1"]
pub mod pio1_10;
#[doc = "PIO2_11 (rw) register accessor: I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_11`]
module"]
#[doc(alias = "PIO2_11")]
pub type Pio2_11 = crate::Reg<pio2_11::Pio2_11Spec>;
#[doc = "I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1"]
pub mod pio2_11;
#[doc = "R_PIO0_11 (rw) register accessor: I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio0_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio0_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio0_11`]
module"]
#[doc(alias = "R_PIO0_11")]
pub type RPio0_11 = crate::Reg<r_pio0_11::RPio0_11Spec>;
#[doc = "I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3"]
pub mod r_pio0_11;
#[doc = "R_PIO1_0 (rw) register accessor: I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_0`]
module"]
#[doc(alias = "R_PIO1_0")]
pub type RPio1_0 = crate::Reg<r_pio1_0::RPio1_0Spec>;
#[doc = "I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0"]
pub mod r_pio1_0;
#[doc = "R_PIO1_1 (rw) register accessor: I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_1`]
module"]
#[doc(alias = "R_PIO1_1")]
pub type RPio1_1 = crate::Reg<r_pio1_1::RPio1_1Spec>;
#[doc = "I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0"]
pub mod r_pio1_1;
#[doc = "R_PIO1_2 (rw) register accessor: I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_2`]
module"]
#[doc(alias = "R_PIO1_2")]
pub type RPio1_2 = crate::Reg<r_pio1_2::RPio1_2Spec>;
#[doc = "I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1"]
pub mod r_pio1_2;
#[doc = "PIO3_0 (rw) register accessor: I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_0`]
module"]
#[doc(alias = "PIO3_0")]
pub type Pio3_0 = crate::Reg<pio3_0::Pio3_0Spec>;
#[doc = "I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD"]
pub mod pio3_0;
#[doc = "PIO3_1 (rw) register accessor: I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_1`]
module"]
#[doc(alias = "PIO3_1")]
pub type Pio3_1 = crate::Reg<pio3_1::Pio3_1Spec>;
#[doc = "I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD"]
pub mod pio3_1;
#[doc = "PIO2_3 (rw) register accessor: I/O configuration for pin PIO2_3/RI/MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_3`]
module"]
#[doc(alias = "PIO2_3")]
pub type Pio2_3 = crate::Reg<pio2_3::Pio2_3Spec>;
#[doc = "I/O configuration for pin PIO2_3/RI/MOSI1"]
pub mod pio2_3;
#[doc = "SWDIO_PIO1_3 (rw) register accessor: I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swdio_pio1_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swdio_pio1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdio_pio1_3`]
module"]
#[doc(alias = "SWDIO_PIO1_3")]
pub type SwdioPio1_3 = crate::Reg<swdio_pio1_3::SwdioPio1_3Spec>;
#[doc = "I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2"]
pub mod swdio_pio1_3;
#[doc = "PIO1_4 (rw) register accessor: I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_4`]
module"]
#[doc(alias = "PIO1_4")]
pub type Pio1_4 = crate::Reg<pio1_4::Pio1_4Spec>;
#[doc = "I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3"]
pub mod pio1_4;
#[doc = "PIO1_11 (rw) register accessor: I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_11`]
module"]
#[doc(alias = "PIO1_11")]
pub type Pio1_11 = crate::Reg<pio1_11::Pio1_11Spec>;
#[doc = "I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1"]
pub mod pio1_11;
#[doc = "PIO3_2 (rw) register accessor: I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_2`]
module"]
#[doc(alias = "PIO3_2")]
pub type Pio3_2 = crate::Reg<pio3_2::Pio3_2Spec>;
#[doc = "I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1"]
pub mod pio3_2;
#[doc = "PIO1_5 (rw) register accessor: I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_5`]
module"]
#[doc(alias = "PIO1_5")]
pub type Pio1_5 = crate::Reg<pio1_5::Pio1_5Spec>;
#[doc = "I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0"]
pub mod pio1_5;
#[doc = "PIO1_6 (rw) register accessor: I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_6`]
module"]
#[doc(alias = "PIO1_6")]
pub type Pio1_6 = crate::Reg<pio1_6::Pio1_6Spec>;
#[doc = "I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0"]
pub mod pio1_6;
#[doc = "PIO1_7 (rw) register accessor: I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_7`]
module"]
#[doc(alias = "PIO1_7")]
pub type Pio1_7 = crate::Reg<pio1_7::Pio1_7Spec>;
#[doc = "I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1"]
pub mod pio1_7;
#[doc = "PIO3_3 (rw) register accessor: I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_3`]
module"]
#[doc(alias = "PIO3_3")]
pub type Pio3_3 = crate::Reg<pio3_3::Pio3_3Spec>;
#[doc = "I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0"]
pub mod pio3_3;
#[doc = "SCK0_LOC (rw) register accessor: SCK0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sck0_loc`]
module"]
#[doc(alias = "SCK0_LOC")]
pub type Sck0Loc = crate::Reg<sck0_loc::Sck0LocSpec>;
#[doc = "SCK0 pin location select register"]
pub mod sck0_loc;
#[doc = "DSR_LOC (rw) register accessor: DSR pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsr_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsr_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsr_loc`]
module"]
#[doc(alias = "DSR_LOC")]
pub type DsrLoc = crate::Reg<dsr_loc::DsrLocSpec>;
#[doc = "DSR pin location select register"]
pub mod dsr_loc;
#[doc = "DCD_LOC (rw) register accessor: DCD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcd_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcd_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcd_loc`]
module"]
#[doc(alias = "DCD_LOC")]
pub type DcdLoc = crate::Reg<dcd_loc::DcdLocSpec>;
#[doc = "DCD pin location select register"]
pub mod dcd_loc;
#[doc = "RI_LOC (rw) register accessor: RI pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ri_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ri_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ri_loc`]
module"]
#[doc(alias = "RI_LOC")]
pub type RiLoc = crate::Reg<ri_loc::RiLocSpec>;
#[doc = "RI pin location select register"]
pub mod ri_loc;
#[doc = "SSEL1_LOC (rw) register accessor: SSEL1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssel1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssel1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssel1_loc`]
module"]
#[doc(alias = "SSEL1_LOC")]
pub type Ssel1Loc = crate::Reg<ssel1_loc::Ssel1LocSpec>;
#[doc = "SSEL1 pin location select register"]
pub mod ssel1_loc;
#[doc = "CT16B0_CAP0_LOC (rw) register accessor: CT16B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct16b0_cap0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct16b0_cap0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct16b0_cap0_loc`]
module"]
#[doc(alias = "CT16B0_CAP0_LOC")]
pub type Ct16b0Cap0Loc = crate::Reg<ct16b0_cap0_loc::Ct16b0Cap0LocSpec>;
#[doc = "CT16B0_CAP0 pin location select register"]
pub mod ct16b0_cap0_loc;
#[doc = "SCK1_LOC (rw) register accessor: SCK1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sck1_loc`]
module"]
#[doc(alias = "SCK1_LOC")]
pub type Sck1Loc = crate::Reg<sck1_loc::Sck1LocSpec>;
#[doc = "SCK1 pin location select register"]
pub mod sck1_loc;
#[doc = "MISO1_LOC (rw) register accessor: MISO1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miso1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miso1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miso1_loc`]
module"]
#[doc(alias = "MISO1_LOC")]
pub type Miso1Loc = crate::Reg<miso1_loc::Miso1LocSpec>;
#[doc = "MISO1 pin location select register"]
pub mod miso1_loc;
#[doc = "MOSI1_LOC (rw) register accessor: MOSI1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mosi1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mosi1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mosi1_loc`]
module"]
#[doc(alias = "MOSI1_LOC")]
pub type Mosi1Loc = crate::Reg<mosi1_loc::Mosi1LocSpec>;
#[doc = "MOSI1 pin location select register"]
pub mod mosi1_loc;
#[doc = "CT32B0_CAP0_LOC (rw) register accessor: CT32B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct32b0_cap0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct32b0_cap0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct32b0_cap0_loc`]
module"]
#[doc(alias = "CT32B0_CAP0_LOC")]
pub type Ct32b0Cap0Loc = crate::Reg<ct32b0_cap0_loc::Ct32b0Cap0LocSpec>;
#[doc = "CT32B0_CAP0 pin location select register"]
pub mod ct32b0_cap0_loc;
#[doc = "RXD_LOC (rw) register accessor: RXD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxd_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxd_loc`]
module"]
#[doc(alias = "RXD_LOC")]
pub type RxdLoc = crate::Reg<rxd_loc::RxdLocSpec>;
#[doc = "RXD pin location select register"]
pub mod rxd_loc;

95
rust-embedded/lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `CT16B0_CAP0_LOC` reader"]
pub type R = crate::R<Ct16b0Cap0LocSpec>;
#[doc = "Register `CT16B0_CAP0_LOC` writer"]
pub type W = crate::W<Ct16b0Cap0LocSpec>;
#[doc = "Selects pin location for CT16B0_CAP0 function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ct16b0Cap0loc {
#[doc = "0: `0`"]
Pio0_2 = 0,
#[doc = "1: `1`"]
Pio3_3 = 1,
}
impl From<Ct16b0Cap0loc> for u8 {
#[inline(always)]
fn from(variant: Ct16b0Cap0loc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ct16b0Cap0loc {
type Ux = u8;
}
#[doc = "Field `CT16B0_CAP0LOC` reader - Selects pin location for CT16B0_CAP0 function."]
pub type Ct16b0Cap0locR = crate::FieldReader<Ct16b0Cap0loc>;
impl Ct16b0Cap0locR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Ct16b0Cap0loc> {
match self.bits {
0 => Some(Ct16b0Cap0loc::Pio0_2),
1 => Some(Ct16b0Cap0loc::Pio3_3),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio0_2(&self) -> bool {
*self == Ct16b0Cap0loc::Pio0_2
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio3_3(&self) -> bool {
*self == Ct16b0Cap0loc::Pio3_3
}
}
#[doc = "Field `CT16B0_CAP0LOC` writer - Selects pin location for CT16B0_CAP0 function."]
pub type Ct16b0Cap0locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ct16b0Cap0loc>;
impl<'a, REG> Ct16b0Cap0locW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio0_2(self) -> &'a mut crate::W<REG> {
self.variant(Ct16b0Cap0loc::Pio0_2)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio3_3(self) -> &'a mut crate::W<REG> {
self.variant(Ct16b0Cap0loc::Pio3_3)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for CT16B0_CAP0 function."]
#[inline(always)]
pub fn ct16b0_cap0loc(&self) -> Ct16b0Cap0locR {
Ct16b0Cap0locR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for CT16B0_CAP0 function."]
#[inline(always)]
#[must_use]
pub fn ct16b0_cap0loc(&mut self) -> Ct16b0Cap0locW<Ct16b0Cap0LocSpec> {
Ct16b0Cap0locW::new(self, 0)
}
}
#[doc = "CT16B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct16b0_cap0_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct16b0_cap0_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ct16b0Cap0LocSpec;
impl crate::RegisterSpec for Ct16b0Cap0LocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ct16b0_cap0_loc::R`](R) reader structure"]
impl crate::Readable for Ct16b0Cap0LocSpec {}
#[doc = "`write(|w| ..)` method takes [`ct16b0_cap0_loc::W`](W) writer structure"]
impl crate::Writable for Ct16b0Cap0LocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CT16B0_CAP0_LOC to value 0"]
impl crate::Resettable for Ct16b0Cap0LocSpec {
const RESET_VALUE: u32 = 0;
}

95
rust-embedded/lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `CT32B0_CAP0_LOC` reader"]
pub type R = crate::R<Ct32b0Cap0LocSpec>;
#[doc = "Register `CT32B0_CAP0_LOC` writer"]
pub type W = crate::W<Ct32b0Cap0LocSpec>;
#[doc = "Selects pin location for the CT32B0_CAP0 function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Ct32b0Cap0loc {
#[doc = "0: `0`"]
Pio1_5 = 0,
#[doc = "1: `1`"]
Pio2_9 = 1,
}
impl From<Ct32b0Cap0loc> for u8 {
#[inline(always)]
fn from(variant: Ct32b0Cap0loc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Ct32b0Cap0loc {
type Ux = u8;
}
#[doc = "Field `CT32B0_CAP0LOC` reader - Selects pin location for the CT32B0_CAP0 function."]
pub type Ct32b0Cap0locR = crate::FieldReader<Ct32b0Cap0loc>;
impl Ct32b0Cap0locR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Ct32b0Cap0loc> {
match self.bits {
0 => Some(Ct32b0Cap0loc::Pio1_5),
1 => Some(Ct32b0Cap0loc::Pio2_9),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio1_5(&self) -> bool {
*self == Ct32b0Cap0loc::Pio1_5
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio2_9(&self) -> bool {
*self == Ct32b0Cap0loc::Pio2_9
}
}
#[doc = "Field `CT32B0_CAP0LOC` writer - Selects pin location for the CT32B0_CAP0 function."]
pub type Ct32b0Cap0locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ct32b0Cap0loc>;
impl<'a, REG> Ct32b0Cap0locW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio1_5(self) -> &'a mut crate::W<REG> {
self.variant(Ct32b0Cap0loc::Pio1_5)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio2_9(self) -> &'a mut crate::W<REG> {
self.variant(Ct32b0Cap0loc::Pio2_9)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for the CT32B0_CAP0 function."]
#[inline(always)]
pub fn ct32b0_cap0loc(&self) -> Ct32b0Cap0locR {
Ct32b0Cap0locR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for the CT32B0_CAP0 function."]
#[inline(always)]
#[must_use]
pub fn ct32b0_cap0loc(&mut self) -> Ct32b0Cap0locW<Ct32b0Cap0LocSpec> {
Ct32b0Cap0locW::new(self, 0)
}
}
#[doc = "CT32B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct32b0_cap0_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct32b0_cap0_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ct32b0Cap0LocSpec;
impl crate::RegisterSpec for Ct32b0Cap0LocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`ct32b0_cap0_loc::R`](R) reader structure"]
impl crate::Readable for Ct32b0Cap0LocSpec {}
#[doc = "`write(|w| ..)` method takes [`ct32b0_cap0_loc::W`](W) writer structure"]
impl crate::Writable for Ct32b0Cap0LocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets CT32B0_CAP0_LOC to value 0"]
impl crate::Resettable for Ct32b0Cap0LocSpec {
const RESET_VALUE: u32 = 0;
}

95
rust-embedded/lpc111x-pac/src/iocon/dcd_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `DCD_LOC` reader"]
pub type R = crate::R<DcdLocSpec>;
#[doc = "Register `DCD_LOC` writer"]
pub type W = crate::W<DcdLocSpec>;
#[doc = "Selects pin location for DCD function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dcdloc {
#[doc = "0: `0`"]
Pio2_2 = 0,
#[doc = "1: `1`"]
Pio3_2 = 1,
}
impl From<Dcdloc> for u8 {
#[inline(always)]
fn from(variant: Dcdloc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dcdloc {
type Ux = u8;
}
#[doc = "Field `DCDLOC` reader - Selects pin location for DCD function."]
pub type DcdlocR = crate::FieldReader<Dcdloc>;
impl DcdlocR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Dcdloc> {
match self.bits {
0 => Some(Dcdloc::Pio2_2),
1 => Some(Dcdloc::Pio3_2),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio2_2(&self) -> bool {
*self == Dcdloc::Pio2_2
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio3_2(&self) -> bool {
*self == Dcdloc::Pio3_2
}
}
#[doc = "Field `DCDLOC` writer - Selects pin location for DCD function."]
pub type DcdlocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dcdloc>;
impl<'a, REG> DcdlocW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio2_2(self) -> &'a mut crate::W<REG> {
self.variant(Dcdloc::Pio2_2)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio3_2(self) -> &'a mut crate::W<REG> {
self.variant(Dcdloc::Pio3_2)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for DCD function."]
#[inline(always)]
pub fn dcdloc(&self) -> DcdlocR {
DcdlocR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for DCD function."]
#[inline(always)]
#[must_use]
pub fn dcdloc(&mut self) -> DcdlocW<DcdLocSpec> {
DcdlocW::new(self, 0)
}
}
#[doc = "DCD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcd_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcd_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DcdLocSpec;
impl crate::RegisterSpec for DcdLocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dcd_loc::R`](R) reader structure"]
impl crate::Readable for DcdLocSpec {}
#[doc = "`write(|w| ..)` method takes [`dcd_loc::W`](W) writer structure"]
impl crate::Writable for DcdLocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DCD_LOC to value 0"]
impl crate::Resettable for DcdLocSpec {
const RESET_VALUE: u32 = 0;
}

95
rust-embedded/lpc111x-pac/src/iocon/dsr_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `DSR_LOC` reader"]
pub type R = crate::R<DsrLocSpec>;
#[doc = "Register `DSR_LOC` writer"]
pub type W = crate::W<DsrLocSpec>;
#[doc = "Selects pin location for DSR function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Dsrloc {
#[doc = "0: `0`"]
Pio2_1 = 0,
#[doc = "1: `1`"]
Pio3_1 = 1,
}
impl From<Dsrloc> for u8 {
#[inline(always)]
fn from(variant: Dsrloc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Dsrloc {
type Ux = u8;
}
#[doc = "Field `DSRLOC` reader - Selects pin location for DSR function."]
pub type DsrlocR = crate::FieldReader<Dsrloc>;
impl DsrlocR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Dsrloc> {
match self.bits {
0 => Some(Dsrloc::Pio2_1),
1 => Some(Dsrloc::Pio3_1),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio2_1(&self) -> bool {
*self == Dsrloc::Pio2_1
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio3_1(&self) -> bool {
*self == Dsrloc::Pio3_1
}
}
#[doc = "Field `DSRLOC` writer - Selects pin location for DSR function."]
pub type DsrlocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dsrloc>;
impl<'a, REG> DsrlocW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio2_1(self) -> &'a mut crate::W<REG> {
self.variant(Dsrloc::Pio2_1)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio3_1(self) -> &'a mut crate::W<REG> {
self.variant(Dsrloc::Pio3_1)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for DSR function."]
#[inline(always)]
pub fn dsrloc(&self) -> DsrlocR {
DsrlocR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for DSR function."]
#[inline(always)]
#[must_use]
pub fn dsrloc(&mut self) -> DsrlocW<DsrLocSpec> {
DsrlocW::new(self, 0)
}
}
#[doc = "DSR pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsr_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsr_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DsrLocSpec;
impl crate::RegisterSpec for DsrLocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`dsr_loc::R`](R) reader structure"]
impl crate::Readable for DsrLocSpec {}
#[doc = "`write(|w| ..)` method takes [`dsr_loc::W`](W) writer structure"]
impl crate::Writable for DsrLocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets DSR_LOC to value 0"]
impl crate::Resettable for DsrLocSpec {
const RESET_VALUE: u32 = 0;
}

95
rust-embedded/lpc111x-pac/src/iocon/miso1_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `MISO1_LOC` reader"]
pub type R = crate::R<Miso1LocSpec>;
#[doc = "Register `MISO1_LOC` writer"]
pub type W = crate::W<Miso1LocSpec>;
#[doc = "Selects pin location for the MISO1 function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Miso1loc {
#[doc = "0: `0`"]
Pio2_2 = 0,
#[doc = "1: `1`"]
Pio1_10 = 1,
}
impl From<Miso1loc> for u8 {
#[inline(always)]
fn from(variant: Miso1loc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Miso1loc {
type Ux = u8;
}
#[doc = "Field `MISO1LOC` reader - Selects pin location for the MISO1 function."]
pub type Miso1locR = crate::FieldReader<Miso1loc>;
impl Miso1locR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Miso1loc> {
match self.bits {
0 => Some(Miso1loc::Pio2_2),
1 => Some(Miso1loc::Pio1_10),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio2_2(&self) -> bool {
*self == Miso1loc::Pio2_2
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio1_10(&self) -> bool {
*self == Miso1loc::Pio1_10
}
}
#[doc = "Field `MISO1LOC` writer - Selects pin location for the MISO1 function."]
pub type Miso1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Miso1loc>;
impl<'a, REG> Miso1locW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio2_2(self) -> &'a mut crate::W<REG> {
self.variant(Miso1loc::Pio2_2)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio1_10(self) -> &'a mut crate::W<REG> {
self.variant(Miso1loc::Pio1_10)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for the MISO1 function."]
#[inline(always)]
pub fn miso1loc(&self) -> Miso1locR {
Miso1locR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for the MISO1 function."]
#[inline(always)]
#[must_use]
pub fn miso1loc(&mut self) -> Miso1locW<Miso1LocSpec> {
Miso1locW::new(self, 0)
}
}
#[doc = "MISO1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miso1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miso1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Miso1LocSpec;
impl crate::RegisterSpec for Miso1LocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`miso1_loc::R`](R) reader structure"]
impl crate::Readable for Miso1LocSpec {}
#[doc = "`write(|w| ..)` method takes [`miso1_loc::W`](W) writer structure"]
impl crate::Writable for Miso1LocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MISO1_LOC to value 0"]
impl crate::Resettable for Miso1LocSpec {
const RESET_VALUE: u32 = 0;
}

95
rust-embedded/lpc111x-pac/src/iocon/mosi1_loc.rs Normal file
View file

@ -0,0 +1,95 @@
#[doc = "Register `MOSI1_LOC` reader"]
pub type R = crate::R<Mosi1LocSpec>;
#[doc = "Register `MOSI1_LOC` writer"]
pub type W = crate::W<Mosi1LocSpec>;
#[doc = "Selects pin location for the MOSI1 function.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mosi1loc {
#[doc = "0: `0`"]
Pio2_3 = 0,
#[doc = "1: `1`"]
Pio1_9 = 1,
}
impl From<Mosi1loc> for u8 {
#[inline(always)]
fn from(variant: Mosi1loc) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mosi1loc {
type Ux = u8;
}
#[doc = "Field `MOSI1LOC` reader - Selects pin location for the MOSI1 function."]
pub type Mosi1locR = crate::FieldReader<Mosi1loc>;
impl Mosi1locR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Mosi1loc> {
match self.bits {
0 => Some(Mosi1loc::Pio2_3),
1 => Some(Mosi1loc::Pio1_9),
_ => None,
}
}
#[doc = "`0`"]
#[inline(always)]
pub fn is_pio2_3(&self) -> bool {
*self == Mosi1loc::Pio2_3
}
#[doc = "`1`"]
#[inline(always)]
pub fn is_pio1_9(&self) -> bool {
*self == Mosi1loc::Pio1_9
}
}
#[doc = "Field `MOSI1LOC` writer - Selects pin location for the MOSI1 function."]
pub type Mosi1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mosi1loc>;
impl<'a, REG> Mosi1locW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "`0`"]
#[inline(always)]
pub fn pio2_3(self) -> &'a mut crate::W<REG> {
self.variant(Mosi1loc::Pio2_3)
}
#[doc = "`1`"]
#[inline(always)]
pub fn pio1_9(self) -> &'a mut crate::W<REG> {
self.variant(Mosi1loc::Pio1_9)
}
}
impl R {
#[doc = "Bits 0:1 - Selects pin location for the MOSI1 function."]
#[inline(always)]
pub fn mosi1loc(&self) -> Mosi1locR {
Mosi1locR::new((self.bits & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:1 - Selects pin location for the MOSI1 function."]
#[inline(always)]
#[must_use]
pub fn mosi1loc(&mut self) -> Mosi1locW<Mosi1LocSpec> {
Mosi1locW::new(self, 0)
}
}
#[doc = "MOSI1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mosi1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mosi1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Mosi1LocSpec;
impl crate::RegisterSpec for Mosi1LocSpec {
type Ux = u32;
}
#[doc = "`read()` method returns [`mosi1_loc::R`](R) reader structure"]
impl crate::Readable for Mosi1LocSpec {}
#[doc = "`write(|w| ..)` method takes [`mosi1_loc::W`](W) writer structure"]
impl crate::Writable for Mosi1LocSpec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets MOSI1_LOC to value 0"]
impl crate::Resettable for Mosi1LocSpec {
const RESET_VALUE: u32 = 0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO0_1` reader"]
pub type R = crate::R<Pio0_1Spec>;
#[doc = "Register `PIO0_1` writer"]
pub type W = crate::W<Pio0_1Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_1."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CLKOUT."]
SelectsFunctionClk = 1,
#[doc = "2: Selects function CT32B0_MAT2."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionClk),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO0_1."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CLKOUT."]
#[inline(always)]
pub fn is_selects_function_clk(&self) -> bool {
*self == Func::SelectsFunctionClk
}
#[doc = "Selects function CT32B0_MAT2."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_1."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CLKOUT."]
#[inline(always)]
pub fn selects_function_clk(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionClk)
}
#[doc = "Selects function CT32B0_MAT2."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_1Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_1Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_1Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_1Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_1Spec;
impl crate::RegisterSpec for Pio0_1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_1::R`](R) reader structure"]
impl crate::Readable for Pio0_1Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_1::W`](W) writer structure"]
impl crate::Writable for Pio0_1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_1 to value 0xd0"]
impl crate::Resettable for Pio0_1Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO0_2` reader"]
pub type R = crate::R<Pio0_2Spec>;
#[doc = "Register `PIO0_2` writer"]
pub type W = crate::W<Pio0_2Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_2."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function SSEL0."]
SelectsFunctionSse = 1,
#[doc = "2: Selects function CT16B0_CAP0."]
SelectsFunctionCt1 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionSse),
2 => Some(Func::SelectsFunctionCt1),
_ => None,
}
}
#[doc = "Selects function PIO0_2."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function SSEL0."]
#[inline(always)]
pub fn is_selects_function_sse(&self) -> bool {
*self == Func::SelectsFunctionSse
}
#[doc = "Selects function CT16B0_CAP0."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_2."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function SSEL0."]
#[inline(always)]
pub fn selects_function_sse(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionSse)
}
#[doc = "Selects function CT16B0_CAP0."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_2Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_2Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_2Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_2Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_2Spec;
impl crate::RegisterSpec for Pio0_2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_2::R`](R) reader structure"]
impl crate::Readable for Pio0_2Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_2::W`](W) writer structure"]
impl crate::Writable for Pio0_2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_2 to value 0xd0"]
impl crate::Resettable for Pio0_2Spec {
const RESET_VALUE: u32 = 0xd0;
}

306
rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs Normal file
View file

@ -0,0 +1,306 @@
#[doc = "Register `PIO0_3` reader"]
pub type R = crate::R<Pio0_3Spec>;
#[doc = "Register `PIO0_3` writer"]
pub type W = crate::W<Pio0_3Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_3."]
SelectsFunctionPio = 0,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
_ => None,
}
}
#[doc = "Selects function PIO0_3."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_3."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_3Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_3Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_3Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_3Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_3Spec;
impl crate::RegisterSpec for Pio0_3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_3::R`](R) reader structure"]
impl crate::Readable for Pio0_3Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_3::W`](W) writer structure"]
impl crate::Writable for Pio0_3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_3 to value 0xd0"]
impl crate::Resettable for Pio0_3Spec {
const RESET_VALUE: u32 = 0xd0;
}

178
rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs Normal file
View file

@ -0,0 +1,178 @@
#[doc = "Register `PIO0_4` reader"]
pub type R = crate::R<Pio0_4Spec>;
#[doc = "Register `PIO0_4` writer"]
pub type W = crate::W<Pio0_4Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_4 (open-drain pin)."]
SelectsFunctionPio = 0,
#[doc = "1: Selects I2C function SCL (open-drain pin)."]
SelectsI2cFunction = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsI2cFunction),
_ => None,
}
}
#[doc = "Selects function PIO0_4 (open-drain pin)."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects I2C function SCL (open-drain pin)."]
#[inline(always)]
pub fn is_selects_i2c_function(&self) -> bool {
*self == Func::SelectsI2cFunction
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_4 (open-drain pin)."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects I2C function SCL (open-drain pin)."]
#[inline(always)]
pub fn selects_i2c_function(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsI2cFunction)
}
}
#[doc = "Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum I2cmode {
#[doc = "0: Standard mode/Fast-mode I2C"]
StandardI2c = 0,
#[doc = "1: Standard I/O"]
StandardIo = 1,
#[doc = "2: Fast-mode Plus I2C"]
FastPlusI2c = 2,
}
impl From<I2cmode> for u8 {
#[inline(always)]
fn from(variant: I2cmode) -> Self {
variant as _
}
}
impl crate::FieldSpec for I2cmode {
type Ux = u8;
}
#[doc = "Field `I2CMODE` reader - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
pub type I2cmodeR = crate::FieldReader<I2cmode>;
impl I2cmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<I2cmode> {
match self.bits {
0 => Some(I2cmode::StandardI2c),
1 => Some(I2cmode::StandardIo),
2 => Some(I2cmode::FastPlusI2c),
_ => None,
}
}
#[doc = "Standard mode/Fast-mode I2C"]
#[inline(always)]
pub fn is_standard_i2c(&self) -> bool {
*self == I2cmode::StandardI2c
}
#[doc = "Standard I/O"]
#[inline(always)]
pub fn is_standard_io(&self) -> bool {
*self == I2cmode::StandardIo
}
#[doc = "Fast-mode Plus I2C"]
#[inline(always)]
pub fn is_fast_plus_i2c(&self) -> bool {
*self == I2cmode::FastPlusI2c
}
}
#[doc = "Field `I2CMODE` writer - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
pub type I2cmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, I2cmode>;
impl<'a, REG> I2cmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Standard mode/Fast-mode I2C"]
#[inline(always)]
pub fn standard_i2c(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::StandardI2c)
}
#[doc = "Standard I/O"]
#[inline(always)]
pub fn standard_io(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::StandardIo)
}
#[doc = "Fast-mode Plus I2C"]
#[inline(always)]
pub fn fast_plus_i2c(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::FastPlusI2c)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
#[inline(always)]
pub fn i2cmode(&self) -> I2cmodeR {
I2cmodeR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_4Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
#[inline(always)]
#[must_use]
pub fn i2cmode(&mut self) -> I2cmodeW<Pio0_4Spec> {
I2cmodeW::new(self, 8)
}
}
#[doc = "I/O configuration for pin PIO0_4/SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_4Spec;
impl crate::RegisterSpec for Pio0_4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_4::R`](R) reader structure"]
impl crate::Readable for Pio0_4Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_4::W`](W) writer structure"]
impl crate::Writable for Pio0_4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_4 to value 0"]
impl crate::Resettable for Pio0_4Spec {
const RESET_VALUE: u32 = 0;
}

178
rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs Normal file
View file

@ -0,0 +1,178 @@
#[doc = "Register `PIO0_5` reader"]
pub type R = crate::R<Pio0_5Spec>;
#[doc = "Register `PIO0_5` writer"]
pub type W = crate::W<Pio0_5Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_5 (open-drain pin)."]
SelectsFunctionPio = 0,
#[doc = "1: Selects I2C function SDA (open-drain pin)."]
SelectsI2cFunction = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsI2cFunction),
_ => None,
}
}
#[doc = "Selects function PIO0_5 (open-drain pin)."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects I2C function SDA (open-drain pin)."]
#[inline(always)]
pub fn is_selects_i2c_function(&self) -> bool {
*self == Func::SelectsI2cFunction
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_5 (open-drain pin)."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects I2C function SDA (open-drain pin)."]
#[inline(always)]
pub fn selects_i2c_function(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsI2cFunction)
}
}
#[doc = "Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum I2cmode {
#[doc = "0: Standard mode/Fast-mode I2C"]
StandardI2c = 0,
#[doc = "1: Standard I/O"]
StandardIo = 1,
#[doc = "2: Fast-mode Plus I2C"]
FastPlusI2c = 2,
}
impl From<I2cmode> for u8 {
#[inline(always)]
fn from(variant: I2cmode) -> Self {
variant as _
}
}
impl crate::FieldSpec for I2cmode {
type Ux = u8;
}
#[doc = "Field `I2CMODE` reader - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
pub type I2cmodeR = crate::FieldReader<I2cmode>;
impl I2cmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<I2cmode> {
match self.bits {
0 => Some(I2cmode::StandardI2c),
1 => Some(I2cmode::StandardIo),
2 => Some(I2cmode::FastPlusI2c),
_ => None,
}
}
#[doc = "Standard mode/Fast-mode I2C"]
#[inline(always)]
pub fn is_standard_i2c(&self) -> bool {
*self == I2cmode::StandardI2c
}
#[doc = "Standard I/O"]
#[inline(always)]
pub fn is_standard_io(&self) -> bool {
*self == I2cmode::StandardIo
}
#[doc = "Fast-mode Plus I2C"]
#[inline(always)]
pub fn is_fast_plus_i2c(&self) -> bool {
*self == I2cmode::FastPlusI2c
}
}
#[doc = "Field `I2CMODE` writer - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
pub type I2cmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, I2cmode>;
impl<'a, REG> I2cmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Standard mode/Fast-mode I2C"]
#[inline(always)]
pub fn standard_i2c(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::StandardI2c)
}
#[doc = "Standard I/O"]
#[inline(always)]
pub fn standard_io(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::StandardIo)
}
#[doc = "Fast-mode Plus I2C"]
#[inline(always)]
pub fn fast_plus_i2c(self) -> &'a mut crate::W<REG> {
self.variant(I2cmode::FastPlusI2c)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
#[inline(always)]
pub fn i2cmode(&self) -> I2cmodeR {
I2cmodeR::new(((self.bits >> 8) & 3) as u8)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_5Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."]
#[inline(always)]
#[must_use]
pub fn i2cmode(&mut self) -> I2cmodeW<Pio0_5Spec> {
I2cmodeW::new(self, 8)
}
}
#[doc = "I/O configuration for pin PIO0_5/SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_5Spec;
impl crate::RegisterSpec for Pio0_5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_5::R`](R) reader structure"]
impl crate::Readable for Pio0_5Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_5::W`](W) writer structure"]
impl crate::Writable for Pio0_5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_5 to value 0"]
impl crate::Resettable for Pio0_5Spec {
const RESET_VALUE: u32 = 0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO0_6` reader"]
pub type R = crate::R<Pio0_6Spec>;
#[doc = "Register `PIO0_6` writer"]
pub type W = crate::W<Pio0_6Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_6."]
SelectsFunctionPio = 0,
#[doc = "1: Reserved."]
Reserved_ = 1,
#[doc = "2: Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."]
SelectsFunctionSck = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::Reserved_),
2 => Some(Func::SelectsFunctionSck),
_ => None,
}
}
#[doc = "Selects function PIO0_6."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Reserved."]
#[inline(always)]
pub fn is_reserved_(&self) -> bool {
*self == Func::Reserved_
}
#[doc = "Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."]
#[inline(always)]
pub fn is_selects_function_sck(&self) -> bool {
*self == Func::SelectsFunctionSck
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_6."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Reserved."]
#[inline(always)]
pub fn reserved_(self) -> &'a mut crate::W<REG> {
self.variant(Func::Reserved_)
}
#[doc = "Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."]
#[inline(always)]
pub fn selects_function_sck(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionSck)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_6Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_6Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_6Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_6Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_6/SCK0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_6Spec;
impl crate::RegisterSpec for Pio0_6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_6::R`](R) reader structure"]
impl crate::Readable for Pio0_6Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_6::W`](W) writer structure"]
impl crate::Writable for Pio0_6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_6 to value 0xd0"]
impl crate::Resettable for Pio0_6Spec {
const RESET_VALUE: u32 = 0xd0;
}

319
rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs Normal file
View file

@ -0,0 +1,319 @@
#[doc = "Register `PIO0_7` reader"]
pub type R = crate::R<Pio0_7Spec>;
#[doc = "Register `PIO0_7` writer"]
pub type W = crate::W<Pio0_7Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_7."]
SelectsFunctionPio = 0,
#[doc = "1: Select function CTS."]
SelectFunctionCts_ = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectFunctionCts_),
_ => None,
}
}
#[doc = "Selects function PIO0_7."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Select function CTS."]
#[inline(always)]
pub fn is_select_function_cts_(&self) -> bool {
*self == Func::SelectFunctionCts_
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_7."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Select function CTS."]
#[inline(always)]
pub fn select_function_cts_(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionCts_)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_7Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_7Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_7Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_7Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_7/CTS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_7Spec;
impl crate::RegisterSpec for Pio0_7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_7::R`](R) reader structure"]
impl crate::Readable for Pio0_7Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_7::W`](W) writer structure"]
impl crate::Writable for Pio0_7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_7 to value 0xd0"]
impl crate::Resettable for Pio0_7Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO0_8` reader"]
pub type R = crate::R<Pio0_8Spec>;
#[doc = "Register `PIO0_8` writer"]
pub type W = crate::W<Pio0_8Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_8."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function MISO0."]
SelectsFunctionMis = 1,
#[doc = "2: Selects function CT16B0_MAT0."]
SelectsFunctionCt1 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionMis),
2 => Some(Func::SelectsFunctionCt1),
_ => None,
}
}
#[doc = "Selects function PIO0_8."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function MISO0."]
#[inline(always)]
pub fn is_selects_function_mis(&self) -> bool {
*self == Func::SelectsFunctionMis
}
#[doc = "Selects function CT16B0_MAT0."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_8."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function MISO0."]
#[inline(always)]
pub fn selects_function_mis(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionMis)
}
#[doc = "Selects function CT16B0_MAT0."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_8Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_8Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_8Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_8Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_8Spec;
impl crate::RegisterSpec for Pio0_8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_8::R`](R) reader structure"]
impl crate::Readable for Pio0_8Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_8::W`](W) writer structure"]
impl crate::Writable for Pio0_8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_8 to value 0xd0"]
impl crate::Resettable for Pio0_8Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO0_9` reader"]
pub type R = crate::R<Pio0_9Spec>;
#[doc = "Register `PIO0_9` writer"]
pub type W = crate::W<Pio0_9Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO0_9."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function MOSI0."]
SelectsFunctionMos = 1,
#[doc = "2: Selects function CT16B0_MAT1."]
SelectsFunctionCt1 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionMos),
2 => Some(Func::SelectsFunctionCt1),
_ => None,
}
}
#[doc = "Selects function PIO0_9."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function MOSI0."]
#[inline(always)]
pub fn is_selects_function_mos(&self) -> bool {
*self == Func::SelectsFunctionMos
}
#[doc = "Selects function CT16B0_MAT1."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO0_9."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function MOSI0."]
#[inline(always)]
pub fn selects_function_mos(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionMos)
}
#[doc = "Selects function CT16B0_MAT1."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio0_9Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio0_9Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio0_9Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio0_9Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio0_9Spec;
impl crate::RegisterSpec for Pio0_9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio0_9::R`](R) reader structure"]
impl crate::Readable for Pio0_9Spec {}
#[doc = "`write(|w| ..)` method takes [`pio0_9::W`](W) writer structure"]
impl crate::Writable for Pio0_9Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO0_9 to value 0xd0"]
impl crate::Resettable for Pio0_9Spec {
const RESET_VALUE: u32 = 0xd0;
}

409
rust-embedded/lpc111x-pac/src/iocon/pio1_10.rs Normal file
View file

@ -0,0 +1,409 @@
#[doc = "Register `PIO1_10` reader"]
pub type R = crate::R<Pio1_10Spec>;
#[doc = "Register `PIO1_10` writer"]
pub type W = crate::W<Pio1_10Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_10."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function AD6."]
SelectsFunctionAd6 = 1,
#[doc = "2: Selects function CT16B1_MAT1."]
SelectsFunctionCt1 = 2,
#[doc = "3: Selects function MISO1."]
SelectsFunctionMis = 3,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionAd6),
2 => Some(Func::SelectsFunctionCt1),
3 => Some(Func::SelectsFunctionMis),
_ => None,
}
}
#[doc = "Selects function PIO1_10."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function AD6."]
#[inline(always)]
pub fn is_selects_function_ad6(&self) -> bool {
*self == Func::SelectsFunctionAd6
}
#[doc = "Selects function CT16B1_MAT1."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
#[doc = "Selects function MISO1."]
#[inline(always)]
pub fn is_selects_function_mis(&self) -> bool {
*self == Func::SelectsFunctionMis
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_10."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function AD6."]
#[inline(always)]
pub fn selects_function_ad6(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionAd6)
}
#[doc = "Selects function CT16B1_MAT1."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
#[doc = "Selects function MISO1."]
#[inline(always)]
pub fn selects_function_mis(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionMis)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Admode {
#[doc = "0: Analog input mode"]
AnalogInputMode = 0,
#[doc = "1: Digital functional mode"]
DigitalFunctionalM = 1,
}
impl From<Admode> for bool {
#[inline(always)]
fn from(variant: Admode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"]
pub type AdmodeR = crate::BitReader<Admode>;
impl AdmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Admode {
match self.bits {
false => Admode::AnalogInputMode,
true => Admode::DigitalFunctionalM,
}
}
#[doc = "Analog input mode"]
#[inline(always)]
pub fn is_analog_input_mode(&self) -> bool {
*self == Admode::AnalogInputMode
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn is_digital_functional_m(&self) -> bool {
*self == Admode::DigitalFunctionalM
}
}
#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"]
pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>;
impl<'a, REG> AdmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Analog input mode"]
#[inline(always)]
pub fn analog_input_mode(self) -> &'a mut crate::W<REG> {
self.variant(Admode::AnalogInputMode)
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn digital_functional_m(self) -> &'a mut crate::W<REG> {
self.variant(Admode::DigitalFunctionalM)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_10Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_10Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_10Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Pio1_10Spec> {
AdmodeW::new(self, 7)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_10Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_10Spec;
impl crate::RegisterSpec for Pio1_10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_10::R`](R) reader structure"]
impl crate::Readable for Pio1_10Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_10::W`](W) writer structure"]
impl crate::Writable for Pio1_10Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_10 to value 0xd0"]
impl crate::Resettable for Pio1_10Spec {
const RESET_VALUE: u32 = 0xd0;
}

396
rust-embedded/lpc111x-pac/src/iocon/pio1_11.rs Normal file
View file

@ -0,0 +1,396 @@
#[doc = "Register `PIO1_11` reader"]
pub type R = crate::R<Pio1_11Spec>;
#[doc = "Register `PIO1_11` writer"]
pub type W = crate::W<Pio1_11Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_11."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function AD7."]
SelectsFunctionAd7 = 1,
#[doc = "2: Selects function CT32B1_CAP1."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionAd7),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO1_11."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function AD7."]
#[inline(always)]
pub fn is_selects_function_ad7(&self) -> bool {
*self == Func::SelectsFunctionAd7
}
#[doc = "Selects function CT32B1_CAP1."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_11."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function AD7."]
#[inline(always)]
pub fn selects_function_ad7(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionAd7)
}
#[doc = "Selects function CT32B1_CAP1."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Admode {
#[doc = "0: Analog input mode"]
AnalogInputMode = 0,
#[doc = "1: Digital functional mode"]
DigitalFunctionalM = 1,
}
impl From<Admode> for bool {
#[inline(always)]
fn from(variant: Admode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"]
pub type AdmodeR = crate::BitReader<Admode>;
impl AdmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Admode {
match self.bits {
false => Admode::AnalogInputMode,
true => Admode::DigitalFunctionalM,
}
}
#[doc = "Analog input mode"]
#[inline(always)]
pub fn is_analog_input_mode(&self) -> bool {
*self == Admode::AnalogInputMode
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn is_digital_functional_m(&self) -> bool {
*self == Admode::DigitalFunctionalM
}
}
#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"]
pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>;
impl<'a, REG> AdmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Analog input mode"]
#[inline(always)]
pub fn analog_input_mode(self) -> &'a mut crate::W<REG> {
self.variant(Admode::AnalogInputMode)
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn digital_functional_m(self) -> &'a mut crate::W<REG> {
self.variant(Admode::DigitalFunctionalM)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_11Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_11Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_11Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Pio1_11Spec> {
AdmodeW::new(self, 7)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_11Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_11Spec;
impl crate::RegisterSpec for Pio1_11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_11::R`](R) reader structure"]
impl crate::Readable for Pio1_11Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_11::W`](W) writer structure"]
impl crate::Writable for Pio1_11Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_11 to value 0xd0"]
impl crate::Resettable for Pio1_11Spec {
const RESET_VALUE: u32 = 0xd0;
}

396
rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs Normal file
View file

@ -0,0 +1,396 @@
#[doc = "Register `PIO1_4` reader"]
pub type R = crate::R<Pio1_4Spec>;
#[doc = "Register `PIO1_4` writer"]
pub type W = crate::W<Pio1_4Spec>;
#[doc = "Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_4."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function AD5."]
SelectsFunctionAd5 = 1,
#[doc = "2: Selects function CT32B1_MAT3."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionAd5),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO1_4."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function AD5."]
#[inline(always)]
pub fn is_selects_function_ad5(&self) -> bool {
*self == Func::SelectsFunctionAd5
}
#[doc = "Selects function CT32B1_MAT3."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_4."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function AD5."]
#[inline(always)]
pub fn selects_function_ad5(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionAd5)
}
#[doc = "Selects function CT32B1_MAT3."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Admode {
#[doc = "0: Analog input mode"]
AnalogInputMode = 0,
#[doc = "1: Digital functional mode"]
DigitalFunctionalM = 1,
}
impl From<Admode> for bool {
#[inline(always)]
fn from(variant: Admode) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"]
pub type AdmodeR = crate::BitReader<Admode>;
impl AdmodeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Admode {
match self.bits {
false => Admode::AnalogInputMode,
true => Admode::DigitalFunctionalM,
}
}
#[doc = "Analog input mode"]
#[inline(always)]
pub fn is_analog_input_mode(&self) -> bool {
*self == Admode::AnalogInputMode
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn is_digital_functional_m(&self) -> bool {
*self == Admode::DigitalFunctionalM
}
}
#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"]
pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>;
impl<'a, REG> AdmodeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Analog input mode"]
#[inline(always)]
pub fn analog_input_mode(self) -> &'a mut crate::W<REG> {
self.variant(Admode::AnalogInputMode)
}
#[doc = "Digital functional mode"]
#[inline(always)]
pub fn digital_functional_m(self) -> &'a mut crate::W<REG> {
self.variant(Admode::DigitalFunctionalM)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
pub fn admode(&self) -> AdmodeR {
AdmodeR::new(((self.bits >> 7) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_4Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_4Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_4Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 7 - Selects Analog/Digital mode"]
#[inline(always)]
#[must_use]
pub fn admode(&mut self) -> AdmodeW<Pio1_4Spec> {
AdmodeW::new(self, 7)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_4Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_4Spec;
impl crate::RegisterSpec for Pio1_4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_4::R`](R) reader structure"]
impl crate::Readable for Pio1_4Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_4::W`](W) writer structure"]
impl crate::Writable for Pio1_4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_4 to value 0xd0"]
impl crate::Resettable for Pio1_4Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO1_5` reader"]
pub type R = crate::R<Pio1_5Spec>;
#[doc = "Register `PIO1_5` writer"]
pub type W = crate::W<Pio1_5Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_5."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function RTS."]
SelectsFunctionRts = 1,
#[doc = "2: Selects function CT32B0_CAP0."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionRts),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO1_5."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function RTS."]
#[inline(always)]
pub fn is_selects_function_rts(&self) -> bool {
*self == Func::SelectsFunctionRts
}
#[doc = "Selects function CT32B0_CAP0."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_5."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function RTS."]
#[inline(always)]
pub fn selects_function_rts(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionRts)
}
#[doc = "Selects function CT32B0_CAP0."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_5Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_5Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_5Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_5Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_5Spec;
impl crate::RegisterSpec for Pio1_5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_5::R`](R) reader structure"]
impl crate::Readable for Pio1_5Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_5::W`](W) writer structure"]
impl crate::Writable for Pio1_5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_5 to value 0xd0"]
impl crate::Resettable for Pio1_5Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO1_6` reader"]
pub type R = crate::R<Pio1_6Spec>;
#[doc = "Register `PIO1_6` writer"]
pub type W = crate::W<Pio1_6Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_6."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function RXD."]
SelectsFunctionRxd = 1,
#[doc = "2: Selects function CT32B0_MAT0."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionRxd),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO1_6."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function RXD."]
#[inline(always)]
pub fn is_selects_function_rxd(&self) -> bool {
*self == Func::SelectsFunctionRxd
}
#[doc = "Selects function CT32B0_MAT0."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_6."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function RXD."]
#[inline(always)]
pub fn selects_function_rxd(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionRxd)
}
#[doc = "Selects function CT32B0_MAT0."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_6Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_6Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_6Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_6Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_6Spec;
impl crate::RegisterSpec for Pio1_6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_6::R`](R) reader structure"]
impl crate::Readable for Pio1_6Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_6::W`](W) writer structure"]
impl crate::Writable for Pio1_6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_6 to value 0xd0"]
impl crate::Resettable for Pio1_6Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO1_7` reader"]
pub type R = crate::R<Pio1_7Spec>;
#[doc = "Register `PIO1_7` writer"]
pub type W = crate::W<Pio1_7Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_7."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function TXD."]
SelectsFunctionTxd = 1,
#[doc = "2: Selects function CT32B0_MAT1."]
SelectsFunctionCt3 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionTxd),
2 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO1_7."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function TXD."]
#[inline(always)]
pub fn is_selects_function_txd(&self) -> bool {
*self == Func::SelectsFunctionTxd
}
#[doc = "Selects function CT32B0_MAT1."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_7."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function TXD."]
#[inline(always)]
pub fn selects_function_txd(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionTxd)
}
#[doc = "Selects function CT32B0_MAT1."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_7Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_7Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_7Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_7Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_7Spec;
impl crate::RegisterSpec for Pio1_7Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_7::R`](R) reader structure"]
impl crate::Readable for Pio1_7Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_7::W`](W) writer structure"]
impl crate::Writable for Pio1_7Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_7 to value 0xd0"]
impl crate::Resettable for Pio1_7Spec {
const RESET_VALUE: u32 = 0xd0;
}

319
rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs Normal file
View file

@ -0,0 +1,319 @@
#[doc = "Register `PIO1_8` reader"]
pub type R = crate::R<Pio1_8Spec>;
#[doc = "Register `PIO1_8` writer"]
pub type W = crate::W<Pio1_8Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_8."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CT16B1_CAP0."]
SelectsFunctionCt1 = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionCt1),
_ => None,
}
}
#[doc = "Selects function PIO1_8."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CT16B1_CAP0."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_8."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CT16B1_CAP0."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_8Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_8Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_8Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_8Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_8/CT16B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_8Spec;
impl crate::RegisterSpec for Pio1_8Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_8::R`](R) reader structure"]
impl crate::Readable for Pio1_8Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_8::W`](W) writer structure"]
impl crate::Writable for Pio1_8Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_8 to value 0xd0"]
impl crate::Resettable for Pio1_8Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO1_9` reader"]
pub type R = crate::R<Pio1_9Spec>;
#[doc = "Register `PIO1_9` writer"]
pub type W = crate::W<Pio1_9Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO1_9."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CT16B1_MAT0."]
SelectsFunctionCt1 = 1,
#[doc = "2: Selects function MOSI1."]
SelectsFunctionMos = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionCt1),
2 => Some(Func::SelectsFunctionMos),
_ => None,
}
}
#[doc = "Selects function PIO1_9."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CT16B1_MAT0."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
#[doc = "Selects function MOSI1."]
#[inline(always)]
pub fn is_selects_function_mos(&self) -> bool {
*self == Func::SelectsFunctionMos
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO1_9."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CT16B1_MAT0."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
#[doc = "Selects function MOSI1."]
#[inline(always)]
pub fn selects_function_mos(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionMos)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio1_9Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio1_9Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio1_9Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio1_9Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio1_9Spec;
impl crate::RegisterSpec for Pio1_9Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio1_9::R`](R) reader structure"]
impl crate::Readable for Pio1_9Spec {}
#[doc = "`write(|w| ..)` method takes [`pio1_9::W`](W) writer structure"]
impl crate::Writable for Pio1_9Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO1_9 to value 0xd0"]
impl crate::Resettable for Pio1_9Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_0` reader"]
pub type R = crate::R<Pio2_0Spec>;
#[doc = "Register `PIO2_0` writer"]
pub type W = crate::W<Pio2_0Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_0."]
SelectsFunctionPio = 0,
#[doc = "1: Select function DTR."]
SelectFunctionDtr_ = 1,
#[doc = "2: Select function SSEL1."]
SelectFunctionSsel = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectFunctionDtr_),
2 => Some(Func::SelectFunctionSsel),
_ => None,
}
}
#[doc = "Selects function PIO2_0."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Select function DTR."]
#[inline(always)]
pub fn is_select_function_dtr_(&self) -> bool {
*self == Func::SelectFunctionDtr_
}
#[doc = "Select function SSEL1."]
#[inline(always)]
pub fn is_select_function_ssel(&self) -> bool {
*self == Func::SelectFunctionSsel
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_0."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Select function DTR."]
#[inline(always)]
pub fn select_function_dtr_(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionDtr_)
}
#[doc = "Select function SSEL1."]
#[inline(always)]
pub fn select_function_ssel(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionSsel)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_0Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_0Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_0Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_0Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_0/DTR/SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_0Spec;
impl crate::RegisterSpec for Pio2_0Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_0::R`](R) reader structure"]
impl crate::Readable for Pio2_0Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_0::W`](W) writer structure"]
impl crate::Writable for Pio2_0Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_0 to value 0xd0"]
impl crate::Resettable for Pio2_0Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_1` reader"]
pub type R = crate::R<Pio2_1Spec>;
#[doc = "Register `PIO2_1` writer"]
pub type W = crate::W<Pio2_1Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_1."]
SelectsFunctionPio = 0,
#[doc = "1: Select function DSR."]
SelectFunctionDsr_ = 1,
#[doc = "2: Select function SCK1."]
SelectFunctionSck1 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectFunctionDsr_),
2 => Some(Func::SelectFunctionSck1),
_ => None,
}
}
#[doc = "Selects function PIO2_1."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Select function DSR."]
#[inline(always)]
pub fn is_select_function_dsr_(&self) -> bool {
*self == Func::SelectFunctionDsr_
}
#[doc = "Select function SCK1."]
#[inline(always)]
pub fn is_select_function_sck1(&self) -> bool {
*self == Func::SelectFunctionSck1
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_1."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Select function DSR."]
#[inline(always)]
pub fn select_function_dsr_(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionDsr_)
}
#[doc = "Select function SCK1."]
#[inline(always)]
pub fn select_function_sck1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionSck1)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_1Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_1Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_1Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_1Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_1/DSR/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_1Spec;
impl crate::RegisterSpec for Pio2_1Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_1::R`](R) reader structure"]
impl crate::Readable for Pio2_1Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_1::W`](W) writer structure"]
impl crate::Writable for Pio2_1Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_1 to value 0xd0"]
impl crate::Resettable for Pio2_1Spec {
const RESET_VALUE: u32 = 0xd0;
}

306
rust-embedded/lpc111x-pac/src/iocon/pio2_10.rs Normal file
View file

@ -0,0 +1,306 @@
#[doc = "Register `PIO2_10` reader"]
pub type R = crate::R<Pio2_10Spec>;
#[doc = "Register `PIO2_10` writer"]
pub type W = crate::W<Pio2_10Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_10."]
SelectsFunctionPio = 0,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
_ => None,
}
}
#[doc = "Selects function PIO2_10."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_10."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_10Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_10Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_10Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_10Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_10Spec;
impl crate::RegisterSpec for Pio2_10Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_10::R`](R) reader structure"]
impl crate::Readable for Pio2_10Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_10::W`](W) writer structure"]
impl crate::Writable for Pio2_10Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_10 to value 0xd0"]
impl crate::Resettable for Pio2_10Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_11.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_11` reader"]
pub type R = crate::R<Pio2_11Spec>;
#[doc = "Register `PIO2_11` writer"]
pub type W = crate::W<Pio2_11Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_11."]
SelectsFunctionPio = 0,
#[doc = "1: Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."]
SelectFunctionSck0 = 1,
#[doc = "2: Select function CT32B0_CAP1."]
SelectFunctionCt32 = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectFunctionSck0),
2 => Some(Func::SelectFunctionCt32),
_ => None,
}
}
#[doc = "Selects function PIO2_11."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."]
#[inline(always)]
pub fn is_select_function_sck0(&self) -> bool {
*self == Func::SelectFunctionSck0
}
#[doc = "Select function CT32B0_CAP1."]
#[inline(always)]
pub fn is_select_function_ct32(&self) -> bool {
*self == Func::SelectFunctionCt32
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_11."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."]
#[inline(always)]
pub fn select_function_sck0(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionSck0)
}
#[doc = "Select function CT32B0_CAP1."]
#[inline(always)]
pub fn select_function_ct32(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionCt32)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_11Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_11Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_11Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_11Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_11Spec;
impl crate::RegisterSpec for Pio2_11Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_11::R`](R) reader structure"]
impl crate::Readable for Pio2_11Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_11::W`](W) writer structure"]
impl crate::Writable for Pio2_11Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_11 to value 0xd0"]
impl crate::Resettable for Pio2_11Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_2` reader"]
pub type R = crate::R<Pio2_2Spec>;
#[doc = "Register `PIO2_2` writer"]
pub type W = crate::W<Pio2_2Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_2."]
SelectsFunctionPio = 0,
#[doc = "1: Select function DCD."]
SelectFunctionDcd_ = 1,
#[doc = "2: Select function MISO1."]
SelectFunctionMiso = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectFunctionDcd_),
2 => Some(Func::SelectFunctionMiso),
_ => None,
}
}
#[doc = "Selects function PIO2_2."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Select function DCD."]
#[inline(always)]
pub fn is_select_function_dcd_(&self) -> bool {
*self == Func::SelectFunctionDcd_
}
#[doc = "Select function MISO1."]
#[inline(always)]
pub fn is_select_function_miso(&self) -> bool {
*self == Func::SelectFunctionMiso
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_2."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Select function DCD."]
#[inline(always)]
pub fn select_function_dcd_(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionDcd_)
}
#[doc = "Select function MISO1."]
#[inline(always)]
pub fn select_function_miso(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectFunctionMiso)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_2Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_2Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_2Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_2Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_2/DCD/MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_2Spec;
impl crate::RegisterSpec for Pio2_2Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_2::R`](R) reader structure"]
impl crate::Readable for Pio2_2Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_2::W`](W) writer structure"]
impl crate::Writable for Pio2_2Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_2 to value 0xd0"]
impl crate::Resettable for Pio2_2Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_3` reader"]
pub type R = crate::R<Pio2_3Spec>;
#[doc = "Register `PIO2_3` writer"]
pub type W = crate::W<Pio2_3Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_3."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function RI."]
SelectsFunctionRi_ = 1,
#[doc = "2: Selects function MOSI1."]
SelectsFunctionMos = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionRi_),
2 => Some(Func::SelectsFunctionMos),
_ => None,
}
}
#[doc = "Selects function PIO2_3."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function RI."]
#[inline(always)]
pub fn is_selects_function_ri_(&self) -> bool {
*self == Func::SelectsFunctionRi_
}
#[doc = "Selects function MOSI1."]
#[inline(always)]
pub fn is_selects_function_mos(&self) -> bool {
*self == Func::SelectsFunctionMos
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_3."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function RI."]
#[inline(always)]
pub fn selects_function_ri_(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionRi_)
}
#[doc = "Selects function MOSI1."]
#[inline(always)]
pub fn selects_function_mos(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionMos)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_3Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_3Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_3Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_3Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_3/RI/MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_3Spec;
impl crate::RegisterSpec for Pio2_3Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_3::R`](R) reader structure"]
impl crate::Readable for Pio2_3Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_3::W`](W) writer structure"]
impl crate::Writable for Pio2_3Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_3 to value 0xd0"]
impl crate::Resettable for Pio2_3Spec {
const RESET_VALUE: u32 = 0xd0;
}

332
rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs Normal file
View file

@ -0,0 +1,332 @@
#[doc = "Register `PIO2_4` reader"]
pub type R = crate::R<Pio2_4Spec>;
#[doc = "Register `PIO2_4` writer"]
pub type W = crate::W<Pio2_4Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_4."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CT16B1_MAT1."]
SelectsFunctionCt1 = 1,
#[doc = "2: Selects function SSEL1."]
SelectsFunctionSse = 2,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionCt1),
2 => Some(Func::SelectsFunctionSse),
_ => None,
}
}
#[doc = "Selects function PIO2_4."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CT16B1_MAT1."]
#[inline(always)]
pub fn is_selects_function_ct1(&self) -> bool {
*self == Func::SelectsFunctionCt1
}
#[doc = "Selects function SSEL1."]
#[inline(always)]
pub fn is_selects_function_sse(&self) -> bool {
*self == Func::SelectsFunctionSse
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_4."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CT16B1_MAT1."]
#[inline(always)]
pub fn selects_function_ct1(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt1)
}
#[doc = "Selects function SSEL1."]
#[inline(always)]
pub fn selects_function_sse(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionSse)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_4Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_4Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_4Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_4Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_4Spec;
impl crate::RegisterSpec for Pio2_4Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_4::R`](R) reader structure"]
impl crate::Readable for Pio2_4Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_4::W`](W) writer structure"]
impl crate::Writable for Pio2_4Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_4 to value 0xd0"]
impl crate::Resettable for Pio2_4Spec {
const RESET_VALUE: u32 = 0xd0;
}

319
rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs Normal file
View file

@ -0,0 +1,319 @@
#[doc = "Register `PIO2_5` reader"]
pub type R = crate::R<Pio2_5Spec>;
#[doc = "Register `PIO2_5` writer"]
pub type W = crate::W<Pio2_5Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_5."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CT32B0_MAT0."]
SelectsFunctionCt3 = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO2_5."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CT32B0_MAT0."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_5."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CT32B0_MAT0."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_5Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_5Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_5Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_5Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_5/ CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_5Spec;
impl crate::RegisterSpec for Pio2_5Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_5::R`](R) reader structure"]
impl crate::Readable for Pio2_5Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_5::W`](W) writer structure"]
impl crate::Writable for Pio2_5Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_5 to value 0xd0"]
impl crate::Resettable for Pio2_5Spec {
const RESET_VALUE: u32 = 0xd0;
}

319
rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs Normal file
View file

@ -0,0 +1,319 @@
#[doc = "Register `PIO2_6` reader"]
pub type R = crate::R<Pio2_6Spec>;
#[doc = "Register `PIO2_6` writer"]
pub type W = crate::W<Pio2_6Spec>;
#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Func {
#[doc = "0: Selects function PIO2_6."]
SelectsFunctionPio = 0,
#[doc = "1: Selects function CT32B0_MAT1."]
SelectsFunctionCt3 = 1,
}
impl From<Func> for u8 {
#[inline(always)]
fn from(variant: Func) -> Self {
variant as _
}
}
impl crate::FieldSpec for Func {
type Ux = u8;
}
#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."]
pub type FuncR = crate::FieldReader<Func>;
impl FuncR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Option<Func> {
match self.bits {
0 => Some(Func::SelectsFunctionPio),
1 => Some(Func::SelectsFunctionCt3),
_ => None,
}
}
#[doc = "Selects function PIO2_6."]
#[inline(always)]
pub fn is_selects_function_pio(&self) -> bool {
*self == Func::SelectsFunctionPio
}
#[doc = "Selects function CT32B0_MAT1."]
#[inline(always)]
pub fn is_selects_function_ct3(&self) -> bool {
*self == Func::SelectsFunctionCt3
}
}
#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."]
pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>;
impl<'a, REG> FuncW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Selects function PIO2_6."]
#[inline(always)]
pub fn selects_function_pio(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionPio)
}
#[doc = "Selects function CT32B0_MAT1."]
#[inline(always)]
pub fn selects_function_ct3(self) -> &'a mut crate::W<REG> {
self.variant(Func::SelectsFunctionCt3)
}
}
#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
#[repr(u8)]
pub enum Mode {
#[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."]
InactiveNoPullDo = 0,
#[doc = "1: Pull-down resistor enabled."]
PullDownResistorE = 1,
#[doc = "2: Pull-up resistor enabled."]
PullUpResistorEna = 2,
#[doc = "3: Repeater mode."]
RepeaterMode_ = 3,
}
impl From<Mode> for u8 {
#[inline(always)]
fn from(variant: Mode) -> Self {
variant as _
}
}
impl crate::FieldSpec for Mode {
type Ux = u8;
}
#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeR = crate::FieldReader<Mode>;
impl ModeR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Mode {
match self.bits {
0 => Mode::InactiveNoPullDo,
1 => Mode::PullDownResistorE,
2 => Mode::PullUpResistorEna,
3 => Mode::RepeaterMode_,
_ => unreachable!(),
}
}
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn is_inactive_no_pull_do(&self) -> bool {
*self == Mode::InactiveNoPullDo
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn is_pull_down_resistor_e(&self) -> bool {
*self == Mode::PullDownResistorE
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn is_pull_up_resistor_ena(&self) -> bool {
*self == Mode::PullUpResistorEna
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn is_repeater_mode_(&self) -> bool {
*self == Mode::RepeaterMode_
}
}
#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."]
pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>;
impl<'a, REG> ModeW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
REG::Ux: From<u8>,
{
#[doc = "Inactive (no pull-down/pull-up resistor enabled)."]
#[inline(always)]
pub fn inactive_no_pull_do(self) -> &'a mut crate::W<REG> {
self.variant(Mode::InactiveNoPullDo)
}
#[doc = "Pull-down resistor enabled."]
#[inline(always)]
pub fn pull_down_resistor_e(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullDownResistorE)
}
#[doc = "Pull-up resistor enabled."]
#[inline(always)]
pub fn pull_up_resistor_ena(self) -> &'a mut crate::W<REG> {
self.variant(Mode::PullUpResistorEna)
}
#[doc = "Repeater mode."]
#[inline(always)]
pub fn repeater_mode_(self) -> &'a mut crate::W<REG> {
self.variant(Mode::RepeaterMode_)
}
}
#[doc = "Hysteresis.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Hys {
#[doc = "0: Disable."]
Disable_ = 0,
#[doc = "1: Enable."]
Enable_ = 1,
}
impl From<Hys> for bool {
#[inline(always)]
fn from(variant: Hys) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `HYS` reader - Hysteresis."]
pub type HysR = crate::BitReader<Hys>;
impl HysR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Hys {
match self.bits {
false => Hys::Disable_,
true => Hys::Enable_,
}
}
#[doc = "Disable."]
#[inline(always)]
pub fn is_disable_(&self) -> bool {
*self == Hys::Disable_
}
#[doc = "Enable."]
#[inline(always)]
pub fn is_enable_(&self) -> bool {
*self == Hys::Enable_
}
}
#[doc = "Field `HYS` writer - Hysteresis."]
pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>;
impl<'a, REG> HysW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Disable."]
#[inline(always)]
pub fn disable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Disable_)
}
#[doc = "Enable."]
#[inline(always)]
pub fn enable_(self) -> &'a mut crate::W<REG> {
self.variant(Hys::Enable_)
}
}
#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Od {
#[doc = "0: Standard GPIO output"]
StandardGpioOutput = 0,
#[doc = "1: Open-drain output"]
OpenDrainOutput = 1,
}
impl From<Od> for bool {
#[inline(always)]
fn from(variant: Od) -> Self {
variant as u8 != 0
}
}
#[doc = "Field `OD` reader - Selects pseudo open-drain mode."]
pub type OdR = crate::BitReader<Od>;
impl OdR {
#[doc = "Get enumerated values variant"]
#[inline(always)]
pub const fn variant(&self) -> Od {
match self.bits {
false => Od::StandardGpioOutput,
true => Od::OpenDrainOutput,
}
}
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn is_standard_gpio_output(&self) -> bool {
*self == Od::StandardGpioOutput
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn is_open_drain_output(&self) -> bool {
*self == Od::OpenDrainOutput
}
}
#[doc = "Field `OD` writer - Selects pseudo open-drain mode."]
pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>;
impl<'a, REG> OdW<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
#[doc = "Standard GPIO output"]
#[inline(always)]
pub fn standard_gpio_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::StandardGpioOutput)
}
#[doc = "Open-drain output"]
#[inline(always)]
pub fn open_drain_output(self) -> &'a mut crate::W<REG> {
self.variant(Od::OpenDrainOutput)
}
}
impl R {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
pub fn func(&self) -> FuncR {
FuncR::new((self.bits & 7) as u8)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
pub fn mode(&self) -> ModeR {
ModeR::new(((self.bits >> 3) & 3) as u8)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
pub fn hys(&self) -> HysR {
HysR::new(((self.bits >> 5) & 1) != 0)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
pub fn od(&self) -> OdR {
OdR::new(((self.bits >> 10) & 1) != 0)
}
}
impl W {
#[doc = "Bits 0:2 - Selects pin function. All other values are reserved."]
#[inline(always)]
#[must_use]
pub fn func(&mut self) -> FuncW<Pio2_6Spec> {
FuncW::new(self, 0)
}
#[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."]
#[inline(always)]
#[must_use]
pub fn mode(&mut self) -> ModeW<Pio2_6Spec> {
ModeW::new(self, 3)
}
#[doc = "Bit 5 - Hysteresis."]
#[inline(always)]
#[must_use]
pub fn hys(&mut self) -> HysW<Pio2_6Spec> {
HysW::new(self, 5)
}
#[doc = "Bit 10 - Selects pseudo open-drain mode."]
#[inline(always)]
#[must_use]
pub fn od(&mut self) -> OdW<Pio2_6Spec> {
OdW::new(self, 10)
}
}
#[doc = "I/O configuration for pin PIO2_6/ CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Pio2_6Spec;
impl crate::RegisterSpec for Pio2_6Spec {
type Ux = u32;
}
#[doc = "`read()` method returns [`pio2_6::R`](R) reader structure"]
impl crate::Readable for Pio2_6Spec {}
#[doc = "`write(|w| ..)` method takes [`pio2_6::W`](W) writer structure"]
impl crate::Writable for Pio2_6Spec {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets PIO2_6 to value 0xd0"]
impl crate::Resettable for Pio2_6Spec {
const RESET_VALUE: u32 = 0xd0;
}

Some files were not shown because too many files have changed in this diff Show more