From 97c416c456d0534589da9948dc60316901b4de33 Mon Sep 17 00:00:00 2001 From: Artemis Tosini Date: Mon, 25 Mar 2024 06:06:51 +0000 Subject: [PATCH] i made my own pac for some reason --- rust-embedded/lpc1114-test/src/main.rs | 8 +- rust-embedded/lpc111x-pac/generate.sh | 4 + rust-embedded/lpc111x-pac/src/adc.rs | 73 ++ rust-embedded/lpc111x-pac/src/adc/cr.rs | 479 +++++++ rust-embedded/lpc111x-pac/src/adc/dr.rs | 70 + rust-embedded/lpc111x-pac/src/adc/gdr.rs | 85 ++ rust-embedded/lpc111x-pac/src/adc/inten.rs | 55 + rust-embedded/lpc111x-pac/src/adc/stat.rs | 36 + rust-embedded/lpc111x-pac/src/ct16b0.rs | 164 +++ rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs | 409 ++++++ rust-embedded/lpc111x-pac/src/ct16b0/cr.rs | 22 + rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs | 302 +++++ rust-embedded/lpc111x-pac/src/ct16b0/emr.rs | 485 +++++++ rust-embedded/lpc111x-pac/src/ct16b0/ir.rs | 115 ++ rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs | 813 ++++++++++++ rust-embedded/lpc111x-pac/src/ct16b0/mr.rs | 40 + rust-embedded/lpc111x-pac/src/ct16b0/pc.rs | 40 + rust-embedded/lpc111x-pac/src/ct16b0/pr.rs | 40 + rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs | 281 ++++ rust-embedded/lpc111x-pac/src/ct16b0/tc.rs | 40 + rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs | 59 + rust-embedded/lpc111x-pac/src/ct32b0.rs | 164 +++ rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs | 409 ++++++ rust-embedded/lpc111x-pac/src/ct32b0/cr.rs | 22 + rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs | 315 +++++ rust-embedded/lpc111x-pac/src/ct32b0/emr.rs | 485 +++++++ rust-embedded/lpc111x-pac/src/ct32b0/ir.rs | 115 ++ rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs | 813 ++++++++++++ rust-embedded/lpc111x-pac/src/ct32b0/mr.rs | 40 + rust-embedded/lpc111x-pac/src/ct32b0/pc.rs | 40 + rust-embedded/lpc111x-pac/src/ct32b0/pr.rs | 40 + rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs | 281 ++++ rust-embedded/lpc111x-pac/src/ct32b0/tc.rs | 40 + rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs | 59 + rust-embedded/lpc111x-pac/src/flashctrl.rs | 119 ++ .../lpc111x-pac/src/flashctrl/flashcfg.rs | 108 ++ .../lpc111x-pac/src/flashctrl/fmsstart.rs | 40 + .../lpc111x-pac/src/flashctrl/fmsstop.rs | 104 ++ .../lpc111x-pac/src/flashctrl/fmstat.rs | 22 + .../lpc111x-pac/src/flashctrl/fmstatclr.rs | 27 + .../lpc111x-pac/src/flashctrl/fmsw0.rs | 22 + .../lpc111x-pac/src/flashctrl/fmsw1.rs | 22 + .../lpc111x-pac/src/flashctrl/fmsw2.rs | 22 + .../lpc111x-pac/src/flashctrl/fmsw3.rs | 22 + rust-embedded/lpc111x-pac/src/generic.rs | 547 ++++++++ rust-embedded/lpc111x-pac/src/generic/raw.rs | 93 ++ rust-embedded/lpc111x-pac/src/gpio0.rs | 116 ++ rust-embedded/lpc111x-pac/src/gpio0/data.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/dir.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/ibe.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/ic.rs | 115 ++ rust-embedded/lpc111x-pac/src/gpio0/ie.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/iev.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/is.rs | 205 +++ rust-embedded/lpc111x-pac/src/gpio0/mis.rs | 99 ++ rust-embedded/lpc111x-pac/src/gpio0/ris.rs | 99 ++ rust-embedded/lpc111x-pac/src/i2c.rs | 161 +++ rust-embedded/lpc111x-pac/src/i2c/adr.rs | 55 + rust-embedded/lpc111x-pac/src/i2c/conclr.rs | 51 + rust-embedded/lpc111x-pac/src/i2c/conset.rs | 100 ++ rust-embedded/lpc111x-pac/src/i2c/dat.rs | 40 + .../lpc111x-pac/src/i2c/data_buffer.rs | 22 + rust-embedded/lpc111x-pac/src/i2c/mask.rs | 40 + rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs | 217 +++ rust-embedded/lpc111x-pac/src/i2c/sclh.rs | 40 + rust-embedded/lpc111x-pac/src/i2c/scll.rs | 40 + rust-embedded/lpc111x-pac/src/i2c/stat.rs | 22 + rust-embedded/lpc111x-pac/src/iocon.rs | 643 +++++++++ .../lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/dcd_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/dsr_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/miso1_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/mosi1_loc.rs | 95 ++ rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs | 306 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs | 178 +++ rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs | 178 +++ rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs | 332 +++++ .../lpc111x-pac/src/iocon/pio1_10.rs | 409 ++++++ .../lpc111x-pac/src/iocon/pio1_11.rs | 396 ++++++ rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs | 396 ++++++ rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs | 332 +++++ .../lpc111x-pac/src/iocon/pio2_10.rs | 306 +++++ .../lpc111x-pac/src/iocon/pio2_11.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_7.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_8.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio2_9.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_0.rs | 345 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_1.rs | 345 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_2.rs | 345 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_3.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_4.rs | 332 +++++ rust-embedded/lpc111x-pac/src/iocon/pio3_5.rs | 332 +++++ .../lpc111x-pac/src/iocon/r_pio0_11.rs | 409 ++++++ .../lpc111x-pac/src/iocon/r_pio1_0.rs | 409 ++++++ .../lpc111x-pac/src/iocon/r_pio1_1.rs | 409 ++++++ .../lpc111x-pac/src/iocon/r_pio1_2.rs | 409 ++++++ .../lpc111x-pac/src/iocon/reset_pio0_0.rs | 319 +++++ rust-embedded/lpc111x-pac/src/iocon/ri_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/rxd_loc.rs | 121 ++ .../lpc111x-pac/src/iocon/sck0_loc.rs | 108 ++ .../lpc111x-pac/src/iocon/sck1_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/ssel1_loc.rs | 95 ++ .../lpc111x-pac/src/iocon/swclk_pio0_10.rs | 345 +++++ .../lpc111x-pac/src/iocon/swdio_pio1_3.rs | 409 ++++++ rust-embedded/lpc111x-pac/src/lib.rs | 1106 ++++++++++++++++ rust-embedded/lpc111x-pac/src/pmu.rs | 48 + rust-embedded/lpc111x-pac/src/pmu/gpreg.rs | 40 + rust-embedded/lpc111x-pac/src/pmu/gpreg4.rs | 104 ++ rust-embedded/lpc111x-pac/src/pmu/pcon.rs | 217 +++ rust-embedded/lpc111x-pac/src/spi0.rs | 114 ++ rust-embedded/lpc111x-pac/src/spi0/cpsr.rs | 40 + rust-embedded/lpc111x-pac/src/spi0/cr0.rs | 464 +++++++ rust-embedded/lpc111x-pac/src/spi0/cr1.rs | 232 ++++ rust-embedded/lpc111x-pac/src/spi0/dr.rs | 40 + rust-embedded/lpc111x-pac/src/spi0/icr.rs | 35 + rust-embedded/lpc111x-pac/src/spi0/imsc.rs | 85 ++ rust-embedded/lpc111x-pac/src/spi0/mis.rs | 43 + rust-embedded/lpc111x-pac/src/spi0/ris.rs | 43 + rust-embedded/lpc111x-pac/src/spi0/sr.rs | 50 + rust-embedded/lpc111x-pac/src/syscon.rs | 452 +++++++ .../lpc111x-pac/src/syscon/bodctrl.rs | 281 ++++ .../lpc111x-pac/src/syscon/clkoutclkdiv.rs | 40 + .../lpc111x-pac/src/syscon/clkoutclksel.rs | 121 ++ .../lpc111x-pac/src/syscon/clkoutuen.rs | 89 ++ .../lpc111x-pac/src/syscon/device_id.rs | 22 + .../lpc111x-pac/src/syscon/ircctrl.rs | 40 + .../lpc111x-pac/src/syscon/mainclksel.rs | 121 ++ .../lpc111x-pac/src/syscon/mainclkuen.rs | 89 ++ .../lpc111x-pac/src/syscon/nmisrc.rs | 55 + .../lpc111x-pac/src/syscon/pdawakecfg.rs | 627 +++++++++ .../lpc111x-pac/src/syscon/pdruncfg.rs | 627 +++++++++ .../lpc111x-pac/src/syscon/pdsleepcfg.rs | 228 ++++ .../lpc111x-pac/src/syscon/pioporcap0.rs | 36 + .../lpc111x-pac/src/syscon/pioporcap1.rs | 85 ++ .../lpc111x-pac/src/syscon/presetctrl.rs | 281 ++++ .../lpc111x-pac/src/syscon/ssp0clkdiv.rs | 40 + .../lpc111x-pac/src/syscon/ssp1clkdiv.rs | 40 + .../lpc111x-pac/src/syscon/startaprp0.rs | 220 ++++ .../lpc111x-pac/src/syscon/starterp0.rs | 220 ++++ .../lpc111x-pac/src/syscon/startrsrp0clr.rs | 123 ++ .../lpc111x-pac/src/syscon/startsrp0.rs | 106 ++ .../lpc111x-pac/src/syscon/sysahbclkctrl.rs | 1165 +++++++++++++++++ .../lpc111x-pac/src/syscon/sysahbclkdiv.rs | 40 + .../lpc111x-pac/src/syscon/sysmemremap.rs | 108 ++ .../lpc111x-pac/src/syscon/sysoscctrl.rs | 153 +++ .../lpc111x-pac/src/syscon/syspllclksel.rs | 95 ++ .../lpc111x-pac/src/syscon/syspllclkuen.rs | 89 ++ .../lpc111x-pac/src/syscon/syspllctrl.rs | 136 ++ .../lpc111x-pac/src/syscon/syspllstat.rs | 56 + .../lpc111x-pac/src/syscon/sysrststat.rs | 220 ++++ .../lpc111x-pac/src/syscon/systckcal.rs | 40 + .../lpc111x-pac/src/syscon/uartclkdiv.rs | 40 + .../lpc111x-pac/src/syscon/wdtclkdiv.rs | 40 + .../lpc111x-pac/src/syscon/wdtclksel.rs | 108 ++ .../lpc111x-pac/src/syscon/wdtclkuen.rs | 89 ++ .../lpc111x-pac/src/syscon/wdtoscctrl.rs | 279 ++++ rust-embedded/lpc111x-pac/src/uart.rs | 221 ++++ rust-embedded/lpc111x-pac/src/uart/acr.rs | 345 +++++ rust-embedded/lpc111x-pac/src/uart/dll.rs | 40 + rust-embedded/lpc111x-pac/src/uart/dlm.rs | 40 + rust-embedded/lpc111x-pac/src/uart/fcr.rs | 192 +++ rust-embedded/lpc111x-pac/src/uart/fdr.rs | 55 + rust-embedded/lpc111x-pac/src/uart/ier.rs | 345 +++++ rust-embedded/lpc111x-pac/src/uart/iir.rs | 156 +++ rust-embedded/lpc111x-pac/src/uart/lcr.rs | 476 +++++++ rust-embedded/lpc111x-pac/src/uart/lsr.rs | 352 +++++ rust-embedded/lpc111x-pac/src/uart/mcr.rs | 198 +++ rust-embedded/lpc111x-pac/src/uart/msr.rs | 215 +++ rust-embedded/lpc111x-pac/src/uart/rbr.rs | 22 + .../lpc111x-pac/src/uart/rs485adrmatch.rs | 40 + .../lpc111x-pac/src/uart/rs485ctrl.rs | 409 ++++++ .../lpc111x-pac/src/uart/rs485dly.rs | 40 + rust-embedded/lpc111x-pac/src/uart/scr.rs | 40 + rust-embedded/lpc111x-pac/src/uart/ter.rs | 40 + rust-embedded/lpc111x-pac/src/uart/thr.rs | 27 + rust-embedded/lpc111x-pac/src/wwdt.rs | 79 ++ rust-embedded/lpc111x-pac/src/wwdt/wdfeed.rs | 27 + rust-embedded/lpc111x-pac/src/wwdt/wdmod.rs | 247 ++++ rust-embedded/lpc111x-pac/src/wwdt/wdtc.rs | 40 + rust-embedded/lpc111x-pac/src/wwdt/wdtv.rs | 22 + .../lpc111x-pac/src/wwdt/wdwarnint.rs | 40 + .../lpc111x-pac/src/wwdt/wdwindow.rs | 40 + rust-embedded/lpc111x-pac/svd/LPC111x.yaml | 85 ++ 200 files changed, 39004 insertions(+), 4 deletions(-) create mode 100644 rust-embedded/lpc111x-pac/src/adc.rs create mode 100644 rust-embedded/lpc111x-pac/src/adc/cr.rs create mode 100644 rust-embedded/lpc111x-pac/src/adc/dr.rs create mode 100644 rust-embedded/lpc111x-pac/src/adc/gdr.rs create mode 100644 rust-embedded/lpc111x-pac/src/adc/inten.rs create mode 100644 rust-embedded/lpc111x-pac/src/adc/stat.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/cr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/emr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/ir.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/mr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/pc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/pr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/tc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/cr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/emr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/ir.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/mr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/pc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/pr.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/tc.rs create mode 100644 rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/flashcfg.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsstart.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsstop.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmstat.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmstatclr.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsw0.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsw1.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsw2.rs create mode 100644 rust-embedded/lpc111x-pac/src/flashctrl/fmsw3.rs create mode 100644 rust-embedded/lpc111x-pac/src/generic.rs create mode 100644 rust-embedded/lpc111x-pac/src/generic/raw.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/data.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/dir.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/ibe.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/ic.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/ie.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/iev.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/is.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/mis.rs create mode 100644 rust-embedded/lpc111x-pac/src/gpio0/ris.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/adr.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/conclr.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/conset.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/dat.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/data_buffer.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/mask.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/sclh.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/scll.rs create mode 100644 rust-embedded/lpc111x-pac/src/i2c/stat.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/dcd_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/dsr_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/miso1_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/mosi1_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_10.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_11.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_10.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_11.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_7.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_8.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio2_9.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_0.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_1.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_2.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_3.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_4.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/pio3_5.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/r_pio0_11.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/r_pio1_0.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/r_pio1_1.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/r_pio1_2.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/reset_pio0_0.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/ri_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/rxd_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/sck0_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/sck1_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/ssel1_loc.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/swclk_pio0_10.rs create mode 100644 rust-embedded/lpc111x-pac/src/iocon/swdio_pio1_3.rs create mode 100644 rust-embedded/lpc111x-pac/src/lib.rs create mode 100644 rust-embedded/lpc111x-pac/src/pmu.rs create mode 100644 rust-embedded/lpc111x-pac/src/pmu/gpreg.rs create mode 100644 rust-embedded/lpc111x-pac/src/pmu/gpreg4.rs create mode 100644 rust-embedded/lpc111x-pac/src/pmu/pcon.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/cpsr.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/cr0.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/cr1.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/dr.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/icr.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/imsc.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/mis.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/ris.rs create mode 100644 rust-embedded/lpc111x-pac/src/spi0/sr.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/bodctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/clkoutclkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/clkoutclksel.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/clkoutuen.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/device_id.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/ircctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/mainclksel.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/mainclkuen.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/nmisrc.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/pdawakecfg.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/pdruncfg.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/pdsleepcfg.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/pioporcap0.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/pioporcap1.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/presetctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/ssp0clkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/ssp1clkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/startaprp0.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/starterp0.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/startrsrp0clr.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/startsrp0.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/sysahbclkctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/sysahbclkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/sysmemremap.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/sysoscctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/syspllclksel.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/syspllclkuen.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/syspllctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/syspllstat.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/sysrststat.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/systckcal.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/uartclkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/wdtclkdiv.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/wdtclksel.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/wdtclkuen.rs create mode 100644 rust-embedded/lpc111x-pac/src/syscon/wdtoscctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/acr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/dll.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/dlm.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/fcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/fdr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/ier.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/iir.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/lcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/lsr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/mcr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/msr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/rbr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/rs485adrmatch.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/rs485ctrl.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/rs485dly.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/scr.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/ter.rs create mode 100644 rust-embedded/lpc111x-pac/src/uart/thr.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdfeed.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdmod.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdtc.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdtv.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdwarnint.rs create mode 100644 rust-embedded/lpc111x-pac/src/wwdt/wdwindow.rs diff --git a/rust-embedded/lpc1114-test/src/main.rs b/rust-embedded/lpc1114-test/src/main.rs index 91b0dc0..16bf2a9 100644 --- a/rust-embedded/lpc1114-test/src/main.rs +++ b/rust-embedded/lpc1114-test/src/main.rs @@ -10,16 +10,16 @@ fn main() -> ! { let cp = cortex_m::Peripherals::take().unwrap(); // SAFETY: yes... ha ha ha... YES - let gpio0 = unsafe { &(*lpc11xx::GPIO0::ptr()) }; + let gpio0 = unsafe { &(*lpc111x_pac::Gpio0::ptr()) }; - gpio0.dir.write(|w| w.dir7().output()); + gpio0.dir().write(|w| w.io7().bit(true)); let mut delay = cortex_m::delay::Delay::new(cp.SYST, 12_000_000); loop { - gpio0.data.write(|w| w.data7().high()); + gpio0.data().write(|w| w.data7().bit(true)); delay.delay_ms(500); - gpio0.data.write(|w| w.data7().low()); + gpio0.data().write(|w| w.data7().bit(false)); delay.delay_ms(500); } } diff --git a/rust-embedded/lpc111x-pac/generate.sh b/rust-embedded/lpc111x-pac/generate.sh index e459ebe..9324258 100755 --- a/rust-embedded/lpc111x-pac/generate.sh +++ b/rust-embedded/lpc111x-pac/generate.sh @@ -3,6 +3,10 @@ set -euo pipefail svdtools patch svd/LPC111x.yaml + +# Hard to do this in svdtools, easy in sed +sed -E -i 's#(ENUM|test)##' svd/LPC111x.svd.patched + svd2rust -i svd/LPC111x.svd.patched rm -r src form -i lib.rs -o src diff --git a/rust-embedded/lpc111x-pac/src/adc.rs b/rust-embedded/lpc111x-pac/src/adc.rs new file mode 100644 index 0000000..1f5e9a0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc.rs @@ -0,0 +1,73 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cr: Cr, + gdr: Gdr, + _reserved2: [u8; 0x04], + inten: Inten, + dr: [Dr; 8], + stat: Stat, +} +impl RegisterBlock { + #[doc = "0x00 - A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."] + #[inline(always)] + pub const fn cr(&self) -> &Cr { + &self.cr + } + #[doc = "0x04 - A/D Global Data Register. Contains the result of the most recent A/D conversion."] + #[inline(always)] + pub const fn gdr(&self) -> &Gdr { + &self.gdr + } + #[doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."] + #[inline(always)] + pub const fn inten(&self) -> &Inten { + &self.inten + } + #[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."] + #[inline(always)] + pub const fn dr(&self, n: usize) -> &Dr { + &self.dr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."] + #[inline(always)] + pub fn dr_iter(&self) -> impl Iterator { + self.dr.iter() + } + #[doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } +} +#[doc = "CR (rw) register accessor: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."] +pub mod cr; +#[doc = "GDR (rw) register accessor: A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdr`] +module"] +#[doc(alias = "GDR")] +pub type Gdr = crate::Reg; +#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion."] +pub mod gdr; +#[doc = "STAT (r) register accessor: A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."] +pub mod stat; +#[doc = "INTEN (rw) register accessor: A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`] +module"] +#[doc(alias = "INTEN")] +pub type Inten = crate::Reg; +#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."] +pub mod inten; +#[doc = "DR (rw) register accessor: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] +module"] +#[doc(alias = "DR")] +pub type Dr = crate::Reg; +#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."] +pub mod dr; diff --git a/rust-embedded/lpc111x-pac/src/adc/cr.rs b/rust-embedded/lpc111x-pac/src/adc/cr.rs new file mode 100644 index 0000000..66326cf --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc/cr.rs @@ -0,0 +1,479 @@ +#[doc = "Register `CR` reader"] +pub type R = crate::R; +#[doc = "Register `CR` writer"] +pub type W = crate::W; +#[doc = "Field `SEL` reader - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."] +pub type SelR = crate::FieldReader; +#[doc = "Field `SEL` writer - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."] +pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLKDIV` reader - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."] +pub type ClkdivR = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."] +pub type ClkdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Burst mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Burst { + #[doc = "0: Software-controlled mode: Conversions are software-controlled and require 11 clocks."] + Swmode = 0, + #[doc = "1: Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."] + Hwmode = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Burst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BURST` reader - Burst mode"] +pub type BurstR = crate::BitReader; +impl BurstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Burst { + match self.bits { + false => Burst::Swmode, + true => Burst::Hwmode, + } + } + #[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."] + #[inline(always)] + pub fn is_swmode(&self) -> bool { + *self == Burst::Swmode + } + #[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."] + #[inline(always)] + pub fn is_hwmode(&self) -> bool { + *self == Burst::Hwmode + } +} +#[doc = "Field `BURST` writer - Burst mode"] +pub type BurstW<'a, REG> = crate::BitWriter<'a, REG, Burst>; +impl<'a, REG> BurstW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."] + #[inline(always)] + pub fn swmode(self) -> &'a mut crate::W { + self.variant(Burst::Swmode) + } + #[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."] + #[inline(always)] + pub fn hwmode(self) -> &'a mut crate::W { + self.variant(Burst::Hwmode) + } +} +#[doc = "This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Clks { + #[doc = "0: 11 clocks / 10 bits"] + _10bit = 0, + #[doc = "1: 10 clocks / 9 bits"] + _9bit = 1, + #[doc = "2: 9 clocks / 8 bits"] + _8bit = 2, + #[doc = "3: 8 clocks / 7 bits"] + _7bit = 3, + #[doc = "4: 7 clocks / 6 bits"] + _6bit = 4, + #[doc = "5: 6 clocks / 5 bits"] + _5bit = 5, + #[doc = "6: 5 clocks / 4 bits"] + _4bit = 6, + #[doc = "7: 4 clocks / 3 bits"] + _3bit = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Clks) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Clks { + type Ux = u8; +} +#[doc = "Field `CLKS` reader - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."] +pub type ClksR = crate::FieldReader; +impl ClksR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Clks { + match self.bits { + 0 => Clks::_10bit, + 1 => Clks::_9bit, + 2 => Clks::_8bit, + 3 => Clks::_7bit, + 4 => Clks::_6bit, + 5 => Clks::_5bit, + 6 => Clks::_4bit, + 7 => Clks::_3bit, + _ => unreachable!(), + } + } + #[doc = "11 clocks / 10 bits"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + *self == Clks::_10bit + } + #[doc = "10 clocks / 9 bits"] + #[inline(always)] + pub fn is_9bit(&self) -> bool { + *self == Clks::_9bit + } + #[doc = "9 clocks / 8 bits"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == Clks::_8bit + } + #[doc = "8 clocks / 7 bits"] + #[inline(always)] + pub fn is_7bit(&self) -> bool { + *self == Clks::_7bit + } + #[doc = "7 clocks / 6 bits"] + #[inline(always)] + pub fn is_6bit(&self) -> bool { + *self == Clks::_6bit + } + #[doc = "6 clocks / 5 bits"] + #[inline(always)] + pub fn is_5bit(&self) -> bool { + *self == Clks::_5bit + } + #[doc = "5 clocks / 4 bits"] + #[inline(always)] + pub fn is_4bit(&self) -> bool { + *self == Clks::_4bit + } + #[doc = "4 clocks / 3 bits"] + #[inline(always)] + pub fn is_3bit(&self) -> bool { + *self == Clks::_3bit + } +} +#[doc = "Field `CLKS` writer - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."] +pub type ClksW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Clks>; +impl<'a, REG> ClksW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "11 clocks / 10 bits"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut crate::W { + self.variant(Clks::_10bit) + } + #[doc = "10 clocks / 9 bits"] + #[inline(always)] + pub fn _9bit(self) -> &'a mut crate::W { + self.variant(Clks::_9bit) + } + #[doc = "9 clocks / 8 bits"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut crate::W { + self.variant(Clks::_8bit) + } + #[doc = "8 clocks / 7 bits"] + #[inline(always)] + pub fn _7bit(self) -> &'a mut crate::W { + self.variant(Clks::_7bit) + } + #[doc = "7 clocks / 6 bits"] + #[inline(always)] + pub fn _6bit(self) -> &'a mut crate::W { + self.variant(Clks::_6bit) + } + #[doc = "6 clocks / 5 bits"] + #[inline(always)] + pub fn _5bit(self) -> &'a mut crate::W { + self.variant(Clks::_5bit) + } + #[doc = "5 clocks / 4 bits"] + #[inline(always)] + pub fn _4bit(self) -> &'a mut crate::W { + self.variant(Clks::_4bit) + } + #[doc = "4 clocks / 3 bits"] + #[inline(always)] + pub fn _3bit(self) -> &'a mut crate::W { + self.variant(Clks::_3bit) + } +} +#[doc = "When the BURST bit is 0, these bits control whether and when an A/D conversion is started:\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Start { + #[doc = "0: No start (this value should be used when clearing PDN to 0)."] + Stop = 0, + #[doc = "1: Start conversion now."] + Start = 1, + #[doc = "2: Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."] + Edgepio0_2 = 2, + #[doc = "3: Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."] + Edgepio1_5 = 3, + #[doc = "4: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."] + Edgect32b0Mat0_1 = 4, + #[doc = "5: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."] + Edgect32b0Mat1_1 = 5, + #[doc = "6: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."] + Edgect16b0Mat0_1 = 6, + #[doc = "7: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."] + Edgect16b0Mat1_1 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Start) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Start { + type Ux = u8; +} +#[doc = "Field `START` reader - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"] +pub type StartR = crate::FieldReader; +impl StartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Start { + match self.bits { + 0 => Start::Stop, + 1 => Start::Start, + 2 => Start::Edgepio0_2, + 3 => Start::Edgepio1_5, + 4 => Start::Edgect32b0Mat0_1, + 5 => Start::Edgect32b0Mat1_1, + 6 => Start::Edgect16b0Mat0_1, + 7 => Start::Edgect16b0Mat1_1, + _ => unreachable!(), + } + } + #[doc = "No start (this value should be used when clearing PDN to 0)."] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == Start::Stop + } + #[doc = "Start conversion now."] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == Start::Start + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."] + #[inline(always)] + pub fn is_edgepio0_2(&self) -> bool { + *self == Start::Edgepio0_2 + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."] + #[inline(always)] + pub fn is_edgepio1_5(&self) -> bool { + *self == Start::Edgepio1_5 + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."] + #[inline(always)] + pub fn is_edgect32b0_mat0_1(&self) -> bool { + *self == Start::Edgect32b0Mat0_1 + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."] + #[inline(always)] + pub fn is_edgect32b0_mat1_1(&self) -> bool { + *self == Start::Edgect32b0Mat1_1 + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."] + #[inline(always)] + pub fn is_edgect16b0_mat0_1(&self) -> bool { + *self == Start::Edgect16b0Mat0_1 + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."] + #[inline(always)] + pub fn is_edgect16b0_mat1_1(&self) -> bool { + *self == Start::Edgect16b0Mat1_1 + } +} +#[doc = "Field `START` writer - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"] +pub type StartW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Start>; +impl<'a, REG> StartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No start (this value should be used when clearing PDN to 0)."] + #[inline(always)] + pub fn stop(self) -> &'a mut crate::W { + self.variant(Start::Stop) + } + #[doc = "Start conversion now."] + #[inline(always)] + pub fn start(self) -> &'a mut crate::W { + self.variant(Start::Start) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."] + #[inline(always)] + pub fn edgepio0_2(self) -> &'a mut crate::W { + self.variant(Start::Edgepio0_2) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."] + #[inline(always)] + pub fn edgepio1_5(self) -> &'a mut crate::W { + self.variant(Start::Edgepio1_5) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."] + #[inline(always)] + pub fn edgect32b0_mat0_1(self) -> &'a mut crate::W { + self.variant(Start::Edgect32b0Mat0_1) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."] + #[inline(always)] + pub fn edgect32b0_mat1_1(self) -> &'a mut crate::W { + self.variant(Start::Edgect32b0Mat1_1) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."] + #[inline(always)] + pub fn edgect16b0_mat0_1(self) -> &'a mut crate::W { + self.variant(Start::Edgect16b0Mat0_1) + } + #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."] + #[inline(always)] + pub fn edgect16b0_mat1_1(self) -> &'a mut crate::W { + self.variant(Start::Edgect16b0Mat1_1) + } +} +#[doc = "This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Edge { + #[doc = "0: Start conversion on a rising edge on the selected CAP/MAT signal."] + Rising = 0, + #[doc = "1: Start conversion on a rising edge on the selected CAP/MAT signal."] + Falling = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Edge) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EDGE` reader - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."] +pub type EdgeR = crate::BitReader; +impl EdgeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Edge { + match self.bits { + false => Edge::Rising, + true => Edge::Falling, + } + } + #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."] + #[inline(always)] + pub fn is_rising(&self) -> bool { + *self == Edge::Rising + } + #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."] + #[inline(always)] + pub fn is_falling(&self) -> bool { + *self == Edge::Falling + } +} +#[doc = "Field `EDGE` writer - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."] +pub type EdgeW<'a, REG> = crate::BitWriter<'a, REG, Edge>; +impl<'a, REG> EdgeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."] + #[inline(always)] + pub fn rising(self) -> &'a mut crate::W { + self.variant(Edge::Rising) + } + #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."] + #[inline(always)] + pub fn falling(self) -> &'a mut crate::W { + self.variant(Edge::Falling) + } +} +impl R { + #[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."] + #[inline(always)] + pub fn clkdiv(&self) -> ClkdivR { + ClkdivR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - Burst mode"] + #[inline(always)] + pub fn burst(&self) -> BurstR { + BurstR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."] + #[inline(always)] + pub fn clks(&self) -> ClksR { + ClksR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."] + #[inline(always)] + pub fn edge(&self) -> EdgeR { + EdgeR::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 0) + } + #[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> ClkdivW { + ClkdivW::new(self, 8) + } + #[doc = "Bit 16 - Burst mode"] + #[inline(always)] + #[must_use] + pub fn burst(&mut self) -> BurstW { + BurstW::new(self, 16) + } + #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."] + #[inline(always)] + #[must_use] + pub fn clks(&mut self) -> ClksW { + ClksW::new(self, 17) + } + #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> StartW { + StartW::new(self, 24) + } + #[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."] + #[inline(always)] + #[must_use] + pub fn edge(&mut self) -> EdgeW { + EdgeW::new(self, 27) + } +} +#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] +impl crate::Writable for CrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CR to value 0"] +impl crate::Resettable for CrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/adc/dr.rs b/rust-embedded/lpc111x-pac/src/adc/dr.rs new file mode 100644 index 0000000..d9024d5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc/dr.rs @@ -0,0 +1,70 @@ +#[doc = "Register `DR%s` reader"] +pub type R = crate::R; +#[doc = "Register `DR%s` writer"] +pub type W = crate::W; +#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."] +pub type VVrefR = crate::FieldReader; +#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."] +pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."] +pub type OverrunR = crate::BitReader; +#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."] +pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."] +pub type DoneR = crate::BitReader; +#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."] +pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."] + #[inline(always)] + pub fn v_vref(&self) -> VVrefR { + VVrefR::new(((self.bits >> 6) & 0x03ff) as u16) + } + #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."] + #[inline(always)] + pub fn overrun(&self) -> OverrunR { + OverrunR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."] + #[inline(always)] + pub fn done(&self) -> DoneR { + DoneR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."] + #[inline(always)] + #[must_use] + pub fn v_vref(&mut self) -> VVrefW { + VVrefW::new(self, 6) + } + #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."] + #[inline(always)] + #[must_use] + pub fn overrun(&mut self) -> OverrunW { + OverrunW::new(self, 30) + } + #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DoneW { + DoneW::new(self, 31) + } +} +#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DrSpec; +impl crate::RegisterSpec for DrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dr::R`](R) reader structure"] +impl crate::Readable for DrSpec {} +#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"] +impl crate::Writable for DrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DR%s to value 0"] +impl crate::Resettable for DrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/adc/gdr.rs b/rust-embedded/lpc111x-pac/src/adc/gdr.rs new file mode 100644 index 0000000..5495fab --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc/gdr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `GDR` reader"] +pub type R = crate::R; +#[doc = "Register `GDR` writer"] +pub type W = crate::W; +#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."] +pub type VVrefR = crate::FieldReader; +#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."] +pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `CHN` reader - These bits contain the channel from which the result bits V_VREF were converted."] +pub type ChnR = crate::FieldReader; +#[doc = "Field `CHN` writer - These bits contain the channel from which the result bits V_VREF were converted."] +pub type ChnW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."] +pub type OverrunR = crate::BitReader; +#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."] +pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."] +pub type DoneR = crate::BitReader; +#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."] +pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."] + #[inline(always)] + pub fn v_vref(&self) -> VVrefR { + VVrefR::new(((self.bits >> 6) & 0x03ff) as u16) + } + #[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."] + #[inline(always)] + pub fn chn(&self) -> ChnR { + ChnR::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."] + #[inline(always)] + pub fn overrun(&self) -> OverrunR { + OverrunR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."] + #[inline(always)] + pub fn done(&self) -> DoneR { + DoneR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."] + #[inline(always)] + #[must_use] + pub fn v_vref(&mut self) -> VVrefW { + VVrefW::new(self, 6) + } + #[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."] + #[inline(always)] + #[must_use] + pub fn chn(&mut self) -> ChnW { + ChnW::new(self, 24) + } + #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."] + #[inline(always)] + #[must_use] + pub fn overrun(&mut self) -> OverrunW { + OverrunW::new(self, 30) + } + #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DoneW { + DoneW::new(self, 31) + } +} +#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GdrSpec; +impl crate::RegisterSpec for GdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gdr::R`](R) reader structure"] +impl crate::Readable for GdrSpec {} +#[doc = "`write(|w| ..)` method takes [`gdr::W`](W) writer structure"] +impl crate::Writable for GdrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GDR to value 0"] +impl crate::Resettable for GdrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/adc/inten.rs b/rust-embedded/lpc111x-pac/src/adc/inten.rs new file mode 100644 index 0000000..adb6488 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc/inten.rs @@ -0,0 +1,55 @@ +#[doc = "Register `INTEN` reader"] +pub type R = crate::R; +#[doc = "Register `INTEN` writer"] +pub type W = crate::W; +#[doc = "Field `ADINTENn` reader - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."] +pub type AdintennR = crate::FieldReader; +#[doc = "Field `ADINTENn` writer - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."] +pub type AdintennW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ADGINTEN` reader - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."] +pub type AdgintenR = crate::BitReader; +#[doc = "Field `ADGINTEN` writer - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."] +pub type AdgintenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."] + #[inline(always)] + pub fn adintenn(&self) -> AdintennR { + AdintennR::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."] + #[inline(always)] + pub fn adginten(&self) -> AdgintenR { + AdgintenR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."] + #[inline(always)] + #[must_use] + pub fn adintenn(&mut self) -> AdintennW { + AdintennW::new(self, 0) + } + #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."] + #[inline(always)] + #[must_use] + pub fn adginten(&mut self) -> AdgintenW { + AdgintenW::new(self, 8) + } +} +#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntenSpec; +impl crate::RegisterSpec for IntenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`inten::R`](R) reader structure"] +impl crate::Readable for IntenSpec {} +#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"] +impl crate::Writable for IntenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTEN to value 0x0100"] +impl crate::Resettable for IntenSpec { + const RESET_VALUE: u32 = 0x0100; +} diff --git a/rust-embedded/lpc111x-pac/src/adc/stat.rs b/rust-embedded/lpc111x-pac/src/adc/stat.rs new file mode 100644 index 0000000..6acc5cb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/adc/stat.rs @@ -0,0 +1,36 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Field `DONE` reader - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."] +pub type DoneR = crate::FieldReader; +#[doc = "Field `OVERRUN` reader - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."] +pub type OverrunR = crate::FieldReader; +#[doc = "Field `ADINT` reader - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."] +pub type AdintR = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."] + #[inline(always)] + pub fn done(&self) -> DoneR { + DoneR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."] + #[inline(always)] + pub fn overrun(&self) -> OverrunR { + OverrunR::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."] + #[inline(always)] + pub fn adint(&self) -> AdintR { + AdintR::new(((self.bits >> 16) & 1) != 0) + } +} +#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0.rs b/rust-embedded/lpc111x-pac/src/ct16b0.rs new file mode 100644 index 0000000..30805e1 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0.rs @@ -0,0 +1,164 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ir: Ir, + tcr: Tcr, + tc: Tc, + pr: Pr, + pc: Pc, + mcr: Mcr, + mr: [Mr; 4], + ccr: Ccr, + cr: [Cr; 2], + _reserved9: [u8; 0x08], + emr: Emr, + _reserved10: [u8; 0x30], + ctcr: Ctcr, + pwmc: Pwmc, +} +impl RegisterBlock { + #[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."] + #[inline(always)] + pub const fn ir(&self) -> &Ir { + &self.ir + } + #[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x08 - Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."] + #[inline(always)] + pub const fn pr(&self) -> &Pr { + &self.pr + } + #[doc = "0x10 - Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."] + #[inline(always)] + pub const fn pc(&self) -> &Pc { + &self.pc + } + #[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] + #[inline(always)] + pub const fn mr(&self, n: usize) -> &Mr { + &self.mr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] + #[inline(always)] + pub fn mr_iter(&self) -> impl Iterator { + self.mr.iter() + } + #[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."] + #[inline(always)] + pub const fn ccr(&self) -> &Ccr { + &self.ccr + } + #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] + #[inline(always)] + pub const fn cr(&self, n: usize) -> &Cr { + &self.cr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] + #[inline(always)] + pub fn cr_iter(&self) -> impl Iterator { + self.cr.iter() + } + #[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."] + #[inline(always)] + pub const fn emr(&self) -> &Emr { + &self.emr + } + #[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."] + #[inline(always)] + pub const fn ctcr(&self) -> &Ctcr { + &self.ctcr + } + #[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."] + #[inline(always)] + pub const fn pwmc(&self) -> &Pwmc { + &self.pwmc + } +} +#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`] +module"] +#[doc(alias = "IR")] +pub type Ir = crate::Reg; +#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."] +pub mod ir; +#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] +module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."] +pub mod tcr; +#[doc = "TC (rw) register accessor: Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] +module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."] +pub mod tc; +#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`] +module"] +#[doc(alias = "PR")] +pub type Pr = crate::Reg; +#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."] +pub mod pr; +#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] +module"] +#[doc(alias = "PC")] +pub type Pc = crate::Reg; +#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."] +pub mod pc; +#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."] +pub mod mcr; +#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`] +module"] +#[doc(alias = "MR")] +pub type Mr = crate::Reg; +#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] +pub mod mr; +#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] +module"] +#[doc(alias = "CCR")] +pub type Ccr = crate::Reg; +#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."] +pub mod ccr; +#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] +pub mod cr; +#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`] +module"] +#[doc(alias = "EMR")] +pub type Emr = crate::Reg; +#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."] +pub mod emr; +#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`] +module"] +#[doc(alias = "CTCR")] +pub type Ctcr = crate::Reg; +#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."] +pub mod ctcr; +#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`] +module"] +#[doc(alias = "PWMC")] +pub type Pwmc = crate::Reg; +#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."] +pub mod pwmc; diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs new file mode 100644 index 0000000..3eba3a4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CCR` reader"] +pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; +#[doc = "Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0re { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0RE` reader - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0reR = crate::BitReader; +impl Cap0reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0re { + match self.bits { + true => Cap0re::Enabled, + false => Cap0re::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0re::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0re::Disabled + } +} +#[doc = "Field `CAP0RE` writer - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>; +impl<'a, REG> Cap0reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0re::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0re::Disabled) + } +} +#[doc = "Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0fe { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0FE` reader - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0feR = crate::BitReader; +impl Cap0feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0fe { + match self.bits { + true => Cap0fe::Enabled, + false => Cap0fe::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0fe::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0fe::Disabled + } +} +#[doc = "Field `CAP0FE` writer - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>; +impl<'a, REG> Cap0feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0fe::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0fe::Disabled) + } +} +#[doc = "Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0I` reader - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."] +pub type Cap0iR = crate::BitReader; +impl Cap0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0i { + match self.bits { + true => Cap0i::Enabled, + false => Cap0i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0i::Disabled + } +} +#[doc = "Field `CAP0I` writer - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."] +pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>; +impl<'a, REG> Cap0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0i::Disabled) + } +} +#[doc = "Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1re { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1RE` reader - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1reR = crate::BitReader; +impl Cap1reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1re { + match self.bits { + true => Cap1re::Enabled, + false => Cap1re::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1re::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1re::Disabled + } +} +#[doc = "Field `CAP1RE` writer - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>; +impl<'a, REG> Cap1reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1re::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1re::Disabled) + } +} +#[doc = "Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1fe { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1FE` reader - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1feR = crate::BitReader; +impl Cap1feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1fe { + match self.bits { + true => Cap1fe::Enabled, + false => Cap1fe::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1fe::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1fe::Disabled + } +} +#[doc = "Field `CAP1FE` writer - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>; +impl<'a, REG> Cap1feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1fe::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1fe::Disabled) + } +} +#[doc = "Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1I` reader - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."] +pub type Cap1iR = crate::BitReader; +impl Cap1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1i { + match self.bits { + true => Cap1i::Enabled, + false => Cap1i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1i::Disabled + } +} +#[doc = "Field `CAP1I` writer - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."] +pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>; +impl<'a, REG> Cap1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1i::Disabled) + } +} +impl R { + #[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap0re(&self) -> Cap0reR { + Cap0reR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap0fe(&self) -> Cap0feR { + Cap0feR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."] + #[inline(always)] + pub fn cap0i(&self) -> Cap0iR { + Cap0iR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap1re(&self) -> Cap1reR { + Cap1reR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap1fe(&self) -> Cap1feR { + Cap1feR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."] + #[inline(always)] + pub fn cap1i(&self) -> Cap1iR { + Cap1iR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap0re(&mut self) -> Cap0reW { + Cap0reW::new(self, 0) + } + #[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap0fe(&mut self) -> Cap0feW { + Cap0feW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."] + #[inline(always)] + #[must_use] + pub fn cap0i(&mut self) -> Cap0iW { + Cap0iW::new(self, 2) + } + #[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap1re(&mut self) -> Cap1reW { + Cap1reW::new(self, 3) + } + #[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap1fe(&mut self) -> Cap1feW { + Cap1feW::new(self, 4) + } + #[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."] + #[inline(always)] + #[must_use] + pub fn cap1i(&mut self) -> Cap1iW { + Cap1iW::new(self, 5) + } +} +#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CcrSpec; +impl crate::RegisterSpec for CcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CCR to value 0"] +impl crate::Resettable for CcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs new file mode 100644 index 0000000..0430469 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `CR%s` reader"] +pub type R = crate::R; +#[doc = "Field `CAP` reader - Timer counter capture value."] +pub type CapR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Timer counter capture value."] + #[inline(always)] + pub fn cap(&self) -> CapR { + CapR::new((self.bits & 0xffff) as u16) + } +} +#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`reset()` method sets CR%s to value 0"] +impl crate::Resettable for CrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs new file mode 100644 index 0000000..d50bbc4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs @@ -0,0 +1,302 @@ +#[doc = "Register `CTCR` reader"] +pub type R = crate::R; +#[doc = "Register `CTCR` writer"] +pub type W = crate::W; +#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctm { + #[doc = "0: Increment on every rising PCLK edge"] + Timer = 0, + #[doc = "1: Increment on rising CAP pin edge"] + CounterRising = 1, + #[doc = "2: Increment on falling CAP pin edge"] + CounterFalling = 2, + #[doc = "3: Increment on both CAP pin edges"] + CounterBoth = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctm) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctm { + type Ux = u8; +} +#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."] +pub type CtmR = crate::FieldReader; +impl CtmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctm { + match self.bits { + 0 => Ctm::Timer, + 1 => Ctm::CounterRising, + 2 => Ctm::CounterFalling, + 3 => Ctm::CounterBoth, + _ => unreachable!(), + } + } + #[doc = "Increment on every rising PCLK edge"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == Ctm::Timer + } + #[doc = "Increment on rising CAP pin edge"] + #[inline(always)] + pub fn is_counter_rising(&self) -> bool { + *self == Ctm::CounterRising + } + #[doc = "Increment on falling CAP pin edge"] + #[inline(always)] + pub fn is_counter_falling(&self) -> bool { + *self == Ctm::CounterFalling + } + #[doc = "Increment on both CAP pin edges"] + #[inline(always)] + pub fn is_counter_both(&self) -> bool { + *self == Ctm::CounterBoth + } +} +#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."] +pub type CtmW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctm>; +impl<'a, REG> CtmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Increment on every rising PCLK edge"] + #[inline(always)] + pub fn timer(self) -> &'a mut crate::W { + self.variant(Ctm::Timer) + } + #[doc = "Increment on rising CAP pin edge"] + #[inline(always)] + pub fn counter_rising(self) -> &'a mut crate::W { + self.variant(Ctm::CounterRising) + } + #[doc = "Increment on falling CAP pin edge"] + #[inline(always)] + pub fn counter_falling(self) -> &'a mut crate::W { + self.variant(Ctm::CounterFalling) + } + #[doc = "Increment on both CAP pin edges"] + #[inline(always)] + pub fn counter_both(self) -> &'a mut crate::W { + self.variant(Ctm::CounterBoth) + } +} +#[doc = "Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cis { + #[doc = "0: CT16Bn_CAP0"] + Ct16bnCap0 = 0, + #[doc = "1: CT16Bn_CAP1"] + Ct16bnCap1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cis) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cis { + type Ux = u8; +} +#[doc = "Field `CIS` reader - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."] +pub type CisR = crate::FieldReader; +impl CisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Cis::Ct16bnCap0), + 1 => Some(Cis::Ct16bnCap1), + _ => None, + } + } + #[doc = "CT16Bn_CAP0"] + #[inline(always)] + pub fn is_ct16bn_cap0(&self) -> bool { + *self == Cis::Ct16bnCap0 + } + #[doc = "CT16Bn_CAP1"] + #[inline(always)] + pub fn is_ct16bn_cap1(&self) -> bool { + *self == Cis::Ct16bnCap1 + } +} +#[doc = "Field `CIS` writer - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."] +pub type CisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cis>; +impl<'a, REG> CisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT16Bn_CAP0"] + #[inline(always)] + pub fn ct16bn_cap0(self) -> &'a mut crate::W { + self.variant(Cis::Ct16bnCap0) + } + #[doc = "CT16Bn_CAP1"] + #[inline(always)] + pub fn ct16bn_cap1(self) -> &'a mut crate::W { + self.variant(Cis::Ct16bnCap1) + } +} +#[doc = "Field `ENCC` reader - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] +pub type EnccR = crate::BitReader; +#[doc = "Field `ENCC` writer - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] +pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Selcc { + #[doc = "0: Rising Edge of CAP0 clears the timer"] + Cap0Rising = 0, + #[doc = "1: Falling Edge of CAP0 clears the timer"] + Cap0Falling = 1, + #[doc = "2: Rising Edge of CAP1 clears the timer"] + Cap1Rising = 2, + #[doc = "3: Falling Edge of CAP1 clears the timer"] + Cap1Falling = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Selcc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Selcc { + type Ux = u8; +} +#[doc = "Field `SELCC` reader - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] +pub type SelccR = crate::FieldReader; +impl SelccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Selcc::Cap0Rising), + 1 => Some(Selcc::Cap0Falling), + 2 => Some(Selcc::Cap1Rising), + 3 => Some(Selcc::Cap1Falling), + _ => None, + } + } + #[doc = "Rising Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn is_cap0_rising(&self) -> bool { + *self == Selcc::Cap0Rising + } + #[doc = "Falling Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn is_cap0_falling(&self) -> bool { + *self == Selcc::Cap0Falling + } + #[doc = "Rising Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn is_cap1_rising(&self) -> bool { + *self == Selcc::Cap1Rising + } + #[doc = "Falling Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn is_cap1_falling(&self) -> bool { + *self == Selcc::Cap1Falling + } +} +#[doc = "Field `SELCC` writer - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] +pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc>; +impl<'a, REG> SelccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Rising Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn cap0_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Cap0Rising) + } + #[doc = "Falling Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn cap0_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Cap0Falling) + } + #[doc = "Rising Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn cap1_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Cap1Rising) + } + #[doc = "Falling Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn cap1_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Cap1Falling) + } +} +impl R { + #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."] + #[inline(always)] + pub fn ctm(&self) -> CtmR { + CtmR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."] + #[inline(always)] + pub fn cis(&self) -> CisR { + CisR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] + #[inline(always)] + pub fn encc(&self) -> EnccR { + EnccR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] + #[inline(always)] + pub fn selcc(&self) -> SelccR { + SelccR::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."] + #[inline(always)] + #[must_use] + pub fn ctm(&mut self) -> CtmW { + CtmW::new(self, 0) + } + #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."] + #[inline(always)] + #[must_use] + pub fn cis(&mut self) -> CisW { + CisW::new(self, 2) + } + #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] + #[inline(always)] + #[must_use] + pub fn encc(&mut self) -> EnccW { + EnccW::new(self, 4) + } + #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] + #[inline(always)] + #[must_use] + pub fn selcc(&mut self) -> SelccW { + SelccW::new(self, 5) + } +} +#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtcrSpec; +impl crate::RegisterSpec for CtcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"] +impl crate::Readable for CtcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"] +impl crate::Writable for CtcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTCR to value 0"] +impl crate::Resettable for CtcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs new file mode 100644 index 0000000..038e606 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs @@ -0,0 +1,485 @@ +#[doc = "Register `EMR` reader"] +pub type R = crate::R; +#[doc = "Register `EMR` writer"] +pub type W = crate::W; +#[doc = "Field `EM0` reader - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em0R = crate::BitReader; +#[doc = "Field `EM0` writer - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM1` reader - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em1R = crate::BitReader; +#[doc = "Field `EM1` writer - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM2` reader - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em2R = crate::BitReader; +#[doc = "Field `EM2` writer - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM3` reader - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."] +pub type Em3R = crate::BitReader; +#[doc = "Field `EM3` writer - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."] +pub type Em3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "External Match Control 0. Determines the functionality of External Match 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc0 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc0 { + type Ux = u8; +} +#[doc = "Field `EMC0` reader - External Match Control 0. Determines the functionality of External Match 0."] +pub type Emc0R = crate::FieldReader; +impl Emc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc0 { + match self.bits { + 0 => Emc0::DoNothing_, + 1 => Emc0::ClearTheCorrespond, + 2 => Emc0::SetTheCorrespondin, + 3 => Emc0::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc0::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc0::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc0::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc0::ToggleTheCorrespon + } +} +#[doc = "Field `EMC0` writer - External Match Control 0. Determines the functionality of External Match 0."] +pub type Emc0W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc0>; +impl<'a, REG> Emc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc0::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc0::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc0::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc0::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 1. Determines the functionality of External Match 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc1 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc1 { + type Ux = u8; +} +#[doc = "Field `EMC1` reader - External Match Control 1. Determines the functionality of External Match 1."] +pub type Emc1R = crate::FieldReader; +impl Emc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc1 { + match self.bits { + 0 => Emc1::DoNothing_, + 1 => Emc1::ClearTheCorrespond, + 2 => Emc1::SetTheCorrespondin, + 3 => Emc1::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc1::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc1::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc1::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc1::ToggleTheCorrespon + } +} +#[doc = "Field `EMC1` writer - External Match Control 1. Determines the functionality of External Match 1."] +pub type Emc1W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc1>; +impl<'a, REG> Emc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc1::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc1::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc1::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc1::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 2. Determines the functionality of External Match 2.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc2 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc2 { + type Ux = u8; +} +#[doc = "Field `EMC2` reader - External Match Control 2. Determines the functionality of External Match 2."] +pub type Emc2R = crate::FieldReader; +impl Emc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc2 { + match self.bits { + 0 => Emc2::DoNothing_, + 1 => Emc2::ClearTheCorrespond, + 2 => Emc2::SetTheCorrespondin, + 3 => Emc2::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc2::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc2::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc2::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc2::ToggleTheCorrespon + } +} +#[doc = "Field `EMC2` writer - External Match Control 2. Determines the functionality of External Match 2."] +pub type Emc2W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc2>; +impl<'a, REG> Emc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc2::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc2::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc2::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc2::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 3. Determines the functionality of External Match 3.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc3 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc3 { + type Ux = u8; +} +#[doc = "Field `EMC3` reader - External Match Control 3. Determines the functionality of External Match 3."] +pub type Emc3R = crate::FieldReader; +impl Emc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc3 { + match self.bits { + 0 => Emc3::DoNothing_, + 1 => Emc3::ClearTheCorrespond, + 2 => Emc3::SetTheCorrespondin, + 3 => Emc3::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc3::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc3::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc3::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc3::ToggleTheCorrespon + } +} +#[doc = "Field `EMC3` writer - External Match Control 3. Determines the functionality of External Match 3."] +pub type Emc3W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc3>; +impl<'a, REG> Emc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc3::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc3::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc3::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc3::ToggleTheCorrespon) + } +} +impl R { + #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em0(&self) -> Em0R { + Em0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em1(&self) -> Em1R { + Em1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em2(&self) -> Em2R { + Em2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."] + #[inline(always)] + pub fn em3(&self) -> Em3R { + Em3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."] + #[inline(always)] + pub fn emc0(&self) -> Emc0R { + Emc0R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."] + #[inline(always)] + pub fn emc1(&self) -> Emc1R { + Emc1R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."] + #[inline(always)] + pub fn emc2(&self) -> Emc2R { + Emc2R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."] + #[inline(always)] + pub fn emc3(&self) -> Emc3R { + Emc3R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em0(&mut self) -> Em0W { + Em0W::new(self, 0) + } + #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em1(&mut self) -> Em1W { + Em1W::new(self, 1) + } + #[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em2(&mut self) -> Em2W { + Em2W::new(self, 2) + } + #[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."] + #[inline(always)] + #[must_use] + pub fn em3(&mut self) -> Em3W { + Em3W::new(self, 3) + } + #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."] + #[inline(always)] + #[must_use] + pub fn emc0(&mut self) -> Emc0W { + Emc0W::new(self, 4) + } + #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."] + #[inline(always)] + #[must_use] + pub fn emc1(&mut self) -> Emc1W { + Emc1W::new(self, 6) + } + #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."] + #[inline(always)] + #[must_use] + pub fn emc2(&mut self) -> Emc2W { + Emc2W::new(self, 8) + } + #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."] + #[inline(always)] + #[must_use] + pub fn emc3(&mut self) -> Emc3W { + Emc3W::new(self, 10) + } +} +#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EmrSpec; +impl crate::RegisterSpec for EmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`emr::R`](R) reader structure"] +impl crate::Readable for EmrSpec {} +#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] +impl crate::Writable for EmrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EMR to value 0"] +impl crate::Resettable for EmrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs new file mode 100644 index 0000000..ba6862b --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs @@ -0,0 +1,115 @@ +#[doc = "Register `IR` reader"] +pub type R = crate::R; +#[doc = "Register `IR` writer"] +pub type W = crate::W; +#[doc = "Field `MR0INT` reader - Interrupt flag for match channel 0."] +pub type Mr0intR = crate::BitReader; +#[doc = "Field `MR0INT` writer - Interrupt flag for match channel 0."] +pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR1INT` reader - Interrupt flag for match channel 1."] +pub type Mr1intR = crate::BitReader; +#[doc = "Field `MR1INT` writer - Interrupt flag for match channel 1."] +pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR2INT` reader - Interrupt flag for match channel 2."] +pub type Mr2intR = crate::BitReader; +#[doc = "Field `MR2INT` writer - Interrupt flag for match channel 2."] +pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR3INT` reader - Interrupt flag for match channel 3."] +pub type Mr3intR = crate::BitReader; +#[doc = "Field `MR3INT` writer - Interrupt flag for match channel 3."] +pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR0INT` reader - Interrupt flag for capture channel 0 event."] +pub type Cr0intR = crate::BitReader; +#[doc = "Field `CR0INT` writer - Interrupt flag for capture channel 0 event."] +pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR1INT` reader - Interrupt flag for capture channel 1 event."] +pub type Cr1intR = crate::BitReader; +#[doc = "Field `CR1INT` writer - Interrupt flag for capture channel 1 event."] +pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Interrupt flag for match channel 0."] + #[inline(always)] + pub fn mr0int(&self) -> Mr0intR { + Mr0intR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt flag for match channel 1."] + #[inline(always)] + pub fn mr1int(&self) -> Mr1intR { + Mr1intR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt flag for match channel 2."] + #[inline(always)] + pub fn mr2int(&self) -> Mr2intR { + Mr2intR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt flag for match channel 3."] + #[inline(always)] + pub fn mr3int(&self) -> Mr3intR { + Mr3intR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."] + #[inline(always)] + pub fn cr0int(&self) -> Cr0intR { + Cr0intR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."] + #[inline(always)] + pub fn cr1int(&self) -> Cr1intR { + Cr1intR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt flag for match channel 0."] + #[inline(always)] + #[must_use] + pub fn mr0int(&mut self) -> Mr0intW { + Mr0intW::new(self, 0) + } + #[doc = "Bit 1 - Interrupt flag for match channel 1."] + #[inline(always)] + #[must_use] + pub fn mr1int(&mut self) -> Mr1intW { + Mr1intW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt flag for match channel 2."] + #[inline(always)] + #[must_use] + pub fn mr2int(&mut self) -> Mr2intW { + Mr2intW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt flag for match channel 3."] + #[inline(always)] + #[must_use] + pub fn mr3int(&mut self) -> Mr3intW { + Mr3intW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."] + #[inline(always)] + #[must_use] + pub fn cr0int(&mut self) -> Cr0intW { + Cr0intW::new(self, 4) + } + #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."] + #[inline(always)] + #[must_use] + pub fn cr1int(&mut self) -> Cr1intW { + Cr1intW::new(self, 5) + } +} +#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrSpec; +impl crate::RegisterSpec for IrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ir::R`](R) reader structure"] +impl crate::Readable for IrSpec {} +#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"] +impl crate::Writable for IrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs new file mode 100644 index 0000000..89ad4d2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs @@ -0,0 +1,813 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0I` reader - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] +pub type Mr0iR = crate::BitReader; +impl Mr0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0i { + match self.bits { + true => Mr0i::Enabled, + false => Mr0i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0i::Disabled + } +} +#[doc = "Field `MR0I` writer - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] +pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>; +impl<'a, REG> Mr0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0i::Disabled) + } +} +#[doc = "Reset on MR0: the TC will be reset if MR0 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0R` reader - Reset on MR0: the TC will be reset if MR0 matches it."] +pub type Mr0rR = crate::BitReader; +impl Mr0rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0r { + match self.bits { + true => Mr0r::Enabled, + false => Mr0r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0r::Disabled + } +} +#[doc = "Field `MR0R` writer - Reset on MR0: the TC will be reset if MR0 matches it."] +pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>; +impl<'a, REG> Mr0rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0r::Disabled) + } +} +#[doc = "Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0S` reader - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] +pub type Mr0sR = crate::BitReader; +impl Mr0sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0s { + match self.bits { + true => Mr0s::Enabled, + false => Mr0s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0s::Disabled + } +} +#[doc = "Field `MR0S` writer - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] +pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>; +impl<'a, REG> Mr0sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0s::Disabled) + } +} +#[doc = "Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1I` reader - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] +pub type Mr1iR = crate::BitReader; +impl Mr1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1i { + match self.bits { + true => Mr1i::Enabled, + false => Mr1i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1i::Disabled + } +} +#[doc = "Field `MR1I` writer - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] +pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>; +impl<'a, REG> Mr1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1i::Disabled) + } +} +#[doc = "Reset on MR1: the TC will be reset if MR1 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1R` reader - Reset on MR1: the TC will be reset if MR1 matches it."] +pub type Mr1rR = crate::BitReader; +impl Mr1rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1r { + match self.bits { + true => Mr1r::Enabled, + false => Mr1r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1r::Disabled + } +} +#[doc = "Field `MR1R` writer - Reset on MR1: the TC will be reset if MR1 matches it."] +pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>; +impl<'a, REG> Mr1rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1r::Disabled) + } +} +#[doc = "Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1S` reader - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] +pub type Mr1sR = crate::BitReader; +impl Mr1sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1s { + match self.bits { + true => Mr1s::Enabled, + false => Mr1s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1s::Disabled + } +} +#[doc = "Field `MR1S` writer - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] +pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>; +impl<'a, REG> Mr1sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1s::Disabled) + } +} +#[doc = "Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2I` reader - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] +pub type Mr2iR = crate::BitReader; +impl Mr2iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2i { + match self.bits { + true => Mr2i::Enabled, + false => Mr2i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2i::Disabled + } +} +#[doc = "Field `MR2I` writer - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] +pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>; +impl<'a, REG> Mr2iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2i::Disabled) + } +} +#[doc = "Reset on MR2: the TC will be reset if MR2 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2R` reader - Reset on MR2: the TC will be reset if MR2 matches it."] +pub type Mr2rR = crate::BitReader; +impl Mr2rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2r { + match self.bits { + true => Mr2r::Enabled, + false => Mr2r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2r::Disabled + } +} +#[doc = "Field `MR2R` writer - Reset on MR2: the TC will be reset if MR2 matches it."] +pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>; +impl<'a, REG> Mr2rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2r::Disabled) + } +} +#[doc = "Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2S` reader - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] +pub type Mr2sR = crate::BitReader; +impl Mr2sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2s { + match self.bits { + true => Mr2s::Enabled, + false => Mr2s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2s::Disabled + } +} +#[doc = "Field `MR2S` writer - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] +pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>; +impl<'a, REG> Mr2sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2s::Disabled) + } +} +#[doc = "Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3I` reader - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] +pub type Mr3iR = crate::BitReader; +impl Mr3iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3i { + match self.bits { + true => Mr3i::Enabled, + false => Mr3i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3i::Disabled + } +} +#[doc = "Field `MR3I` writer - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] +pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>; +impl<'a, REG> Mr3iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3i::Disabled) + } +} +#[doc = "Reset on MR3: the TC will be reset if MR3 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3R` reader - Reset on MR3: the TC will be reset if MR3 matches it."] +pub type Mr3rR = crate::BitReader; +impl Mr3rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3r { + match self.bits { + true => Mr3r::Enabled, + false => Mr3r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3r::Disabled + } +} +#[doc = "Field `MR3R` writer - Reset on MR3: the TC will be reset if MR3 matches it."] +pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>; +impl<'a, REG> Mr3rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3r::Disabled) + } +} +#[doc = "Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3S` reader - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] +pub type Mr3sR = crate::BitReader; +impl Mr3sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3s { + match self.bits { + true => Mr3s::Enabled, + false => Mr3s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3s::Disabled + } +} +#[doc = "Field `MR3S` writer - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] +pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>; +impl<'a, REG> Mr3sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3s::Disabled) + } +} +impl R { + #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] + #[inline(always)] + pub fn mr0i(&self) -> Mr0iR { + Mr0iR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."] + #[inline(always)] + pub fn mr0r(&self) -> Mr0rR { + Mr0rR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] + #[inline(always)] + pub fn mr0s(&self) -> Mr0sR { + Mr0sR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] + #[inline(always)] + pub fn mr1i(&self) -> Mr1iR { + Mr1iR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."] + #[inline(always)] + pub fn mr1r(&self) -> Mr1rR { + Mr1rR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] + #[inline(always)] + pub fn mr1s(&self) -> Mr1sR { + Mr1sR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] + #[inline(always)] + pub fn mr2i(&self) -> Mr2iR { + Mr2iR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."] + #[inline(always)] + pub fn mr2r(&self) -> Mr2rR { + Mr2rR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] + #[inline(always)] + pub fn mr2s(&self) -> Mr2sR { + Mr2sR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] + #[inline(always)] + pub fn mr3i(&self) -> Mr3iR { + Mr3iR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."] + #[inline(always)] + pub fn mr3r(&self) -> Mr3rR { + Mr3rR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] + #[inline(always)] + pub fn mr3s(&self) -> Mr3sR { + Mr3sR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr0i(&mut self) -> Mr0iW { + Mr0iW::new(self, 0) + } + #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."] + #[inline(always)] + #[must_use] + pub fn mr0r(&mut self) -> Mr0rW { + Mr0rW::new(self, 1) + } + #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr0s(&mut self) -> Mr0sW { + Mr0sW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr1i(&mut self) -> Mr1iW { + Mr1iW::new(self, 3) + } + #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."] + #[inline(always)] + #[must_use] + pub fn mr1r(&mut self) -> Mr1rW { + Mr1rW::new(self, 4) + } + #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr1s(&mut self) -> Mr1sW { + Mr1sW::new(self, 5) + } + #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr2i(&mut self) -> Mr2iW { + Mr2iW::new(self, 6) + } + #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."] + #[inline(always)] + #[must_use] + pub fn mr2r(&mut self) -> Mr2rW { + Mr2rW::new(self, 7) + } + #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr2s(&mut self) -> Mr2sW { + Mr2sW::new(self, 8) + } + #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr3i(&mut self) -> Mr3iW { + Mr3iW::new(self, 9) + } + #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."] + #[inline(always)] + #[must_use] + pub fn mr3r(&mut self) -> Mr3rW { + Mr3rW::new(self, 10) + } + #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr3s(&mut self) -> Mr3sW { + Mr3sW::new(self, 11) + } +} +#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for McrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs new file mode 100644 index 0000000..29b4f01 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MR%s` reader"] +pub type R = crate::R; +#[doc = "Register `MR%s` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Timer counter match value."] +pub type MatchR = crate::FieldReader; +#[doc = "Field `MATCH` writer - Timer counter match value."] +pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timer counter match value."] + #[inline(always)] + pub fn match_(&self) -> MatchR { + MatchR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timer counter match value."] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MatchW { + MatchW::new(self, 0) + } +} +#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrSpec; +impl crate::RegisterSpec for MrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MrSpec {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] +impl crate::Writable for MrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MR%s to value 0"] +impl crate::Resettable for MrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs b/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs new file mode 100644 index 0000000..e1664ca --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PC` reader"] +pub type R = crate::R; +#[doc = "Register `PC` writer"] +pub type W = crate::W; +#[doc = "Field `PC` reader - Prescale counter value."] +pub type PcR = crate::FieldReader; +#[doc = "Field `PC` writer - Prescale counter value."] +pub type PcW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Prescale counter value."] + #[inline(always)] + pub fn pc(&self) -> PcR { + PcR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Prescale counter value."] + #[inline(always)] + #[must_use] + pub fn pc(&mut self) -> PcW { + PcW::new(self, 0) + } +} +#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcSpec; +impl crate::RegisterSpec for PcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pc::R`](R) reader structure"] +impl crate::Readable for PcSpec {} +#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"] +impl crate::Writable for PcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PC to value 0"] +impl crate::Resettable for PcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs new file mode 100644 index 0000000..6b0f858 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PR` reader"] +pub type R = crate::R; +#[doc = "Register `PR` writer"] +pub type W = crate::W; +#[doc = "Field `PR` reader - Prescale max value."] +pub type PrR = crate::FieldReader; +#[doc = "Field `PR` writer - Prescale max value."] +pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Prescale max value."] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Prescale max value."] + #[inline(always)] + #[must_use] + pub fn pr(&mut self) -> PrW { + PrW::new(self, 0) + } +} +#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrSpec; +impl crate::RegisterSpec for PrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pr::R`](R) reader structure"] +impl crate::Readable for PrSpec {} +#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"] +impl crate::Writable for PrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PR to value 0"] +impl crate::Resettable for PrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs b/rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs new file mode 100644 index 0000000..f1bd692 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/pwmc.rs @@ -0,0 +1,281 @@ +#[doc = "Register `PWMC` reader"] +pub type R = crate::R; +#[doc = "Register `PWMC` writer"] +pub type W = crate::W; +#[doc = "PWM channel0 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen0 { + #[doc = "0: CT16Bn_MAT0 is controlled by EM0."] + Ct16bnMat0IsContr = 0, + #[doc = "1: PWM mode is enabled for CT16Bn_MAT0."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN0` reader - PWM channel0 enable"] +pub type Pwmen0R = crate::BitReader; +impl Pwmen0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen0 { + match self.bits { + false => Pwmen0::Ct16bnMat0IsContr, + true => Pwmen0::PwmModeIsEnabled_, + } + } + #[doc = "CT16Bn_MAT0 is controlled by EM0."] + #[inline(always)] + pub fn is_ct16bn_mat0_is_contr(&self) -> bool { + *self == Pwmen0::Ct16bnMat0IsContr + } + #[doc = "PWM mode is enabled for CT16Bn_MAT0."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen0::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN0` writer - PWM channel0 enable"] +pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>; +impl<'a, REG> Pwmen0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT16Bn_MAT0 is controlled by EM0."] + #[inline(always)] + pub fn ct16bn_mat0_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen0::Ct16bnMat0IsContr) + } + #[doc = "PWM mode is enabled for CT16Bn_MAT0."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen0::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel1 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen1 { + #[doc = "0: CT16Bn_MAT1 is controlled by EM1."] + Ct16bnMat1IsContr = 0, + #[doc = "1: PWM mode is enabled for CT16Bn_MAT1."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN1` reader - PWM channel1 enable"] +pub type Pwmen1R = crate::BitReader; +impl Pwmen1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen1 { + match self.bits { + false => Pwmen1::Ct16bnMat1IsContr, + true => Pwmen1::PwmModeIsEnabled_, + } + } + #[doc = "CT16Bn_MAT1 is controlled by EM1."] + #[inline(always)] + pub fn is_ct16bn_mat1_is_contr(&self) -> bool { + *self == Pwmen1::Ct16bnMat1IsContr + } + #[doc = "PWM mode is enabled for CT16Bn_MAT1."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen1::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN1` writer - PWM channel1 enable"] +pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>; +impl<'a, REG> Pwmen1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT16Bn_MAT1 is controlled by EM1."] + #[inline(always)] + pub fn ct16bn_mat1_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen1::Ct16bnMat1IsContr) + } + #[doc = "PWM mode is enabled for CT16Bn_MAT1."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen1::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel2 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen2 { + #[doc = "0: Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."] + MatchChannel2OrP = 0, + #[doc = "1: PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN2` reader - PWM channel2 enable"] +pub type Pwmen2R = crate::BitReader; +impl Pwmen2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen2 { + match self.bits { + false => Pwmen2::MatchChannel2OrP, + true => Pwmen2::PwmModeIsEnabled_, + } + } + #[doc = "Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."] + #[inline(always)] + pub fn is_match_channel_2_or_p(&self) -> bool { + *self == Pwmen2::MatchChannel2OrP + } + #[doc = "PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen2::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN2` writer - PWM channel2 enable"] +pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>; +impl<'a, REG> Pwmen2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1."] + #[inline(always)] + pub fn match_channel_2_or_p(self) -> &'a mut crate::W { + self.variant(Pwmen2::MatchChannel2OrP) + } + #[doc = "PWM mode is enabled for match channel 2 or pin CT16B0_MAT2."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen2::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen3 { + #[doc = "0: Match channel 3 match channel 3 is controlled by EM3."] + MatchChannel3Matc = 0, + #[doc = "1: PWM mode is enabled for match channel 3match channel 3."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN3` reader - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."] +pub type Pwmen3R = crate::BitReader; +impl Pwmen3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen3 { + match self.bits { + false => Pwmen3::MatchChannel3Matc, + true => Pwmen3::PwmModeIsEnabled_, + } + } + #[doc = "Match channel 3 match channel 3 is controlled by EM3."] + #[inline(always)] + pub fn is_match_channel_3_matc(&self) -> bool { + *self == Pwmen3::MatchChannel3Matc + } + #[doc = "PWM mode is enabled for match channel 3match channel 3."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen3::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN3` writer - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."] +pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>; +impl<'a, REG> Pwmen3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Match channel 3 match channel 3 is controlled by EM3."] + #[inline(always)] + pub fn match_channel_3_matc(self) -> &'a mut crate::W { + self.variant(Pwmen3::MatchChannel3Matc) + } + #[doc = "PWM mode is enabled for match channel 3match channel 3."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen3::PwmModeIsEnabled_) + } +} +impl R { + #[doc = "Bit 0 - PWM channel0 enable"] + #[inline(always)] + pub fn pwmen0(&self) -> Pwmen0R { + Pwmen0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM channel1 enable"] + #[inline(always)] + pub fn pwmen1(&self) -> Pwmen1R { + Pwmen1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - PWM channel2 enable"] + #[inline(always)] + pub fn pwmen2(&self) -> Pwmen2R { + Pwmen2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."] + #[inline(always)] + pub fn pwmen3(&self) -> Pwmen3R { + Pwmen3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PWM channel0 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen0(&mut self) -> Pwmen0W { + Pwmen0W::new(self, 0) + } + #[doc = "Bit 1 - PWM channel1 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen1(&mut self) -> Pwmen1W { + Pwmen1W::new(self, 1) + } + #[doc = "Bit 2 - PWM channel2 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen2(&mut self) -> Pwmen2W { + Pwmen2W::new(self, 2) + } + #[doc = "Bit 3 - PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out."] + #[inline(always)] + #[must_use] + pub fn pwmen3(&mut self) -> Pwmen3W { + Pwmen3W::new(self, 3) + } +} +#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmcSpec; +impl crate::RegisterSpec for PwmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"] +impl crate::Readable for PwmcSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"] +impl crate::Writable for PwmcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWMC to value 0"] +impl crate::Resettable for PwmcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/tc.rs b/rust-embedded/lpc111x-pac/src/ct16b0/tc.rs new file mode 100644 index 0000000..80455d4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/tc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `TC` reader - Timer counter value."] +pub type TcR = crate::FieldReader; +#[doc = "Field `TC` writer - Timer counter value."] +pub type TcW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timer counter value."] + #[inline(always)] + pub fn tc(&self) -> TcR { + TcR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timer counter value."] + #[inline(always)] + #[must_use] + pub fn tc(&mut self) -> TcW { + TcW::new(self, 0) + } +} +#[doc = "Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs new file mode 100644 index 0000000..23d06a7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct16b0/tcr.rs @@ -0,0 +1,59 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CEN` reader - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] +pub type CenR = crate::BitReader; +#[doc = "Field `CEN` writer - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] +pub type CenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRST` reader - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] +pub type CrstR = crate::BitReader; +#[doc = "Field `CRST` writer - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] +pub type CrstW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] + #[inline(always)] + pub fn cen(&self) -> CenR { + CenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] + #[inline(always)] + pub fn crst(&self) -> CrstR { + CrstR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] + #[inline(always)] + #[must_use] + pub fn cen(&mut self) -> CenW { + CenW::new(self, 0) + } + #[doc = "Bit 1 - Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] + #[inline(always)] + #[must_use] + pub fn crst(&mut self) -> CrstW { + CrstW::new(self, 1) + } +} +#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TCR to value 0"] +impl crate::Resettable for TcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0.rs b/rust-embedded/lpc111x-pac/src/ct32b0.rs new file mode 100644 index 0000000..1073ec7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0.rs @@ -0,0 +1,164 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ir: Ir, + tcr: Tcr, + tc: Tc, + pr: Pr, + pc: Pc, + mcr: Mcr, + mr: [Mr; 4], + ccr: Ccr, + cr: [Cr; 2], + _reserved9: [u8; 0x08], + emr: Emr, + _reserved10: [u8; 0x30], + ctcr: Ctcr, + pwmc: Pwmc, +} +impl RegisterBlock { + #[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."] + #[inline(always)] + pub const fn ir(&self) -> &Ir { + &self.ir + } + #[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."] + #[inline(always)] + pub const fn tcr(&self) -> &Tcr { + &self.tcr + } + #[doc = "0x08 - Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."] + #[inline(always)] + pub const fn pr(&self) -> &Pr { + &self.pr + } + #[doc = "0x10 - Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."] + #[inline(always)] + pub const fn pc(&self) -> &Pc { + &self.pc + } + #[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] + #[inline(always)] + pub const fn mr(&self, n: usize) -> &Mr { + &self.mr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] + #[inline(always)] + pub fn mr_iter(&self) -> impl Iterator { + self.mr.iter() + } + #[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."] + #[inline(always)] + pub const fn ccr(&self) -> &Ccr { + &self.ccr + } + #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] + #[inline(always)] + pub const fn cr(&self, n: usize) -> &Cr { + &self.cr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] + #[inline(always)] + pub fn cr_iter(&self) -> impl Iterator { + self.cr.iter() + } + #[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."] + #[inline(always)] + pub const fn emr(&self) -> &Emr { + &self.emr + } + #[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."] + #[inline(always)] + pub const fn ctcr(&self) -> &Ctcr { + &self.ctcr + } + #[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."] + #[inline(always)] + pub const fn pwmc(&self) -> &Pwmc { + &self.pwmc + } +} +#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`] +module"] +#[doc(alias = "IR")] +pub type Ir = crate::Reg; +#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."] +pub mod ir; +#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`] +module"] +#[doc(alias = "TCR")] +pub type Tcr = crate::Reg; +#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."] +pub mod tcr; +#[doc = "TC (rw) register accessor: Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] +module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."] +pub mod tc; +#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`] +module"] +#[doc(alias = "PR")] +pub type Pr = crate::Reg; +#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."] +pub mod pr; +#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`] +module"] +#[doc(alias = "PC")] +pub type Pc = crate::Reg; +#[doc = "Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."] +pub mod pc; +#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."] +pub mod mcr; +#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`] +module"] +#[doc(alias = "MR")] +pub type Mr = crate::Reg; +#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."] +pub mod mr; +#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`] +module"] +#[doc(alias = "CCR")] +pub type Ccr = crate::Reg; +#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."] +pub mod ccr; +#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`] +module"] +#[doc(alias = "CR")] +pub type Cr = crate::Reg; +#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."] +pub mod cr; +#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`] +module"] +#[doc(alias = "EMR")] +pub type Emr = crate::Reg; +#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."] +pub mod emr; +#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`] +module"] +#[doc(alias = "CTCR")] +pub type Ctcr = crate::Reg; +#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."] +pub mod ctcr; +#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`] +module"] +#[doc(alias = "PWMC")] +pub type Pwmc = crate::Reg; +#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."] +pub mod pwmc; diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs new file mode 100644 index 0000000..c881a5c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/ccr.rs @@ -0,0 +1,409 @@ +#[doc = "Register `CCR` reader"] +pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; +#[doc = "Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0re { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0RE` reader - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0reR = crate::BitReader; +impl Cap0reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0re { + match self.bits { + true => Cap0re::Enabled, + false => Cap0re::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0re::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0re::Disabled + } +} +#[doc = "Field `CAP0RE` writer - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>; +impl<'a, REG> Cap0reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0re::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0re::Disabled) + } +} +#[doc = "Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0fe { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0FE` reader - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0feR = crate::BitReader; +impl Cap0feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0fe { + match self.bits { + true => Cap0fe::Enabled, + false => Cap0fe::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0fe::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0fe::Disabled + } +} +#[doc = "Field `CAP0FE` writer - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] +pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>; +impl<'a, REG> Cap0feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0fe::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0fe::Disabled) + } +} +#[doc = "Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap0i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP0I` reader - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."] +pub type Cap0iR = crate::BitReader; +impl Cap0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap0i { + match self.bits { + true => Cap0i::Enabled, + false => Cap0i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap0i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap0i::Disabled + } +} +#[doc = "Field `CAP0I` writer - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."] +pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>; +impl<'a, REG> Cap0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap0i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap0i::Disabled) + } +} +#[doc = "Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1re { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1re) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1RE` reader - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1reR = crate::BitReader; +impl Cap1reR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1re { + match self.bits { + true => Cap1re::Enabled, + false => Cap1re::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1re::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1re::Disabled + } +} +#[doc = "Field `CAP1RE` writer - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>; +impl<'a, REG> Cap1reW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1re::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1re::Disabled) + } +} +#[doc = "Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1fe { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1FE` reader - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1feR = crate::BitReader; +impl Cap1feR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1fe { + match self.bits { + true => Cap1fe::Enabled, + false => Cap1fe::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1fe::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1fe::Disabled + } +} +#[doc = "Field `CAP1FE` writer - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] +pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>; +impl<'a, REG> Cap1feW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1fe::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1fe::Disabled) + } +} +#[doc = "Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cap1i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cap1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAP1I` reader - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."] +pub type Cap1iR = crate::BitReader; +impl Cap1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cap1i { + match self.bits { + true => Cap1i::Enabled, + false => Cap1i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Cap1i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Cap1i::Disabled + } +} +#[doc = "Field `CAP1I` writer - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."] +pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>; +impl<'a, REG> Cap1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Cap1i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Cap1i::Disabled) + } +} +impl R { + #[doc = "Bit 0 - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap0re(&self) -> Cap0reR { + Cap0reR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap0fe(&self) -> Cap0feR { + Cap0feR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."] + #[inline(always)] + pub fn cap0i(&self) -> Cap0iR { + Cap0iR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap1re(&self) -> Cap1reR { + Cap1reR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + pub fn cap1fe(&self) -> Cap1feR { + Cap1feR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."] + #[inline(always)] + pub fn cap1i(&self) -> Cap1iR { + Cap1iR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap0re(&mut self) -> Cap0reW { + Cap0reW::new(self, 0) + } + #[doc = "Bit 1 - Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap0fe(&mut self) -> Cap0feW { + Cap0feW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt."] + #[inline(always)] + #[must_use] + pub fn cap0i(&mut self) -> Cap0iW { + Cap0iW::new(self, 2) + } + #[doc = "Bit 3 - Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap1re(&mut self) -> Cap1reW { + Cap1reW::new(self, 3) + } + #[doc = "Bit 4 - Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC."] + #[inline(always)] + #[must_use] + pub fn cap1fe(&mut self) -> Cap1feW { + Cap1feW::new(self, 4) + } + #[doc = "Bit 5 - Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt."] + #[inline(always)] + #[must_use] + pub fn cap1i(&mut self) -> Cap1iW { + Cap1iW::new(self, 5) + } +} +#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CcrSpec; +impl crate::RegisterSpec for CcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CCR to value 0"] +impl crate::Resettable for CcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/cr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/cr.rs new file mode 100644 index 0000000..d8cafa0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/cr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `CR%s` reader"] +pub type R = crate::R; +#[doc = "Field `CAP` reader - Timer counter capture value."] +pub type CapR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Timer counter capture value."] + #[inline(always)] + pub fn cap(&self) -> CapR { + CapR::new(self.bits) + } +} +#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CrSpec; +impl crate::RegisterSpec for CrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CrSpec {} +#[doc = "`reset()` method sets CR%s to value 0"] +impl crate::Resettable for CrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs new file mode 100644 index 0000000..d4983d6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/ctcr.rs @@ -0,0 +1,315 @@ +#[doc = "Register `CTCR` reader"] +pub type R = crate::R; +#[doc = "Register `CTCR` writer"] +pub type W = crate::W; +#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ctm { + #[doc = "0: Increment on every rising PCLK edge"] + Timer = 0, + #[doc = "1: Increment on rising CAP pin edge"] + CounterRising = 1, + #[doc = "2: Increment on falling CAP pin edge"] + CounterFalling = 2, + #[doc = "3: Increment on both CAP pin edges"] + CounterBoth = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ctm) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ctm { + type Ux = u8; +} +#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"] +pub type CtmR = crate::FieldReader; +impl CtmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctm { + match self.bits { + 0 => Ctm::Timer, + 1 => Ctm::CounterRising, + 2 => Ctm::CounterFalling, + 3 => Ctm::CounterBoth, + _ => unreachable!(), + } + } + #[doc = "Increment on every rising PCLK edge"] + #[inline(always)] + pub fn is_timer(&self) -> bool { + *self == Ctm::Timer + } + #[doc = "Increment on rising CAP pin edge"] + #[inline(always)] + pub fn is_counter_rising(&self) -> bool { + *self == Ctm::CounterRising + } + #[doc = "Increment on falling CAP pin edge"] + #[inline(always)] + pub fn is_counter_falling(&self) -> bool { + *self == Ctm::CounterFalling + } + #[doc = "Increment on both CAP pin edges"] + #[inline(always)] + pub fn is_counter_both(&self) -> bool { + *self == Ctm::CounterBoth + } +} +#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"] +pub type CtmW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctm>; +impl<'a, REG> CtmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Increment on every rising PCLK edge"] + #[inline(always)] + pub fn timer(self) -> &'a mut crate::W { + self.variant(Ctm::Timer) + } + #[doc = "Increment on rising CAP pin edge"] + #[inline(always)] + pub fn counter_rising(self) -> &'a mut crate::W { + self.variant(Ctm::CounterRising) + } + #[doc = "Increment on falling CAP pin edge"] + #[inline(always)] + pub fn counter_falling(self) -> &'a mut crate::W { + self.variant(Ctm::CounterFalling) + } + #[doc = "Increment on both CAP pin edges"] + #[inline(always)] + pub fn counter_both(self) -> &'a mut crate::W { + self.variant(Ctm::CounterBoth) + } +} +#[doc = "Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Cis { + #[doc = "0: CT32Bn_CAP0"] + Ct32bnCap0 = 0, + #[doc = "1: CT32Bn_CAP1"] + Ct32bnCap1 = 1, + #[doc = "3: Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."] + ReservedNoteIfCo = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Cis) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Cis { + type Ux = u8; +} +#[doc = "Field `CIS` reader - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"] +pub type CisR = crate::FieldReader; +impl CisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cis { + match self.bits { + 0 => Cis::Ct32bnCap0, + 1 => Cis::Ct32bnCap1, + 3 => Cis::ReservedNoteIfCo, + _ => unreachable!(), + } + } + #[doc = "CT32Bn_CAP0"] + #[inline(always)] + pub fn is_ct32bn_cap0(&self) -> bool { + *self == Cis::Ct32bnCap0 + } + #[doc = "CT32Bn_CAP1"] + #[inline(always)] + pub fn is_ct32bn_cap1(&self) -> bool { + *self == Cis::Ct32bnCap1 + } + #[doc = "Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."] + #[inline(always)] + pub fn is_reserved_note_if_co(&self) -> bool { + *self == Cis::ReservedNoteIfCo + } +} +#[doc = "Field `CIS` writer - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"] +pub type CisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cis>; +impl<'a, REG> CisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "CT32Bn_CAP0"] + #[inline(always)] + pub fn ct32bn_cap0(self) -> &'a mut crate::W { + self.variant(Cis::Ct32bnCap0) + } + #[doc = "CT32Bn_CAP1"] + #[inline(always)] + pub fn ct32bn_cap1(self) -> &'a mut crate::W { + self.variant(Cis::Ct32bnCap1) + } + #[doc = "Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000."] + #[inline(always)] + pub fn reserved_note_if_co(self) -> &'a mut crate::W { + self.variant(Cis::ReservedNoteIfCo) + } +} +#[doc = "Field `ENCC` reader - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] +pub type EnccR = crate::BitReader; +#[doc = "Field `ENCC` writer - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] +pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Selcc { + #[doc = "0: Rising Edge of CAP0 clears the timer"] + Cap0Rising = 0, + #[doc = "1: Falling Edge of CAP0 clears the timer"] + Cap0Falling = 1, + #[doc = "2: Rising Edge of CAP1 clears the timer"] + Cap1Rising = 2, + #[doc = "3: Falling Edge of CAP1 clears the timer"] + Cap1Falling = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Selcc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Selcc { + type Ux = u8; +} +#[doc = "Field `SELCC` reader - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] +pub type SelccR = crate::FieldReader; +impl SelccR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Selcc::Cap0Rising), + 1 => Some(Selcc::Cap0Falling), + 2 => Some(Selcc::Cap1Rising), + 3 => Some(Selcc::Cap1Falling), + _ => None, + } + } + #[doc = "Rising Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn is_cap0_rising(&self) -> bool { + *self == Selcc::Cap0Rising + } + #[doc = "Falling Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn is_cap0_falling(&self) -> bool { + *self == Selcc::Cap0Falling + } + #[doc = "Rising Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn is_cap1_rising(&self) -> bool { + *self == Selcc::Cap1Rising + } + #[doc = "Falling Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn is_cap1_falling(&self) -> bool { + *self == Selcc::Cap1Falling + } +} +#[doc = "Field `SELCC` writer - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] +pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc>; +impl<'a, REG> SelccW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Rising Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn cap0_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Cap0Rising) + } + #[doc = "Falling Edge of CAP0 clears the timer"] + #[inline(always)] + pub fn cap0_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Cap0Falling) + } + #[doc = "Rising Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn cap1_rising(self) -> &'a mut crate::W { + self.variant(Selcc::Cap1Rising) + } + #[doc = "Falling Edge of CAP1 clears the timer"] + #[inline(always)] + pub fn cap1_falling(self) -> &'a mut crate::W { + self.variant(Selcc::Cap1Falling) + } +} +impl R { + #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"] + #[inline(always)] + pub fn ctm(&self) -> CtmR { + CtmR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"] + #[inline(always)] + pub fn cis(&self) -> CisR { + CisR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] + #[inline(always)] + pub fn encc(&self) -> EnccR { + EnccR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] + #[inline(always)] + pub fn selcc(&self) -> SelccR { + SelccR::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge"] + #[inline(always)] + #[must_use] + pub fn ctm(&mut self) -> CtmW { + CtmW::new(self, 0) + } + #[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:"] + #[inline(always)] + #[must_use] + pub fn cis(&mut self) -> CisW { + CisW::new(self, 2) + } + #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."] + #[inline(always)] + #[must_use] + pub fn encc(&mut self) -> EnccW { + EnccW::new(self, 4) + } + #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."] + #[inline(always)] + #[must_use] + pub fn selcc(&mut self) -> SelccW { + SelccW::new(self, 5) + } +} +#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtcrSpec; +impl crate::RegisterSpec for CtcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"] +impl crate::Readable for CtcrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"] +impl crate::Writable for CtcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTCR to value 0"] +impl crate::Resettable for CtcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/emr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/emr.rs new file mode 100644 index 0000000..de87ed9 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/emr.rs @@ -0,0 +1,485 @@ +#[doc = "Register `EMR` reader"] +pub type R = crate::R; +#[doc = "Register `EMR` writer"] +pub type W = crate::W; +#[doc = "Field `EM0` reader - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em0R = crate::BitReader; +#[doc = "Field `EM0` writer - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM1` reader - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em1R = crate::BitReader; +#[doc = "Field `EM1` writer - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM2` reader - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em2R = crate::BitReader; +#[doc = "Field `EM2` writer - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EM3` reader - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em3R = crate::BitReader; +#[doc = "Field `EM3` writer - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] +pub type Em3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "External Match Control 0. Determines the functionality of External Match 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc0 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc0) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc0 { + type Ux = u8; +} +#[doc = "Field `EMC0` reader - External Match Control 0. Determines the functionality of External Match 0."] +pub type Emc0R = crate::FieldReader; +impl Emc0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc0 { + match self.bits { + 0 => Emc0::DoNothing_, + 1 => Emc0::ClearTheCorrespond, + 2 => Emc0::SetTheCorrespondin, + 3 => Emc0::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc0::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc0::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc0::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc0::ToggleTheCorrespon + } +} +#[doc = "Field `EMC0` writer - External Match Control 0. Determines the functionality of External Match 0."] +pub type Emc0W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc0>; +impl<'a, REG> Emc0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc0::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc0::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc0::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc0::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 1. Determines the functionality of External Match 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc1 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc1) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc1 { + type Ux = u8; +} +#[doc = "Field `EMC1` reader - External Match Control 1. Determines the functionality of External Match 1."] +pub type Emc1R = crate::FieldReader; +impl Emc1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc1 { + match self.bits { + 0 => Emc1::DoNothing_, + 1 => Emc1::ClearTheCorrespond, + 2 => Emc1::SetTheCorrespondin, + 3 => Emc1::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc1::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc1::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc1::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc1::ToggleTheCorrespon + } +} +#[doc = "Field `EMC1` writer - External Match Control 1. Determines the functionality of External Match 1."] +pub type Emc1W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc1>; +impl<'a, REG> Emc1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc1::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc1::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc1::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc1::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 2. Determines the functionality of External Match 2.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc2 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc2) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc2 { + type Ux = u8; +} +#[doc = "Field `EMC2` reader - External Match Control 2. Determines the functionality of External Match 2."] +pub type Emc2R = crate::FieldReader; +impl Emc2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc2 { + match self.bits { + 0 => Emc2::DoNothing_, + 1 => Emc2::ClearTheCorrespond, + 2 => Emc2::SetTheCorrespondin, + 3 => Emc2::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc2::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc2::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc2::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc2::ToggleTheCorrespon + } +} +#[doc = "Field `EMC2` writer - External Match Control 2. Determines the functionality of External Match 2."] +pub type Emc2W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc2>; +impl<'a, REG> Emc2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc2::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc2::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc2::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc2::ToggleTheCorrespon) + } +} +#[doc = "External Match Control 3. Determines the functionality of External Match 3.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Emc3 { + #[doc = "0: Do Nothing."] + DoNothing_ = 0, + #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + ClearTheCorrespond = 1, + #[doc = "2: Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + SetTheCorrespondin = 2, + #[doc = "3: Toggle the corresponding External Match bit/output."] + ToggleTheCorrespon = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Emc3) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Emc3 { + type Ux = u8; +} +#[doc = "Field `EMC3` reader - External Match Control 3. Determines the functionality of External Match 3."] +pub type Emc3R = crate::FieldReader; +impl Emc3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Emc3 { + match self.bits { + 0 => Emc3::DoNothing_, + 1 => Emc3::ClearTheCorrespond, + 2 => Emc3::SetTheCorrespondin, + 3 => Emc3::ToggleTheCorrespon, + _ => unreachable!(), + } + } + #[doc = "Do Nothing."] + #[inline(always)] + pub fn is_do_nothing_(&self) -> bool { + *self == Emc3::DoNothing_ + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn is_clear_the_correspond(&self) -> bool { + *self == Emc3::ClearTheCorrespond + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn is_set_the_correspondin(&self) -> bool { + *self == Emc3::SetTheCorrespondin + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn is_toggle_the_correspon(&self) -> bool { + *self == Emc3::ToggleTheCorrespon + } +} +#[doc = "Field `EMC3` writer - External Match Control 3. Determines the functionality of External Match 3."] +pub type Emc3W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc3>; +impl<'a, REG> Emc3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do Nothing."] + #[inline(always)] + pub fn do_nothing_(self) -> &'a mut crate::W { + self.variant(Emc3::DoNothing_) + } + #[doc = "Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out)."] + #[inline(always)] + pub fn clear_the_correspond(self) -> &'a mut crate::W { + self.variant(Emc3::ClearTheCorrespond) + } + #[doc = "Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out)."] + #[inline(always)] + pub fn set_the_correspondin(self) -> &'a mut crate::W { + self.variant(Emc3::SetTheCorrespondin) + } + #[doc = "Toggle the corresponding External Match bit/output."] + #[inline(always)] + pub fn toggle_the_correspon(self) -> &'a mut crate::W { + self.variant(Emc3::ToggleTheCorrespon) + } +} +impl R { + #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em0(&self) -> Em0R { + Em0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em1(&self) -> Em1R { + Em1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em2(&self) -> Em2R { + Em2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + pub fn em3(&self) -> Em3R { + Em3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."] + #[inline(always)] + pub fn emc0(&self) -> Emc0R { + Emc0R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."] + #[inline(always)] + pub fn emc1(&self) -> Emc1R { + Emc1R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."] + #[inline(always)] + pub fn emc2(&self) -> Emc2R { + Emc2R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."] + #[inline(always)] + pub fn emc3(&self) -> Emc3R { + Emc3R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em0(&mut self) -> Em0W { + Em0W::new(self, 0) + } + #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em1(&mut self) -> Em1W { + Em1W::new(self, 1) + } + #[doc = "Bit 2 - External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em2(&mut self) -> Em2W { + Em2W::new(self, 2) + } + #[doc = "Bit 3 - External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\] +control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."] + #[inline(always)] + #[must_use] + pub fn em3(&mut self) -> Em3W { + Em3W::new(self, 3) + } + #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."] + #[inline(always)] + #[must_use] + pub fn emc0(&mut self) -> Emc0W { + Emc0W::new(self, 4) + } + #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."] + #[inline(always)] + #[must_use] + pub fn emc1(&mut self) -> Emc1W { + Emc1W::new(self, 6) + } + #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."] + #[inline(always)] + #[must_use] + pub fn emc2(&mut self) -> Emc2W { + Emc2W::new(self, 8) + } + #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."] + #[inline(always)] + #[must_use] + pub fn emc3(&mut self) -> Emc3W { + Emc3W::new(self, 10) + } +} +#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EmrSpec; +impl crate::RegisterSpec for EmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`emr::R`](R) reader structure"] +impl crate::Readable for EmrSpec {} +#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] +impl crate::Writable for EmrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EMR to value 0"] +impl crate::Resettable for EmrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/ir.rs b/rust-embedded/lpc111x-pac/src/ct32b0/ir.rs new file mode 100644 index 0000000..ba6862b --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/ir.rs @@ -0,0 +1,115 @@ +#[doc = "Register `IR` reader"] +pub type R = crate::R; +#[doc = "Register `IR` writer"] +pub type W = crate::W; +#[doc = "Field `MR0INT` reader - Interrupt flag for match channel 0."] +pub type Mr0intR = crate::BitReader; +#[doc = "Field `MR0INT` writer - Interrupt flag for match channel 0."] +pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR1INT` reader - Interrupt flag for match channel 1."] +pub type Mr1intR = crate::BitReader; +#[doc = "Field `MR1INT` writer - Interrupt flag for match channel 1."] +pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR2INT` reader - Interrupt flag for match channel 2."] +pub type Mr2intR = crate::BitReader; +#[doc = "Field `MR2INT` writer - Interrupt flag for match channel 2."] +pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MR3INT` reader - Interrupt flag for match channel 3."] +pub type Mr3intR = crate::BitReader; +#[doc = "Field `MR3INT` writer - Interrupt flag for match channel 3."] +pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR0INT` reader - Interrupt flag for capture channel 0 event."] +pub type Cr0intR = crate::BitReader; +#[doc = "Field `CR0INT` writer - Interrupt flag for capture channel 0 event."] +pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR1INT` reader - Interrupt flag for capture channel 1 event."] +pub type Cr1intR = crate::BitReader; +#[doc = "Field `CR1INT` writer - Interrupt flag for capture channel 1 event."] +pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Interrupt flag for match channel 0."] + #[inline(always)] + pub fn mr0int(&self) -> Mr0intR { + Mr0intR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Interrupt flag for match channel 1."] + #[inline(always)] + pub fn mr1int(&self) -> Mr1intR { + Mr1intR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Interrupt flag for match channel 2."] + #[inline(always)] + pub fn mr2int(&self) -> Mr2intR { + Mr2intR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt flag for match channel 3."] + #[inline(always)] + pub fn mr3int(&self) -> Mr3intR { + Mr3intR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."] + #[inline(always)] + pub fn cr0int(&self) -> Cr0intR { + Cr0intR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."] + #[inline(always)] + pub fn cr1int(&self) -> Cr1intR { + Cr1intR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt flag for match channel 0."] + #[inline(always)] + #[must_use] + pub fn mr0int(&mut self) -> Mr0intW { + Mr0intW::new(self, 0) + } + #[doc = "Bit 1 - Interrupt flag for match channel 1."] + #[inline(always)] + #[must_use] + pub fn mr1int(&mut self) -> Mr1intW { + Mr1intW::new(self, 1) + } + #[doc = "Bit 2 - Interrupt flag for match channel 2."] + #[inline(always)] + #[must_use] + pub fn mr2int(&mut self) -> Mr2intW { + Mr2intW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt flag for match channel 3."] + #[inline(always)] + #[must_use] + pub fn mr3int(&mut self) -> Mr3intW { + Mr3intW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."] + #[inline(always)] + #[must_use] + pub fn cr0int(&mut self) -> Cr0intW { + Cr0intW::new(self, 4) + } + #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."] + #[inline(always)] + #[must_use] + pub fn cr1int(&mut self) -> Cr1intW { + Cr1intW::new(self, 5) + } +} +#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrSpec; +impl crate::RegisterSpec for IrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ir::R`](R) reader structure"] +impl crate::Readable for IrSpec {} +#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"] +impl crate::Writable for IrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IR to value 0"] +impl crate::Resettable for IrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs new file mode 100644 index 0000000..89ad4d2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/mcr.rs @@ -0,0 +1,813 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0I` reader - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] +pub type Mr0iR = crate::BitReader; +impl Mr0iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0i { + match self.bits { + true => Mr0i::Enabled, + false => Mr0i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0i::Disabled + } +} +#[doc = "Field `MR0I` writer - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] +pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>; +impl<'a, REG> Mr0iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0i::Disabled) + } +} +#[doc = "Reset on MR0: the TC will be reset if MR0 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0R` reader - Reset on MR0: the TC will be reset if MR0 matches it."] +pub type Mr0rR = crate::BitReader; +impl Mr0rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0r { + match self.bits { + true => Mr0r::Enabled, + false => Mr0r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0r::Disabled + } +} +#[doc = "Field `MR0R` writer - Reset on MR0: the TC will be reset if MR0 matches it."] +pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>; +impl<'a, REG> Mr0rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0r::Disabled) + } +} +#[doc = "Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr0s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr0s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR0S` reader - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] +pub type Mr0sR = crate::BitReader; +impl Mr0sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr0s { + match self.bits { + true => Mr0s::Enabled, + false => Mr0s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr0s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr0s::Disabled + } +} +#[doc = "Field `MR0S` writer - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] +pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>; +impl<'a, REG> Mr0sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr0s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr0s::Disabled) + } +} +#[doc = "Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1I` reader - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] +pub type Mr1iR = crate::BitReader; +impl Mr1iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1i { + match self.bits { + true => Mr1i::Enabled, + false => Mr1i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1i::Disabled + } +} +#[doc = "Field `MR1I` writer - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] +pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>; +impl<'a, REG> Mr1iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1i::Disabled) + } +} +#[doc = "Reset on MR1: the TC will be reset if MR1 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1R` reader - Reset on MR1: the TC will be reset if MR1 matches it."] +pub type Mr1rR = crate::BitReader; +impl Mr1rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1r { + match self.bits { + true => Mr1r::Enabled, + false => Mr1r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1r::Disabled + } +} +#[doc = "Field `MR1R` writer - Reset on MR1: the TC will be reset if MR1 matches it."] +pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>; +impl<'a, REG> Mr1rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1r::Disabled) + } +} +#[doc = "Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr1s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr1s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR1S` reader - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] +pub type Mr1sR = crate::BitReader; +impl Mr1sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr1s { + match self.bits { + true => Mr1s::Enabled, + false => Mr1s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr1s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr1s::Disabled + } +} +#[doc = "Field `MR1S` writer - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] +pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>; +impl<'a, REG> Mr1sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr1s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr1s::Disabled) + } +} +#[doc = "Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2I` reader - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] +pub type Mr2iR = crate::BitReader; +impl Mr2iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2i { + match self.bits { + true => Mr2i::Enabled, + false => Mr2i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2i::Disabled + } +} +#[doc = "Field `MR2I` writer - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] +pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>; +impl<'a, REG> Mr2iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2i::Disabled) + } +} +#[doc = "Reset on MR2: the TC will be reset if MR2 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2R` reader - Reset on MR2: the TC will be reset if MR2 matches it."] +pub type Mr2rR = crate::BitReader; +impl Mr2rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2r { + match self.bits { + true => Mr2r::Enabled, + false => Mr2r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2r::Disabled + } +} +#[doc = "Field `MR2R` writer - Reset on MR2: the TC will be reset if MR2 matches it."] +pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>; +impl<'a, REG> Mr2rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2r::Disabled) + } +} +#[doc = "Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr2s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr2s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR2S` reader - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] +pub type Mr2sR = crate::BitReader; +impl Mr2sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr2s { + match self.bits { + true => Mr2s::Enabled, + false => Mr2s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr2s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr2s::Disabled + } +} +#[doc = "Field `MR2S` writer - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] +pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>; +impl<'a, REG> Mr2sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr2s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr2s::Disabled) + } +} +#[doc = "Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3i { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3i) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3I` reader - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] +pub type Mr3iR = crate::BitReader; +impl Mr3iR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3i { + match self.bits { + true => Mr3i::Enabled, + false => Mr3i::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3i::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3i::Disabled + } +} +#[doc = "Field `MR3I` writer - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] +pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>; +impl<'a, REG> Mr3iW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3i::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3i::Disabled) + } +} +#[doc = "Reset on MR3: the TC will be reset if MR3 matches it.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3r { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3r) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3R` reader - Reset on MR3: the TC will be reset if MR3 matches it."] +pub type Mr3rR = crate::BitReader; +impl Mr3rR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3r { + match self.bits { + true => Mr3r::Enabled, + false => Mr3r::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3r::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3r::Disabled + } +} +#[doc = "Field `MR3R` writer - Reset on MR3: the TC will be reset if MR3 matches it."] +pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>; +impl<'a, REG> Mr3rW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3r::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3r::Disabled) + } +} +#[doc = "Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mr3s { + #[doc = "1: Enabled"] + Enabled = 1, + #[doc = "0: Disabled"] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mr3s) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MR3S` reader - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] +pub type Mr3sR = crate::BitReader; +impl Mr3sR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mr3s { + match self.bits { + true => Mr3s::Enabled, + false => Mr3s::Disabled, + } + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Mr3s::Enabled + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Mr3s::Disabled + } +} +#[doc = "Field `MR3S` writer - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] +pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>; +impl<'a, REG> Mr3sW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Mr3s::Enabled) + } + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Mr3s::Disabled) + } +} +impl R { + #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] + #[inline(always)] + pub fn mr0i(&self) -> Mr0iR { + Mr0iR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."] + #[inline(always)] + pub fn mr0r(&self) -> Mr0rR { + Mr0rR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] + #[inline(always)] + pub fn mr0s(&self) -> Mr0sR { + Mr0sR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] + #[inline(always)] + pub fn mr1i(&self) -> Mr1iR { + Mr1iR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."] + #[inline(always)] + pub fn mr1r(&self) -> Mr1rR { + Mr1rR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] + #[inline(always)] + pub fn mr1s(&self) -> Mr1sR { + Mr1sR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] + #[inline(always)] + pub fn mr2i(&self) -> Mr2iR { + Mr2iR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."] + #[inline(always)] + pub fn mr2r(&self) -> Mr2rR { + Mr2rR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] + #[inline(always)] + pub fn mr2s(&self) -> Mr2sR { + Mr2sR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] + #[inline(always)] + pub fn mr3i(&self) -> Mr3iR { + Mr3iR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."] + #[inline(always)] + pub fn mr3r(&self) -> Mr3rR { + Mr3rR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] + #[inline(always)] + pub fn mr3s(&self) -> Mr3sR { + Mr3sR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr0i(&mut self) -> Mr0iW { + Mr0iW::new(self, 0) + } + #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."] + #[inline(always)] + #[must_use] + pub fn mr0r(&mut self) -> Mr0rW { + Mr0rW::new(self, 1) + } + #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR0 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr0s(&mut self) -> Mr0sW { + Mr0sW::new(self, 2) + } + #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr1i(&mut self) -> Mr1iW { + Mr1iW::new(self, 3) + } + #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."] + #[inline(always)] + #[must_use] + pub fn mr1r(&mut self) -> Mr1rW { + Mr1rW::new(self, 4) + } + #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR1 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr1s(&mut self) -> Mr1sW { + Mr1sW::new(self, 5) + } + #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr2i(&mut self) -> Mr2iW { + Mr2iW::new(self, 6) + } + #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."] + #[inline(always)] + #[must_use] + pub fn mr2r(&mut self) -> Mr2rW { + Mr2rW::new(self, 7) + } + #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR2 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr2s(&mut self) -> Mr2sW { + Mr2sW::new(self, 8) + } + #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."] + #[inline(always)] + #[must_use] + pub fn mr3i(&mut self) -> Mr3iW { + Mr3iW::new(self, 9) + } + #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."] + #[inline(always)] + #[must_use] + pub fn mr3r(&mut self) -> Mr3rW { + Mr3rW::new(self, 10) + } + #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\] +will be set to 0 if MR3 matches the TC."] + #[inline(always)] + #[must_use] + pub fn mr3s(&mut self) -> Mr3sW { + Mr3sW::new(self, 11) + } +} +#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for McrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/mr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/mr.rs new file mode 100644 index 0000000..5d8426e --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/mr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MR%s` reader"] +pub type R = crate::R; +#[doc = "Register `MR%s` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Timer counter match value."] +pub type MatchR = crate::FieldReader; +#[doc = "Field `MATCH` writer - Timer counter match value."] +pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer counter match value."] + #[inline(always)] + pub fn match_(&self) -> MatchR { + MatchR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timer counter match value."] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MatchW { + MatchW::new(self, 0) + } +} +#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MrSpec; +impl crate::RegisterSpec for MrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MrSpec {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] +impl crate::Writable for MrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MR%s to value 0"] +impl crate::Resettable for MrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/pc.rs b/rust-embedded/lpc111x-pac/src/ct32b0/pc.rs new file mode 100644 index 0000000..5ae0812 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/pc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PC` reader"] +pub type R = crate::R; +#[doc = "Register `PC` writer"] +pub type W = crate::W; +#[doc = "Field `PC` reader - Prescale counter value."] +pub type PcR = crate::FieldReader; +#[doc = "Field `PC` writer - Prescale counter value."] +pub type PcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Prescale counter value."] + #[inline(always)] + pub fn pc(&self) -> PcR { + PcR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Prescale counter value."] + #[inline(always)] + #[must_use] + pub fn pc(&mut self) -> PcW { + PcW::new(self, 0) + } +} +#[doc = "Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PcSpec; +impl crate::RegisterSpec for PcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pc::R`](R) reader structure"] +impl crate::Readable for PcSpec {} +#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"] +impl crate::Writable for PcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PC to value 0"] +impl crate::Resettable for PcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/pr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/pr.rs new file mode 100644 index 0000000..26d87bb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/pr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PR` reader"] +pub type R = crate::R; +#[doc = "Register `PR` writer"] +pub type W = crate::W; +#[doc = "Field `PR` reader - Prescale value."] +pub type PrR = crate::FieldReader; +#[doc = "Field `PR` writer - Prescale value."] +pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Prescale value."] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Prescale value."] + #[inline(always)] + #[must_use] + pub fn pr(&mut self) -> PrW { + PrW::new(self, 0) + } +} +#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrSpec; +impl crate::RegisterSpec for PrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pr::R`](R) reader structure"] +impl crate::Readable for PrSpec {} +#[doc = "`write(|w| ..)` method takes [`pr::W`](W) writer structure"] +impl crate::Writable for PrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PR to value 0"] +impl crate::Resettable for PrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs b/rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs new file mode 100644 index 0000000..c603037 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/pwmc.rs @@ -0,0 +1,281 @@ +#[doc = "Register `PWMC` reader"] +pub type R = crate::R; +#[doc = "Register `PWMC` writer"] +pub type W = crate::W; +#[doc = "PWM channel 0 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen0 { + #[doc = "0: CT32Bn_MAT0 is controlled by EM0."] + Ct32bnMat0IsContr = 0, + #[doc = "1: PWM mode is enabled for CT32Bn_MAT0."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN0` reader - PWM channel 0 enable"] +pub type Pwmen0R = crate::BitReader; +impl Pwmen0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen0 { + match self.bits { + false => Pwmen0::Ct32bnMat0IsContr, + true => Pwmen0::PwmModeIsEnabled_, + } + } + #[doc = "CT32Bn_MAT0 is controlled by EM0."] + #[inline(always)] + pub fn is_ct32bn_mat0_is_contr(&self) -> bool { + *self == Pwmen0::Ct32bnMat0IsContr + } + #[doc = "PWM mode is enabled for CT32Bn_MAT0."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen0::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN0` writer - PWM channel 0 enable"] +pub type Pwmen0W<'a, REG> = crate::BitWriter<'a, REG, Pwmen0>; +impl<'a, REG> Pwmen0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT32Bn_MAT0 is controlled by EM0."] + #[inline(always)] + pub fn ct32bn_mat0_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen0::Ct32bnMat0IsContr) + } + #[doc = "PWM mode is enabled for CT32Bn_MAT0."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen0::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel 1 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen1 { + #[doc = "0: CT32Bn_MAT1 is controlled by EM1."] + Ct32bnMat1IsContr = 0, + #[doc = "1: PWM mode is enabled for CT32Bn_MAT1."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN1` reader - PWM channel 1 enable"] +pub type Pwmen1R = crate::BitReader; +impl Pwmen1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen1 { + match self.bits { + false => Pwmen1::Ct32bnMat1IsContr, + true => Pwmen1::PwmModeIsEnabled_, + } + } + #[doc = "CT32Bn_MAT1 is controlled by EM1."] + #[inline(always)] + pub fn is_ct32bn_mat1_is_contr(&self) -> bool { + *self == Pwmen1::Ct32bnMat1IsContr + } + #[doc = "PWM mode is enabled for CT32Bn_MAT1."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen1::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN1` writer - PWM channel 1 enable"] +pub type Pwmen1W<'a, REG> = crate::BitWriter<'a, REG, Pwmen1>; +impl<'a, REG> Pwmen1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT32Bn_MAT1 is controlled by EM1."] + #[inline(always)] + pub fn ct32bn_mat1_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen1::Ct32bnMat1IsContr) + } + #[doc = "PWM mode is enabled for CT32Bn_MAT1."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen1::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel 2 enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen2 { + #[doc = "0: CT32Bn_MAT2 is controlled by EM2."] + Ct32bnMat2IsContr = 0, + #[doc = "1: PWM mode is enabled for CT32Bn_MAT2."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen2) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN2` reader - PWM channel 2 enable"] +pub type Pwmen2R = crate::BitReader; +impl Pwmen2R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen2 { + match self.bits { + false => Pwmen2::Ct32bnMat2IsContr, + true => Pwmen2::PwmModeIsEnabled_, + } + } + #[doc = "CT32Bn_MAT2 is controlled by EM2."] + #[inline(always)] + pub fn is_ct32bn_mat2_is_contr(&self) -> bool { + *self == Pwmen2::Ct32bnMat2IsContr + } + #[doc = "PWM mode is enabled for CT32Bn_MAT2."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen2::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN2` writer - PWM channel 2 enable"] +pub type Pwmen2W<'a, REG> = crate::BitWriter<'a, REG, Pwmen2>; +impl<'a, REG> Pwmen2W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT32Bn_MAT2 is controlled by EM2."] + #[inline(always)] + pub fn ct32bn_mat2_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen2::Ct32bnMat2IsContr) + } + #[doc = "PWM mode is enabled for CT32Bn_MAT2."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen2::PwmModeIsEnabled_) + } +} +#[doc = "PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pwmen3 { + #[doc = "0: CT32Bn_MAT3 is controlled by EM3."] + Ct32bnMat3IsContr = 0, + #[doc = "1: PWM mode is enabled for CT32Bn_MAT3."] + PwmModeIsEnabled_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pwmen3) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PWMEN3` reader - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."] +pub type Pwmen3R = crate::BitReader; +impl Pwmen3R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pwmen3 { + match self.bits { + false => Pwmen3::Ct32bnMat3IsContr, + true => Pwmen3::PwmModeIsEnabled_, + } + } + #[doc = "CT32Bn_MAT3 is controlled by EM3."] + #[inline(always)] + pub fn is_ct32bn_mat3_is_contr(&self) -> bool { + *self == Pwmen3::Ct32bnMat3IsContr + } + #[doc = "PWM mode is enabled for CT32Bn_MAT3."] + #[inline(always)] + pub fn is_pwm_mode_is_enabled_(&self) -> bool { + *self == Pwmen3::PwmModeIsEnabled_ + } +} +#[doc = "Field `PWMEN3` writer - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."] +pub type Pwmen3W<'a, REG> = crate::BitWriter<'a, REG, Pwmen3>; +impl<'a, REG> Pwmen3W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "CT32Bn_MAT3 is controlled by EM3."] + #[inline(always)] + pub fn ct32bn_mat3_is_contr(self) -> &'a mut crate::W { + self.variant(Pwmen3::Ct32bnMat3IsContr) + } + #[doc = "PWM mode is enabled for CT32Bn_MAT3."] + #[inline(always)] + pub fn pwm_mode_is_enabled_(self) -> &'a mut crate::W { + self.variant(Pwmen3::PwmModeIsEnabled_) + } +} +impl R { + #[doc = "Bit 0 - PWM channel 0 enable"] + #[inline(always)] + pub fn pwmen0(&self) -> Pwmen0R { + Pwmen0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PWM channel 1 enable"] + #[inline(always)] + pub fn pwmen1(&self) -> Pwmen1R { + Pwmen1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - PWM channel 2 enable"] + #[inline(always)] + pub fn pwmen2(&self) -> Pwmen2R { + Pwmen2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."] + #[inline(always)] + pub fn pwmen3(&self) -> Pwmen3R { + Pwmen3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PWM channel 0 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen0(&mut self) -> Pwmen0W { + Pwmen0W::new(self, 0) + } + #[doc = "Bit 1 - PWM channel 1 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen1(&mut self) -> Pwmen1W { + Pwmen1W::new(self, 1) + } + #[doc = "Bit 2 - PWM channel 2 enable"] + #[inline(always)] + #[must_use] + pub fn pwmen2(&mut self) -> Pwmen2W { + Pwmen2W::new(self, 2) + } + #[doc = "Bit 3 - PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle."] + #[inline(always)] + #[must_use] + pub fn pwmen3(&mut self) -> Pwmen3W { + Pwmen3W::new(self, 3) + } +} +#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmcSpec; +impl crate::RegisterSpec for PwmcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmc::R`](R) reader structure"] +impl crate::Readable for PwmcSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmc::W`](W) writer structure"] +impl crate::Writable for PwmcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWMC to value 0"] +impl crate::Resettable for PwmcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/tc.rs b/rust-embedded/lpc111x-pac/src/ct32b0/tc.rs new file mode 100644 index 0000000..fd18d29 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/tc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `TC` reader - Timer counter value."] +pub type TcR = crate::FieldReader; +#[doc = "Field `TC` writer - Timer counter value."] +pub type TcW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timer counter value."] + #[inline(always)] + pub fn tc(&self) -> TcR { + TcR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timer counter value."] + #[inline(always)] + #[must_use] + pub fn tc(&mut self) -> TcW { + TcW::new(self, 0) + } +} +#[doc = "Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs b/rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs new file mode 100644 index 0000000..0f77df1 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/ct32b0/tcr.rs @@ -0,0 +1,59 @@ +#[doc = "Register `TCR` reader"] +pub type R = crate::R; +#[doc = "Register `TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CEN` reader - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] +pub type CenR = crate::BitReader; +#[doc = "Field `CEN` writer - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] +pub type CenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRST` reader - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] +pub type CrstR = crate::BitReader; +#[doc = "Field `CRST` writer - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] +pub type CrstW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] + #[inline(always)] + pub fn cen(&self) -> CenR { + CenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] + #[inline(always)] + pub fn crst(&self) -> CrstR { + CrstR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled."] + #[inline(always)] + #[must_use] + pub fn cen(&mut self) -> CenW { + CenW::new(self, 0) + } + #[doc = "Bit 1 - When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR\\[1\\] +is returned to zero."] + #[inline(always)] + #[must_use] + pub fn crst(&mut self) -> CrstW { + CrstW::new(self, 1) + } +} +#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcrSpec; +impl crate::RegisterSpec for TcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tcr::R`](R) reader structure"] +impl crate::Readable for TcrSpec {} +#[doc = "`write(|w| ..)` method takes [`tcr::W`](W) writer structure"] +impl crate::Writable for TcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TCR to value 0"] +impl crate::Resettable for TcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl.rs b/rust-embedded/lpc111x-pac/src/flashctrl.rs new file mode 100644 index 0000000..f1bbb42 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl.rs @@ -0,0 +1,119 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x10], + flashcfg: Flashcfg, + _reserved1: [u8; 0x0c], + fmsstart: Fmsstart, + fmsstop: Fmsstop, + _reserved3: [u8; 0x04], + fmsw0: Fmsw0, + fmsw1: Fmsw1, + fmsw2: Fmsw2, + fmsw3: Fmsw3, + _reserved7: [u8; 0x0fa4], + fmstat: Fmstat, + _reserved8: [u8; 0x04], + fmstatclr: Fmstatclr, +} +impl RegisterBlock { + #[doc = "0x10 - Flash memory access time configuration register"] + #[inline(always)] + pub const fn flashcfg(&self) -> &Flashcfg { + &self.flashcfg + } + #[doc = "0x20 - Signature start address register"] + #[inline(always)] + pub const fn fmsstart(&self) -> &Fmsstart { + &self.fmsstart + } + #[doc = "0x24 - Signature stop-address register"] + #[inline(always)] + pub const fn fmsstop(&self) -> &Fmsstop { + &self.fmsstop + } + #[doc = "0x2c - Word 0 \\[31:0\\]"] + #[inline(always)] + pub const fn fmsw0(&self) -> &Fmsw0 { + &self.fmsw0 + } + #[doc = "0x30 - Word 1 \\[63:32\\]"] + #[inline(always)] + pub const fn fmsw1(&self) -> &Fmsw1 { + &self.fmsw1 + } + #[doc = "0x34 - Word 2 \\[95:64\\]"] + #[inline(always)] + pub const fn fmsw2(&self) -> &Fmsw2 { + &self.fmsw2 + } + #[doc = "0x38 - Word 3 \\[127:96\\]"] + #[inline(always)] + pub const fn fmsw3(&self) -> &Fmsw3 { + &self.fmsw3 + } + #[doc = "0xfe0 - Signature generation status register"] + #[inline(always)] + pub const fn fmstat(&self) -> &Fmstat { + &self.fmstat + } + #[doc = "0xfe8 - Signature generation status clear register"] + #[inline(always)] + pub const fn fmstatclr(&self) -> &Fmstatclr { + &self.fmstatclr + } +} +#[doc = "FLASHCFG (rw) register accessor: Flash memory access time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flashcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flashcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flashcfg`] +module"] +#[doc(alias = "FLASHCFG")] +pub type Flashcfg = crate::Reg; +#[doc = "Flash memory access time configuration register"] +pub mod flashcfg; +#[doc = "FMSSTART (rw) register accessor: Signature start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstart::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstart::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsstart`] +module"] +#[doc(alias = "FMSSTART")] +pub type Fmsstart = crate::Reg; +#[doc = "Signature start address register"] +pub mod fmsstart; +#[doc = "FMSSTOP (rw) register accessor: Signature stop-address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstop::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsstop`] +module"] +#[doc(alias = "FMSSTOP")] +pub type Fmsstop = crate::Reg; +#[doc = "Signature stop-address register"] +pub mod fmsstop; +#[doc = "FMSW0 (r) register accessor: Word 0 \\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw0`] +module"] +#[doc(alias = "FMSW0")] +pub type Fmsw0 = crate::Reg; +#[doc = "Word 0 \\[31:0\\]"] +pub mod fmsw0; +#[doc = "FMSW1 (r) register accessor: Word 1 \\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw1`] +module"] +#[doc(alias = "FMSW1")] +pub type Fmsw1 = crate::Reg; +#[doc = "Word 1 \\[63:32\\]"] +pub mod fmsw1; +#[doc = "FMSW2 (r) register accessor: Word 2 \\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw2`] +module"] +#[doc(alias = "FMSW2")] +pub type Fmsw2 = crate::Reg; +#[doc = "Word 2 \\[95:64\\]"] +pub mod fmsw2; +#[doc = "FMSW3 (r) register accessor: Word 3 \\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmsw3`] +module"] +#[doc(alias = "FMSW3")] +pub type Fmsw3 = crate::Reg; +#[doc = "Word 3 \\[127:96\\]"] +pub mod fmsw3; +#[doc = "FMSTAT (r) register accessor: Signature generation status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmstat`] +module"] +#[doc(alias = "FMSTAT")] +pub type Fmstat = crate::Reg; +#[doc = "Signature generation status register"] +pub mod fmstat; +#[doc = "FMSTATCLR (w) register accessor: Signature generation status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmstatclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fmstatclr`] +module"] +#[doc(alias = "FMSTATCLR")] +pub type Fmstatclr = crate::Reg; +#[doc = "Signature generation status clear register"] +pub mod fmstatclr; diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/flashcfg.rs b/rust-embedded/lpc111x-pac/src/flashctrl/flashcfg.rs new file mode 100644 index 0000000..cf74540 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/flashcfg.rs @@ -0,0 +1,108 @@ +#[doc = "Register `FLASHCFG` reader"] +pub type R = crate::R; +#[doc = "Register `FLASHCFG` writer"] +pub type W = crate::W; +#[doc = "Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Flashtim { + #[doc = "1: 1 system clock flash access time (for system clock frequencies of up to 20 MHz)."] + _1SystemClockFlash = 1, + #[doc = "2: 2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."] + _2SystemClocksFlas = 2, + #[doc = "3: 3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."] + _3SystemClocksFlas = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Flashtim) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Flashtim { + type Ux = u8; +} +#[doc = "Field `FLASHTIM` reader - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."] +pub type FlashtimR = crate::FieldReader; +impl FlashtimR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Flashtim::_1SystemClockFlash), + 2 => Some(Flashtim::_2SystemClocksFlas), + 3 => Some(Flashtim::_3SystemClocksFlas), + _ => None, + } + } + #[doc = "1 system clock flash access time (for system clock frequencies of up to 20 MHz)."] + #[inline(always)] + pub fn is_1_system_clock_flash(&self) -> bool { + *self == Flashtim::_1SystemClockFlash + } + #[doc = "2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."] + #[inline(always)] + pub fn is_2_system_clocks_flas(&self) -> bool { + *self == Flashtim::_2SystemClocksFlas + } + #[doc = "3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."] + #[inline(always)] + pub fn is_3_system_clocks_flas(&self) -> bool { + *self == Flashtim::_3SystemClocksFlas + } +} +#[doc = "Field `FLASHTIM` writer - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."] +pub type FlashtimW<'a, REG> = crate::FieldWriter<'a, REG, 2, Flashtim>; +impl<'a, REG> FlashtimW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "1 system clock flash access time (for system clock frequencies of up to 20 MHz)."] + #[inline(always)] + pub fn _1_system_clock_flash(self) -> &'a mut crate::W { + self.variant(Flashtim::_1SystemClockFlash) + } + #[doc = "2 system clocks flash access time (for system clock frequencies of up to 40 MHz)."] + #[inline(always)] + pub fn _2_system_clocks_flas(self) -> &'a mut crate::W { + self.variant(Flashtim::_2SystemClocksFlas) + } + #[doc = "3 system clocks flash access time (for system clock frequencies of up to 50 MHz)."] + #[inline(always)] + pub fn _3_system_clocks_flas(self) -> &'a mut crate::W { + self.variant(Flashtim::_3SystemClocksFlas) + } +} +impl R { + #[doc = "Bits 0:1 - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."] + #[inline(always)] + pub fn flashtim(&self) -> FlashtimR { + FlashtimR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access."] + #[inline(always)] + #[must_use] + pub fn flashtim(&mut self) -> FlashtimW { + FlashtimW::new(self, 0) + } +} +#[doc = "Flash memory access time configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flashcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flashcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FlashcfgSpec; +impl crate::RegisterSpec for FlashcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`flashcfg::R`](R) reader structure"] +impl crate::Readable for FlashcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`flashcfg::W`](W) writer structure"] +impl crate::Writable for FlashcfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FLASHCFG to value 0"] +impl crate::Resettable for FlashcfgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsstart.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsstart.rs new file mode 100644 index 0000000..74526c8 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsstart.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FMSSTART` reader"] +pub type R = crate::R; +#[doc = "Register `FMSSTART` writer"] +pub type W = crate::W; +#[doc = "Field `START` reader - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."] +pub type StartR = crate::FieldReader; +#[doc = "Field `START` writer - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."] +pub type StartW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +impl R { + #[doc = "Bits 0:16 - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new(self.bits & 0x0001_ffff) + } +} +impl W { + #[doc = "Bits 0:16 - Signature generation start address (corresponds to AHB byte address bits\\[20:4\\])."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> StartW { + StartW::new(self, 0) + } +} +#[doc = "Signature start address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstart::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstart::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FmsstartSpec; +impl crate::RegisterSpec for FmsstartSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsstart::R`](R) reader structure"] +impl crate::Readable for FmsstartSpec {} +#[doc = "`write(|w| ..)` method takes [`fmsstart::W`](W) writer structure"] +impl crate::Writable for FmsstartSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FMSSTART to value 0"] +impl crate::Resettable for FmsstartSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsstop.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsstop.rs new file mode 100644 index 0000000..823ae02 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsstop.rs @@ -0,0 +1,104 @@ +#[doc = "Register `FMSSTOP` reader"] +pub type R = crate::R; +#[doc = "Register `FMSSTOP` writer"] +pub type W = crate::W; +#[doc = "Field `STOP` reader - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."] +pub type StopR = crate::FieldReader; +#[doc = "Field `STOP` writer - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."] +pub type StopW<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>; +#[doc = "Start control bit for signature generation.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SigStart { + #[doc = "0: Signature generation is stopped"] + SignatureGeneration = 0, + #[doc = "1: Initiate signature generation"] + InitiateSignatureG = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SigStart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SIG_START` reader - Start control bit for signature generation."] +pub type SigStartR = crate::BitReader; +impl SigStartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SigStart { + match self.bits { + false => SigStart::SignatureGeneration, + true => SigStart::InitiateSignatureG, + } + } + #[doc = "Signature generation is stopped"] + #[inline(always)] + pub fn is_signature_generation(&self) -> bool { + *self == SigStart::SignatureGeneration + } + #[doc = "Initiate signature generation"] + #[inline(always)] + pub fn is_initiate_signature_g(&self) -> bool { + *self == SigStart::InitiateSignatureG + } +} +#[doc = "Field `SIG_START` writer - Start control bit for signature generation."] +pub type SigStartW<'a, REG> = crate::BitWriter<'a, REG, SigStart>; +impl<'a, REG> SigStartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Signature generation is stopped"] + #[inline(always)] + pub fn signature_generation(self) -> &'a mut crate::W { + self.variant(SigStart::SignatureGeneration) + } + #[doc = "Initiate signature generation"] + #[inline(always)] + pub fn initiate_signature_g(self) -> &'a mut crate::W { + self.variant(SigStart::InitiateSignatureG) + } +} +impl R { + #[doc = "Bits 0:16 - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."] + #[inline(always)] + pub fn stop(&self) -> StopR { + StopR::new(self.bits & 0x0001_ffff) + } + #[doc = "Bit 17 - Start control bit for signature generation."] + #[inline(always)] + pub fn sig_start(&self) -> SigStartR { + SigStartR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:16 - BIST stop address divided by 16 (corresponds to AHB byte address \\[20:4\\])."] + #[inline(always)] + #[must_use] + pub fn stop(&mut self) -> StopW { + StopW::new(self, 0) + } + #[doc = "Bit 17 - Start control bit for signature generation."] + #[inline(always)] + #[must_use] + pub fn sig_start(&mut self) -> SigStartW { + SigStartW::new(self, 17) + } +} +#[doc = "Signature stop-address register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsstop::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmsstop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FmsstopSpec; +impl crate::RegisterSpec for FmsstopSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsstop::R`](R) reader structure"] +impl crate::Readable for FmsstopSpec {} +#[doc = "`write(|w| ..)` method takes [`fmsstop::W`](W) writer structure"] +impl crate::Writable for FmsstopSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FMSSTOP to value 0"] +impl crate::Resettable for FmsstopSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmstat.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmstat.rs new file mode 100644 index 0000000..eec4ad2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmstat.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FMSTAT` reader"] +pub type R = crate::R; +#[doc = "Field `SIG_DONE` reader - When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag."] +pub type SigDoneR = crate::BitReader; +impl R { + #[doc = "Bit 2 - When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag."] + #[inline(always)] + pub fn sig_done(&self) -> SigDoneR { + SigDoneR::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "Signature generation status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FmstatSpec; +impl crate::RegisterSpec for FmstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmstat::R`](R) reader structure"] +impl crate::Readable for FmstatSpec {} +#[doc = "`reset()` method sets FMSTAT to value 0"] +impl crate::Resettable for FmstatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmstatclr.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmstatclr.rs new file mode 100644 index 0000000..8b438d0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmstatclr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `FMSTATCLR` writer"] +pub type W = crate::W; +#[doc = "Field `SIG_DONE_CLR` writer - Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register."] +pub type SigDoneClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 2 - Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register."] + #[inline(always)] + #[must_use] + pub fn sig_done_clr(&mut self) -> SigDoneClrW { + SigDoneClrW::new(self, 2) + } +} +#[doc = "Signature generation status clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmstatclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FmstatclrSpec; +impl crate::RegisterSpec for FmstatclrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fmstatclr::W`](W) writer structure"] +impl crate::Writable for FmstatclrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FMSTATCLR to value 0"] +impl crate::Resettable for FmstatclrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsw0.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw0.rs new file mode 100644 index 0000000..3679e2b --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FMSW0` reader"] +pub type R = crate::R; +#[doc = "Field `SW0_31_0` reader - Word 0 of 128-bit signature (bits 31 to 0)."] +pub type Sw0_31_0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Word 0 of 128-bit signature (bits 31 to 0)."] + #[inline(always)] + pub fn sw0_31_0(&self) -> Sw0_31_0R { + Sw0_31_0R::new(self.bits) + } +} +#[doc = "Word 0 \\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fmsw0Spec; +impl crate::RegisterSpec for Fmsw0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsw0::R`](R) reader structure"] +impl crate::Readable for Fmsw0Spec {} +#[doc = "`reset()` method sets FMSW0 to value 0"] +impl crate::Resettable for Fmsw0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsw1.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw1.rs new file mode 100644 index 0000000..539e056 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FMSW1` reader"] +pub type R = crate::R; +#[doc = "Field `SW1_63_32` reader - Word 1 of 128-bit signature (bits 63 to 32)."] +pub type Sw1_63_32R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Word 1 of 128-bit signature (bits 63 to 32)."] + #[inline(always)] + pub fn sw1_63_32(&self) -> Sw1_63_32R { + Sw1_63_32R::new(self.bits) + } +} +#[doc = "Word 1 \\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fmsw1Spec; +impl crate::RegisterSpec for Fmsw1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsw1::R`](R) reader structure"] +impl crate::Readable for Fmsw1Spec {} +#[doc = "`reset()` method sets FMSW1 to value 0"] +impl crate::Resettable for Fmsw1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsw2.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw2.rs new file mode 100644 index 0000000..dbb0920 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FMSW2` reader"] +pub type R = crate::R; +#[doc = "Field `SW2_95_64` reader - Word 2 of 128-bit signature (bits 95 to 64)."] +pub type Sw2_95_64R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Word 2 of 128-bit signature (bits 95 to 64)."] + #[inline(always)] + pub fn sw2_95_64(&self) -> Sw2_95_64R { + Sw2_95_64R::new(self.bits) + } +} +#[doc = "Word 2 \\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fmsw2Spec; +impl crate::RegisterSpec for Fmsw2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsw2::R`](R) reader structure"] +impl crate::Readable for Fmsw2Spec {} +#[doc = "`reset()` method sets FMSW2 to value 0"] +impl crate::Resettable for Fmsw2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/flashctrl/fmsw3.rs b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw3.rs new file mode 100644 index 0000000..2716bfd --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/flashctrl/fmsw3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `FMSW3` reader"] +pub type R = crate::R; +#[doc = "Field `SW3_127_96` reader - Word 3 of 128-bit signature (bits 127 to 96)."] +pub type Sw3_127_96R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Word 3 of 128-bit signature (bits 127 to 96)."] + #[inline(always)] + pub fn sw3_127_96(&self) -> Sw3_127_96R { + Sw3_127_96R::new(self.bits) + } +} +#[doc = "Word 3 \\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmsw3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Fmsw3Spec; +impl crate::RegisterSpec for Fmsw3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fmsw3::R`](R) reader structure"] +impl crate::Readable for Fmsw3Spec {} +#[doc = "`reset()` method sets FMSW3 to value 0"] +impl crate::Resettable for Fmsw3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/generic.rs b/rust-embedded/lpc111x-pac/src/generic.rs new file mode 100644 index 0000000..db0f701 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/generic.rs @@ -0,0 +1,547 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + PartialEq + From; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Safe>; +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +impl<'a, REG, const WI: u8, FI> FieldWriterSafe<'a, REG, WI, FI> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bits(FI::Ux::from(variant)) + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} diff --git a/rust-embedded/lpc111x-pac/src/generic/raw.rs b/rust-embedded/lpc111x-pac/src/generic/raw.rs new file mode 100644 index 0000000..81f5779 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/generic/raw.rs @@ -0,0 +1,93 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0.rs b/rust-embedded/lpc111x-pac/src/gpio0.rs new file mode 100644 index 0000000..decab42 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0.rs @@ -0,0 +1,116 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x3ffc], + data: Data, + _reserved1: [u8; 0x4000], + dir: Dir, + is: Is, + ibe: Ibe, + iev: Iev, + ie: Ie, + ris: Ris, + mis: Mis, + ic: Ic, +} +impl RegisterBlock { + #[doc = "0x3ffc - Port n data register for pins PIOn_0 to PIOn_11"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x8000 - Data direction register for port n"] + #[inline(always)] + pub const fn dir(&self) -> &Dir { + &self.dir + } + #[doc = "0x8004 - Interrupt sense register for port n"] + #[inline(always)] + pub const fn is(&self) -> &Is { + &self.is + } + #[doc = "0x8008 - Interrupt both edges register for port n"] + #[inline(always)] + pub const fn ibe(&self) -> &Ibe { + &self.ibe + } + #[doc = "0x800c - Interrupt event register for port n"] + #[inline(always)] + pub const fn iev(&self) -> &Iev { + &self.iev + } + #[doc = "0x8010 - Interrupt mask register for port n"] + #[inline(always)] + pub const fn ie(&self) -> &Ie { + &self.ie + } + #[doc = "0x8014 - Raw interrupt status register for port n"] + #[inline(always)] + pub const fn ris(&self) -> &Ris { + &self.ris + } + #[doc = "0x8018 - Masked interrupt status register for port n"] + #[inline(always)] + pub const fn mis(&self) -> &Mis { + &self.mis + } + #[doc = "0x801c - Interrupt clear register for port n"] + #[inline(always)] + pub const fn ic(&self) -> &Ic { + &self.ic + } +} +#[doc = "DATA (rw) register accessor: Port n data register for pins PIOn_0 to PIOn_11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Port n data register for pins PIOn_0 to PIOn_11"] +pub mod data; +#[doc = "DIR (rw) register accessor: Data direction register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dir`] +module"] +#[doc(alias = "DIR")] +pub type Dir = crate::Reg; +#[doc = "Data direction register for port n"] +pub mod dir; +#[doc = "IS (rw) register accessor: Interrupt sense register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`is::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`is::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@is`] +module"] +#[doc(alias = "IS")] +pub type Is = crate::Reg; +#[doc = "Interrupt sense register for port n"] +pub mod is; +#[doc = "IBE (rw) register accessor: Interrupt both edges register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibe`] +module"] +#[doc(alias = "IBE")] +pub type Ibe = crate::Reg; +#[doc = "Interrupt both edges register for port n"] +pub mod ibe; +#[doc = "IEV (rw) register accessor: Interrupt event register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iev::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iev`] +module"] +#[doc(alias = "IEV")] +pub type Iev = crate::Reg; +#[doc = "Interrupt event register for port n"] +pub mod iev; +#[doc = "IE (rw) register accessor: Interrupt mask register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`] +module"] +#[doc(alias = "IE")] +pub type Ie = crate::Reg; +#[doc = "Interrupt mask register for port n"] +pub mod ie; +#[doc = "RIS (r) register accessor: Raw interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] +module"] +#[doc(alias = "RIS")] +pub type Ris = crate::Reg; +#[doc = "Raw interrupt status register for port n"] +pub mod ris; +#[doc = "MIS (r) register accessor: Masked interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] +module"] +#[doc(alias = "MIS")] +pub type Mis = crate::Reg; +#[doc = "Masked interrupt status register for port n"] +pub mod mis; +#[doc = "IC (w) register accessor: Interrupt clear register for port n\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ic`] +module"] +#[doc(alias = "IC")] +pub type Ic = crate::Reg; +#[doc = "Interrupt clear register for port n"] +pub mod ic; diff --git a/rust-embedded/lpc111x-pac/src/gpio0/data.rs b/rust-embedded/lpc111x-pac/src/gpio0/data.rs new file mode 100644 index 0000000..f4d98be --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/data.rs @@ -0,0 +1,205 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA0` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data0R = crate::BitReader; +#[doc = "Field `DATA0` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA1` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data1R = crate::BitReader; +#[doc = "Field `DATA1` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA2` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data2R = crate::BitReader; +#[doc = "Field `DATA2` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA3` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data3R = crate::BitReader; +#[doc = "Field `DATA3` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA4` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data4R = crate::BitReader; +#[doc = "Field `DATA4` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA5` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data5R = crate::BitReader; +#[doc = "Field `DATA5` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA6` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data6R = crate::BitReader; +#[doc = "Field `DATA6` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA7` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data7R = crate::BitReader; +#[doc = "Field `DATA7` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA8` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data8R = crate::BitReader; +#[doc = "Field `DATA8` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA9` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data9R = crate::BitReader; +#[doc = "Field `DATA9` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA10` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data10R = crate::BitReader; +#[doc = "Field `DATA10` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DATA11` reader - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data11R = crate::BitReader; +#[doc = "Field `DATA11` writer - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] +pub type Data11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data0(&self) -> Data0R { + Data0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data1(&self) -> Data1R { + Data1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data2(&self) -> Data2R { + Data2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data3(&self) -> Data3R { + Data3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data4(&self) -> Data4R { + Data4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data5(&self) -> Data5R { + Data5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data6(&self) -> Data6R { + Data6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data7(&self) -> Data7R { + Data7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data8(&self) -> Data8R { + Data8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data9(&self) -> Data9R { + Data9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data10(&self) -> Data10R { + Data10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + pub fn data11(&self) -> Data11R { + Data11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data0(&mut self) -> Data0W { + Data0W::new(self, 0) + } + #[doc = "Bit 1 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data1(&mut self) -> Data1W { + Data1W::new(self, 1) + } + #[doc = "Bit 2 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data2(&mut self) -> Data2W { + Data2W::new(self, 2) + } + #[doc = "Bit 3 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data3(&mut self) -> Data3W { + Data3W::new(self, 3) + } + #[doc = "Bit 4 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data4(&mut self) -> Data4W { + Data4W::new(self, 4) + } + #[doc = "Bit 5 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data5(&mut self) -> Data5W { + Data5W::new(self, 5) + } + #[doc = "Bit 6 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data6(&mut self) -> Data6W { + Data6W::new(self, 6) + } + #[doc = "Bit 7 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data7(&mut self) -> Data7W { + Data7W::new(self, 7) + } + #[doc = "Bit 8 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data8(&mut self) -> Data8W { + Data8W::new(self, 8) + } + #[doc = "Bit 9 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data9(&mut self) -> Data9W { + Data9W::new(self, 9) + } + #[doc = "Bit 10 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data10(&mut self) -> Data10W { + Data10W::new(self, 10) + } + #[doc = "Bit 11 - Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0."] + #[inline(always)] + #[must_use] + pub fn data11(&mut self) -> Data11W { + Data11W::new(self, 11) + } +} +#[doc = "Port n data register for pins PIOn_0 to PIOn_11\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/dir.rs b/rust-embedded/lpc111x-pac/src/gpio0/dir.rs new file mode 100644 index 0000000..c7dc6d7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/dir.rs @@ -0,0 +1,205 @@ +#[doc = "Register `DIR` reader"] +pub type R = crate::R; +#[doc = "Register `DIR` writer"] +pub type W = crate::W; +#[doc = "Field `IO0` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io0R = crate::BitReader; +#[doc = "Field `IO0` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO1` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io1R = crate::BitReader; +#[doc = "Field `IO1` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO2` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io2R = crate::BitReader; +#[doc = "Field `IO2` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO3` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io3R = crate::BitReader; +#[doc = "Field `IO3` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO4` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io4R = crate::BitReader; +#[doc = "Field `IO4` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO5` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io5R = crate::BitReader; +#[doc = "Field `IO5` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO6` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io6R = crate::BitReader; +#[doc = "Field `IO6` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO7` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io7R = crate::BitReader; +#[doc = "Field `IO7` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO8` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io8R = crate::BitReader; +#[doc = "Field `IO8` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO9` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io9R = crate::BitReader; +#[doc = "Field `IO9` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO10` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io10R = crate::BitReader; +#[doc = "Field `IO10` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO11` reader - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io11R = crate::BitReader; +#[doc = "Field `IO11` writer - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] +pub type Io11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io0(&self) -> Io0R { + Io0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io1(&self) -> Io1R { + Io1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io2(&self) -> Io2R { + Io2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io3(&self) -> Io3R { + Io3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io4(&self) -> Io4R { + Io4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io5(&self) -> Io5R { + Io5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io6(&self) -> Io6R { + Io6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io7(&self) -> Io7R { + Io7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io8(&self) -> Io8R { + Io8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io9(&self) -> Io9R { + Io9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io10(&self) -> Io10R { + Io10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + pub fn io11(&self) -> Io11R { + Io11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io0(&mut self) -> Io0W { + Io0W::new(self, 0) + } + #[doc = "Bit 1 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io1(&mut self) -> Io1W { + Io1W::new(self, 1) + } + #[doc = "Bit 2 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io2(&mut self) -> Io2W { + Io2W::new(self, 2) + } + #[doc = "Bit 3 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io3(&mut self) -> Io3W { + Io3W::new(self, 3) + } + #[doc = "Bit 4 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io4(&mut self) -> Io4W { + Io4W::new(self, 4) + } + #[doc = "Bit 5 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io5(&mut self) -> Io5W { + Io5W::new(self, 5) + } + #[doc = "Bit 6 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io6(&mut self) -> Io6W { + Io6W::new(self, 6) + } + #[doc = "Bit 7 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io7(&mut self) -> Io7W { + Io7W::new(self, 7) + } + #[doc = "Bit 8 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io8(&mut self) -> Io8W { + Io8W::new(self, 8) + } + #[doc = "Bit 9 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io9(&mut self) -> Io9W { + Io9W::new(self, 9) + } + #[doc = "Bit 10 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io10(&mut self) -> Io10W { + Io10W::new(self, 10) + } + #[doc = "Bit 11 - Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output."] + #[inline(always)] + #[must_use] + pub fn io11(&mut self) -> Io11W { + Io11W::new(self, 11) + } +} +#[doc = "Data direction register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DirSpec; +impl crate::RegisterSpec for DirSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dir::R`](R) reader structure"] +impl crate::Readable for DirSpec {} +#[doc = "`write(|w| ..)` method takes [`dir::W`](W) writer structure"] +impl crate::Writable for DirSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIR to value 0"] +impl crate::Resettable for DirSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/ibe.rs b/rust-embedded/lpc111x-pac/src/gpio0/ibe.rs new file mode 100644 index 0000000..11e74bc --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/ibe.rs @@ -0,0 +1,205 @@ +#[doc = "Register `IBE` reader"] +pub type R = crate::R; +#[doc = "Register `IBE` writer"] +pub type W = crate::W; +#[doc = "Field `IBE0` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe0R = crate::BitReader; +#[doc = "Field `IBE0` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE1` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe1R = crate::BitReader; +#[doc = "Field `IBE1` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE2` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe2R = crate::BitReader; +#[doc = "Field `IBE2` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE3` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe3R = crate::BitReader; +#[doc = "Field `IBE3` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE4` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe4R = crate::BitReader; +#[doc = "Field `IBE4` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE5` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe5R = crate::BitReader; +#[doc = "Field `IBE5` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE6` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe6R = crate::BitReader; +#[doc = "Field `IBE6` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE7` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe7R = crate::BitReader; +#[doc = "Field `IBE7` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE8` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe8R = crate::BitReader; +#[doc = "Field `IBE8` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE9` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe9R = crate::BitReader; +#[doc = "Field `IBE9` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE10` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe10R = crate::BitReader; +#[doc = "Field `IBE10` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IBE11` reader - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe11R = crate::BitReader; +#[doc = "Field `IBE11` writer - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] +pub type Ibe11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe0(&self) -> Ibe0R { + Ibe0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe1(&self) -> Ibe1R { + Ibe1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe2(&self) -> Ibe2R { + Ibe2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe3(&self) -> Ibe3R { + Ibe3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe4(&self) -> Ibe4R { + Ibe4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe5(&self) -> Ibe5R { + Ibe5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe6(&self) -> Ibe6R { + Ibe6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe7(&self) -> Ibe7R { + Ibe7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe8(&self) -> Ibe8R { + Ibe8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe9(&self) -> Ibe9R { + Ibe9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe10(&self) -> Ibe10R { + Ibe10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn ibe11(&self) -> Ibe11R { + Ibe11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe0(&mut self) -> Ibe0W { + Ibe0W::new(self, 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe1(&mut self) -> Ibe1W { + Ibe1W::new(self, 1) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe2(&mut self) -> Ibe2W { + Ibe2W::new(self, 2) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe3(&mut self) -> Ibe3W { + Ibe3W::new(self, 3) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe4(&mut self) -> Ibe4W { + Ibe4W::new(self, 4) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe5(&mut self) -> Ibe5W { + Ibe5W::new(self, 5) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe6(&mut self) -> Ibe6W { + Ibe6W::new(self, 6) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe7(&mut self) -> Ibe7W { + Ibe7W::new(self, 7) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe8(&mut self) -> Ibe8W { + Ibe8W::new(self, 8) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe9(&mut self) -> Ibe9W { + Ibe9W::new(self, 9) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe10(&mut self) -> Ibe10W { + Ibe10W::new(self, 10) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn ibe11(&mut self) -> Ibe11W { + Ibe11W::new(self, 11) + } +} +#[doc = "Interrupt both edges register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IbeSpec; +impl crate::RegisterSpec for IbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ibe::R`](R) reader structure"] +impl crate::Readable for IbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ibe::W`](W) writer structure"] +impl crate::Writable for IbeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IBE to value 0"] +impl crate::Resettable for IbeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/ic.rs b/rust-embedded/lpc111x-pac/src/gpio0/ic.rs new file mode 100644 index 0000000..86654de --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/ic.rs @@ -0,0 +1,115 @@ +#[doc = "Register `IC` writer"] +pub type W = crate::W; +#[doc = "Field `CLR0` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR1` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR2` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR3` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR4` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR5` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR6` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR7` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR8` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR9` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR10` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR11` writer - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] +pub type Clr11W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr0(&mut self) -> Clr0W { + Clr0W::new(self, 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr1(&mut self) -> Clr1W { + Clr1W::new(self, 1) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr2(&mut self) -> Clr2W { + Clr2W::new(self, 2) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr3(&mut self) -> Clr3W { + Clr3W::new(self, 3) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr4(&mut self) -> Clr4W { + Clr4W::new(self, 4) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr5(&mut self) -> Clr5W { + Clr5W::new(self, 5) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr6(&mut self) -> Clr6W { + Clr6W::new(self, 6) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr7(&mut self) -> Clr7W { + Clr7W::new(self, 7) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr8(&mut self) -> Clr8W { + Clr8W::new(self, 8) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr9(&mut self) -> Clr9W { + Clr9W::new(self, 9) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr10(&mut self) -> Clr10W { + Clr10W::new(self, 10) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x."] + #[inline(always)] + #[must_use] + pub fn clr11(&mut self) -> Clr11W { + Clr11W::new(self, 11) + } +} +#[doc = "Interrupt clear register for port n\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ic::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IcSpec; +impl crate::RegisterSpec for IcSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`ic::W`](W) writer structure"] +impl crate::Writable for IcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC to value 0"] +impl crate::Resettable for IcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/ie.rs b/rust-embedded/lpc111x-pac/src/gpio0/ie.rs new file mode 100644 index 0000000..d227012 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/ie.rs @@ -0,0 +1,205 @@ +#[doc = "Register `IE` reader"] +pub type R = crate::R; +#[doc = "Register `IE` writer"] +pub type W = crate::W; +#[doc = "Field `MASK0` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask0R = crate::BitReader; +#[doc = "Field `MASK0` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK1` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask1R = crate::BitReader; +#[doc = "Field `MASK1` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK2` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask2R = crate::BitReader; +#[doc = "Field `MASK2` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK3` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask3R = crate::BitReader; +#[doc = "Field `MASK3` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK4` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask4R = crate::BitReader; +#[doc = "Field `MASK4` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK5` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask5R = crate::BitReader; +#[doc = "Field `MASK5` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK6` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask6R = crate::BitReader; +#[doc = "Field `MASK6` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK7` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask7R = crate::BitReader; +#[doc = "Field `MASK7` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK8` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask8R = crate::BitReader; +#[doc = "Field `MASK8` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK9` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask9R = crate::BitReader; +#[doc = "Field `MASK9` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK10` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask10R = crate::BitReader; +#[doc = "Field `MASK10` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK11` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask11R = crate::BitReader; +#[doc = "Field `MASK11` writer - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] +pub type Mask11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask0(&self) -> Mask0R { + Mask0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask1(&self) -> Mask1R { + Mask1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask2(&self) -> Mask2R { + Mask2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask3(&self) -> Mask3R { + Mask3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask4(&self) -> Mask4R { + Mask4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask5(&self) -> Mask5R { + Mask5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask6(&self) -> Mask6R { + Mask6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask7(&self) -> Mask7R { + Mask7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask8(&self) -> Mask8R { + Mask8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask9(&self) -> Mask9R { + Mask9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask10(&self) -> Mask10R { + Mask10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + pub fn mask11(&self) -> Mask11R { + Mask11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask0(&mut self) -> Mask0W { + Mask0W::new(self, 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask1(&mut self) -> Mask1W { + Mask1W::new(self, 1) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask2(&mut self) -> Mask2W { + Mask2W::new(self, 2) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask3(&mut self) -> Mask3W { + Mask3W::new(self, 3) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask4(&mut self) -> Mask4W { + Mask4W::new(self, 4) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask5(&mut self) -> Mask5W { + Mask5W::new(self, 5) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask6(&mut self) -> Mask6W { + Mask6W::new(self, 6) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask7(&mut self) -> Mask7W { + Mask7W::new(self, 7) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask8(&mut self) -> Mask8W { + Mask8W::new(self, 8) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask9(&mut self) -> Mask9W { + Mask9W::new(self, 9) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask10(&mut self) -> Mask10W { + Mask10W::new(self, 10) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked."] + #[inline(always)] + #[must_use] + pub fn mask11(&mut self) -> Mask11W { + Mask11W::new(self, 11) + } +} +#[doc = "Interrupt mask register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IeSpec; +impl crate::RegisterSpec for IeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ie::R`](R) reader structure"] +impl crate::Readable for IeSpec {} +#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"] +impl crate::Writable for IeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IE to value 0"] +impl crate::Resettable for IeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/iev.rs b/rust-embedded/lpc111x-pac/src/gpio0/iev.rs new file mode 100644 index 0000000..7006331 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/iev.rs @@ -0,0 +1,205 @@ +#[doc = "Register `IEV` reader"] +pub type R = crate::R; +#[doc = "Register `IEV` writer"] +pub type W = crate::W; +#[doc = "Field `IEV0` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev0R = crate::BitReader; +#[doc = "Field `IEV0` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV1` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev1R = crate::BitReader; +#[doc = "Field `IEV1` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV2` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev2R = crate::BitReader; +#[doc = "Field `IEV2` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV3` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev3R = crate::BitReader; +#[doc = "Field `IEV3` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV4` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev4R = crate::BitReader; +#[doc = "Field `IEV4` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV5` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev5R = crate::BitReader; +#[doc = "Field `IEV5` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV6` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev6R = crate::BitReader; +#[doc = "Field `IEV6` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV7` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev7R = crate::BitReader; +#[doc = "Field `IEV7` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV8` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev8R = crate::BitReader; +#[doc = "Field `IEV8` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV9` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev9R = crate::BitReader; +#[doc = "Field `IEV9` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV10` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev10R = crate::BitReader; +#[doc = "Field `IEV10` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEV11` reader - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev11R = crate::BitReader; +#[doc = "Field `IEV11` writer - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] +pub type Iev11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev0(&self) -> Iev0R { + Iev0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev1(&self) -> Iev1R { + Iev1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev2(&self) -> Iev2R { + Iev2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev3(&self) -> Iev3R { + Iev3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev4(&self) -> Iev4R { + Iev4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev5(&self) -> Iev5R { + Iev5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev6(&self) -> Iev6R { + Iev6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev7(&self) -> Iev7R { + Iev7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev8(&self) -> Iev8R { + Iev8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev9(&self) -> Iev9R { + Iev9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev10(&self) -> Iev10R { + Iev10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + pub fn iev11(&self) -> Iev11R { + Iev11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev0(&mut self) -> Iev0W { + Iev0W::new(self, 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev1(&mut self) -> Iev1W { + Iev1W::new(self, 1) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev2(&mut self) -> Iev2W { + Iev2W::new(self, 2) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev3(&mut self) -> Iev3W { + Iev3W::new(self, 3) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev4(&mut self) -> Iev4W { + Iev4W::new(self, 4) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev5(&mut self) -> Iev5W { + Iev5W::new(self, 5) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev6(&mut self) -> Iev6W { + Iev6W::new(self, 6) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev7(&mut self) -> Iev7W { + Iev7W::new(self, 7) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev8(&mut self) -> Iev8W { + Iev8W::new(self, 8) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev9(&mut self) -> Iev9W { + Iev9W::new(self, 9) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev10(&mut self) -> Iev10W { + Iev10W::new(self, 10) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt."] + #[inline(always)] + #[must_use] + pub fn iev11(&mut self) -> Iev11W { + Iev11W::new(self, 11) + } +} +#[doc = "Interrupt event register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iev::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IevSpec; +impl crate::RegisterSpec for IevSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`iev::R`](R) reader structure"] +impl crate::Readable for IevSpec {} +#[doc = "`write(|w| ..)` method takes [`iev::W`](W) writer structure"] +impl crate::Writable for IevSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IEV to value 0"] +impl crate::Resettable for IevSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/is.rs b/rust-embedded/lpc111x-pac/src/gpio0/is.rs new file mode 100644 index 0000000..ca4297e --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/is.rs @@ -0,0 +1,205 @@ +#[doc = "Register `IS` reader"] +pub type R = crate::R; +#[doc = "Register `IS` writer"] +pub type W = crate::W; +#[doc = "Field `ISENSE0` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense0R = crate::BitReader; +#[doc = "Field `ISENSE0` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE1` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense1R = crate::BitReader; +#[doc = "Field `ISENSE1` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE2` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense2R = crate::BitReader; +#[doc = "Field `ISENSE2` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE3` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense3R = crate::BitReader; +#[doc = "Field `ISENSE3` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE4` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense4R = crate::BitReader; +#[doc = "Field `ISENSE4` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE5` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense5R = crate::BitReader; +#[doc = "Field `ISENSE5` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE6` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense6R = crate::BitReader; +#[doc = "Field `ISENSE6` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE7` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense7R = crate::BitReader; +#[doc = "Field `ISENSE7` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE8` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense8R = crate::BitReader; +#[doc = "Field `ISENSE8` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE9` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense9R = crate::BitReader; +#[doc = "Field `ISENSE9` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE10` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense10R = crate::BitReader; +#[doc = "Field `ISENSE10` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISENSE11` reader - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense11R = crate::BitReader; +#[doc = "Field `ISENSE11` writer - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] +pub type Isense11W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense0(&self) -> Isense0R { + Isense0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense1(&self) -> Isense1R { + Isense1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense2(&self) -> Isense2R { + Isense2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense3(&self) -> Isense3R { + Isense3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense4(&self) -> Isense4R { + Isense4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense5(&self) -> Isense5R { + Isense5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense6(&self) -> Isense6R { + Isense6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense7(&self) -> Isense7R { + Isense7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense8(&self) -> Isense8R { + Isense8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense9(&self) -> Isense9R { + Isense9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense10(&self) -> Isense10R { + Isense10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + pub fn isense11(&self) -> Isense11R { + Isense11R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense0(&mut self) -> Isense0W { + Isense0W::new(self, 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense1(&mut self) -> Isense1W { + Isense1W::new(self, 1) + } + #[doc = "Bit 2 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense2(&mut self) -> Isense2W { + Isense2W::new(self, 2) + } + #[doc = "Bit 3 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense3(&mut self) -> Isense3W { + Isense3W::new(self, 3) + } + #[doc = "Bit 4 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense4(&mut self) -> Isense4W { + Isense4W::new(self, 4) + } + #[doc = "Bit 5 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense5(&mut self) -> Isense5W { + Isense5W::new(self, 5) + } + #[doc = "Bit 6 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense6(&mut self) -> Isense6W { + Isense6W::new(self, 6) + } + #[doc = "Bit 7 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense7(&mut self) -> Isense7W { + Isense7W::new(self, 7) + } + #[doc = "Bit 8 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense8(&mut self) -> Isense8W { + Isense8W::new(self, 8) + } + #[doc = "Bit 9 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense9(&mut self) -> Isense9W { + Isense9W::new(self, 9) + } + #[doc = "Bit 10 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense10(&mut self) -> Isense10W { + Isense10W::new(self, 10) + } + #[doc = "Bit 11 - Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive."] + #[inline(always)] + #[must_use] + pub fn isense11(&mut self) -> Isense11W { + Isense11W::new(self, 11) + } +} +#[doc = "Interrupt sense register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`is::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`is::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IsSpec; +impl crate::RegisterSpec for IsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`is::R`](R) reader structure"] +impl crate::Readable for IsSpec {} +#[doc = "`write(|w| ..)` method takes [`is::W`](W) writer structure"] +impl crate::Writable for IsSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IS to value 0"] +impl crate::Resettable for IsSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/mis.rs b/rust-embedded/lpc111x-pac/src/gpio0/mis.rs new file mode 100644 index 0000000..d0e7d50 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/mis.rs @@ -0,0 +1,99 @@ +#[doc = "Register `MIS` reader"] +pub type R = crate::R; +#[doc = "Field `MASK0` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask0R = crate::BitReader; +#[doc = "Field `MASK1` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask1R = crate::BitReader; +#[doc = "Field `MASK2` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask2R = crate::BitReader; +#[doc = "Field `MASK3` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask3R = crate::BitReader; +#[doc = "Field `MASK4` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask4R = crate::BitReader; +#[doc = "Field `MASK5` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask5R = crate::BitReader; +#[doc = "Field `MASK6` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask6R = crate::BitReader; +#[doc = "Field `MASK7` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask7R = crate::BitReader; +#[doc = "Field `MASK8` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask8R = crate::BitReader; +#[doc = "Field `MASK9` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask9R = crate::BitReader; +#[doc = "Field `MASK10` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask10R = crate::BitReader; +#[doc = "Field `MASK11` reader - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] +pub type Mask11R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask0(&self) -> Mask0R { + Mask0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask1(&self) -> Mask1R { + Mask1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask2(&self) -> Mask2R { + Mask2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask3(&self) -> Mask3R { + Mask3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask4(&self) -> Mask4R { + Mask4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask5(&self) -> Mask5R { + Mask5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask6(&self) -> Mask6R { + Mask6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask7(&self) -> Mask7R { + Mask7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask8(&self) -> Mask8R { + Mask8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask9(&self) -> Mask9R { + Mask9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask10(&self) -> Mask10R { + Mask10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x."] + #[inline(always)] + pub fn mask11(&self) -> Mask11R { + Mask11R::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Masked interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MisSpec; +impl crate::RegisterSpec for MisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mis::R`](R) reader structure"] +impl crate::Readable for MisSpec {} +#[doc = "`reset()` method sets MIS to value 0"] +impl crate::Resettable for MisSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/gpio0/ris.rs b/rust-embedded/lpc111x-pac/src/gpio0/ris.rs new file mode 100644 index 0000000..873f986 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/gpio0/ris.rs @@ -0,0 +1,99 @@ +#[doc = "Register `RIS` reader"] +pub type R = crate::R; +#[doc = "Field `RAWST0` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst0R = crate::BitReader; +#[doc = "Field `RAWST1` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst1R = crate::BitReader; +#[doc = "Field `RAWST2` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst2R = crate::BitReader; +#[doc = "Field `RAWST3` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst3R = crate::BitReader; +#[doc = "Field `RAWST4` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst4R = crate::BitReader; +#[doc = "Field `RAWST5` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst5R = crate::BitReader; +#[doc = "Field `RAWST6` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst6R = crate::BitReader; +#[doc = "Field `RAWST7` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst7R = crate::BitReader; +#[doc = "Field `RAWST8` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst8R = crate::BitReader; +#[doc = "Field `RAWST9` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst9R = crate::BitReader; +#[doc = "Field `RAWST10` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst10R = crate::BitReader; +#[doc = "Field `RAWST11` reader - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] +pub type Rawst11R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst0(&self) -> Rawst0R { + Rawst0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst1(&self) -> Rawst1R { + Rawst1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst2(&self) -> Rawst2R { + Rawst2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst3(&self) -> Rawst3R { + Rawst3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst4(&self) -> Rawst4R { + Rawst4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst5(&self) -> Rawst5R { + Rawst5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst6(&self) -> Rawst6R { + Rawst6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst7(&self) -> Rawst7R { + Rawst7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst8(&self) -> Rawst8R { + Rawst8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst9(&self) -> Rawst9R { + Rawst9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst10(&self) -> Rawst10R { + Rawst10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x."] + #[inline(always)] + pub fn rawst11(&self) -> Rawst11R { + Rawst11R::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Raw interrupt status register for port n\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RisSpec; +impl crate::RegisterSpec for RisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ris::R`](R) reader structure"] +impl crate::Readable for RisSpec {} +#[doc = "`reset()` method sets RIS to value 0"] +impl crate::Resettable for RisSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c.rs b/rust-embedded/lpc111x-pac/src/i2c.rs new file mode 100644 index 0000000..88c4f1c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c.rs @@ -0,0 +1,161 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + conset: Conset, + stat: Stat, + dat: Dat, + adr0: Adr0, + sclh: Sclh, + scll: Scll, + conclr: Conclr, + mmctrl: Mmctrl, + adr: [Adr; 3], + data_buffer: DataBuffer, + mask: [Mask; 4], +} +impl RegisterBlock { + #[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."] + #[inline(always)] + pub const fn conset(&self) -> &Conset { + &self.conset + } + #[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."] + #[inline(always)] + pub const fn dat(&self) -> &Dat { + &self.dat + } + #[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub const fn adr0(&self) -> &Adr0 { + &self.adr0 + } + #[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."] + #[inline(always)] + pub const fn sclh(&self) -> &Sclh { + &self.sclh + } + #[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."] + #[inline(always)] + pub const fn scll(&self) -> &Scll { + &self.scll + } + #[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."] + #[inline(always)] + pub const fn conclr(&self) -> &Conclr { + &self.conclr + } + #[doc = "0x1c - Monitor mode control register."] + #[inline(always)] + pub const fn mmctrl(&self) -> &Mmctrl { + &self.mmctrl + } + #[doc = "0x20..0x2c - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub const fn adr(&self, n: usize) -> &Adr { + &self.adr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x20..0x2c - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub fn adr_iter(&self) -> impl Iterator { + self.adr.iter() + } + #[doc = "0x20 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub const fn adr1(&self) -> &Adr { + self.adr(0) + } + #[doc = "0x24 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub const fn adr2(&self) -> &Adr { + self.adr(1) + } + #[doc = "0x28 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] + #[inline(always)] + pub const fn adr3(&self) -> &Adr { + self.adr(2) + } + #[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."] + #[inline(always)] + pub const fn data_buffer(&self) -> &DataBuffer { + &self.data_buffer + } + #[doc = "0x30..0x40 - I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."] + #[inline(always)] + pub const fn mask(&self, n: usize) -> &Mask { + &self.mask[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x30..0x40 - I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."] + #[inline(always)] + pub fn mask_iter(&self) -> impl Iterator { + self.mask.iter() + } +} +#[doc = "CONSET (rw) register accessor: I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conset`] +module"] +#[doc(alias = "CONSET")] +pub type Conset = crate::Reg; +#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."] +pub mod conset; +#[doc = "STAT (r) register accessor: I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."] +pub mod stat; +#[doc = "DAT (rw) register accessor: I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dat`] +module"] +#[doc(alias = "DAT")] +pub type Dat = crate::Reg; +#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."] +pub mod dat; +pub use adr as adr0; +pub use Adr as Adr0; +#[doc = "SCLH (rw) register accessor: SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sclh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sclh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sclh`] +module"] +#[doc(alias = "SCLH")] +pub type Sclh = crate::Reg; +#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."] +pub mod sclh; +#[doc = "SCLL (rw) register accessor: SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scll`] +module"] +#[doc(alias = "SCLL")] +pub type Scll = crate::Reg; +#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."] +pub mod scll; +#[doc = "CONCLR (w) register accessor: I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conclr`] +module"] +#[doc(alias = "CONCLR")] +pub type Conclr = crate::Reg; +#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."] +pub mod conclr; +#[doc = "MMCTRL (rw) register accessor: Monitor mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmctrl`] +module"] +#[doc(alias = "MMCTRL")] +pub type Mmctrl = crate::Reg; +#[doc = "Monitor mode control register."] +pub mod mmctrl; +#[doc = "ADR (rw) register accessor: I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adr`] +module"] +#[doc(alias = "ADR")] +pub type Adr = crate::Reg; +#[doc = "I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."] +pub mod adr; +#[doc = "DATA_BUFFER (r) register accessor: Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_buffer`] +module"] +#[doc(alias = "DATA_BUFFER")] +pub type DataBuffer = crate::Reg; +#[doc = "Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."] +pub mod data_buffer; +#[doc = "MASK (rw) register accessor: I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mask`] +module"] +#[doc(alias = "MASK")] +pub type Mask = crate::Reg; +#[doc = "I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."] +pub mod mask; diff --git a/rust-embedded/lpc111x-pac/src/i2c/adr.rs b/rust-embedded/lpc111x-pac/src/i2c/adr.rs new file mode 100644 index 0000000..2937a26 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/adr.rs @@ -0,0 +1,55 @@ +#[doc = "Register `ADR%s` reader"] +pub type R = crate::R; +#[doc = "Register `ADR%s` writer"] +pub type W = crate::W; +#[doc = "Field `GC` reader - General Call enable bit."] +pub type GcR = crate::BitReader; +#[doc = "Field `GC` writer - General Call enable bit."] +pub type GcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `Address` reader - The I2C device address for slave mode."] +pub type AddressR = crate::FieldReader; +#[doc = "Field `Address` writer - The I2C device address for slave mode."] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bit 0 - General Call enable bit."] + #[inline(always)] + pub fn gc(&self) -> GcR { + GcR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:7 - The I2C device address for slave mode."] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bit 0 - General Call enable bit."] + #[inline(always)] + #[must_use] + pub fn gc(&mut self) -> GcW { + GcW::new(self, 0) + } + #[doc = "Bits 1:7 - The I2C device address for slave mode."] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> AddressW { + AddressW::new(self, 1) + } +} +#[doc = "I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AdrSpec; +impl crate::RegisterSpec for AdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adr::R`](R) reader structure"] +impl crate::Readable for AdrSpec {} +#[doc = "`write(|w| ..)` method takes [`adr::W`](W) writer structure"] +impl crate::Writable for AdrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADR%s to value 0"] +impl crate::Resettable for AdrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/conclr.rs b/rust-embedded/lpc111x-pac/src/i2c/conclr.rs new file mode 100644 index 0000000..69e668e --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/conclr.rs @@ -0,0 +1,51 @@ +#[doc = "Register `CONCLR` writer"] +pub type W = crate::W; +#[doc = "Field `AAC` writer - Assert acknowledge Clear bit."] +pub type AacW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIC` writer - I2C interrupt Clear bit."] +pub type SicW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STAC` writer - START flag Clear bit."] +pub type StacW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2ENC` writer - I2C interface Disable bit."] +pub type I2encW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 2 - Assert acknowledge Clear bit."] + #[inline(always)] + #[must_use] + pub fn aac(&mut self) -> AacW { + AacW::new(self, 2) + } + #[doc = "Bit 3 - I2C interrupt Clear bit."] + #[inline(always)] + #[must_use] + pub fn sic(&mut self) -> SicW { + SicW::new(self, 3) + } + #[doc = "Bit 5 - START flag Clear bit."] + #[inline(always)] + #[must_use] + pub fn stac(&mut self) -> StacW { + StacW::new(self, 5) + } + #[doc = "Bit 6 - I2C interface Disable bit."] + #[inline(always)] + #[must_use] + pub fn i2enc(&mut self) -> I2encW { + I2encW::new(self, 6) + } +} +#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConclrSpec; +impl crate::RegisterSpec for ConclrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`conclr::W`](W) writer structure"] +impl crate::Writable for ConclrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONCLR to value 0"] +impl crate::Resettable for ConclrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/conset.rs b/rust-embedded/lpc111x-pac/src/i2c/conset.rs new file mode 100644 index 0000000..ebd1233 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/conset.rs @@ -0,0 +1,100 @@ +#[doc = "Register `CONSET` reader"] +pub type R = crate::R; +#[doc = "Register `CONSET` writer"] +pub type W = crate::W; +#[doc = "Field `AA` reader - Assert acknowledge flag."] +pub type AaR = crate::BitReader; +#[doc = "Field `AA` writer - Assert acknowledge flag."] +pub type AaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SI` reader - I2C interrupt flag."] +pub type SiR = crate::BitReader; +#[doc = "Field `SI` writer - I2C interrupt flag."] +pub type SiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STO` reader - STOP flag."] +pub type StoR = crate::BitReader; +#[doc = "Field `STO` writer - STOP flag."] +pub type StoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STA` reader - START flag."] +pub type StaR = crate::BitReader; +#[doc = "Field `STA` writer - START flag."] +pub type StaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2EN` reader - I2C interface enable."] +pub type I2enR = crate::BitReader; +#[doc = "Field `I2EN` writer - I2C interface enable."] +pub type I2enW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 2 - Assert acknowledge flag."] + #[inline(always)] + pub fn aa(&self) -> AaR { + AaR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - I2C interrupt flag."] + #[inline(always)] + pub fn si(&self) -> SiR { + SiR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - STOP flag."] + #[inline(always)] + pub fn sto(&self) -> StoR { + StoR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - START flag."] + #[inline(always)] + pub fn sta(&self) -> StaR { + StaR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C interface enable."] + #[inline(always)] + pub fn i2en(&self) -> I2enR { + I2enR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Assert acknowledge flag."] + #[inline(always)] + #[must_use] + pub fn aa(&mut self) -> AaW { + AaW::new(self, 2) + } + #[doc = "Bit 3 - I2C interrupt flag."] + #[inline(always)] + #[must_use] + pub fn si(&mut self) -> SiW { + SiW::new(self, 3) + } + #[doc = "Bit 4 - STOP flag."] + #[inline(always)] + #[must_use] + pub fn sto(&mut self) -> StoW { + StoW::new(self, 4) + } + #[doc = "Bit 5 - START flag."] + #[inline(always)] + #[must_use] + pub fn sta(&mut self) -> StaW { + StaW::new(self, 5) + } + #[doc = "Bit 6 - I2C interface enable."] + #[inline(always)] + #[must_use] + pub fn i2en(&mut self) -> I2enW { + I2enW::new(self, 6) + } +} +#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConsetSpec; +impl crate::RegisterSpec for ConsetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`conset::R`](R) reader structure"] +impl crate::Readable for ConsetSpec {} +#[doc = "`write(|w| ..)` method takes [`conset::W`](W) writer structure"] +impl crate::Writable for ConsetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONSET to value 0"] +impl crate::Resettable for ConsetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/dat.rs b/rust-embedded/lpc111x-pac/src/i2c/dat.rs new file mode 100644 index 0000000..3d45ee7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/dat.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DAT` reader"] +pub type R = crate::R; +#[doc = "Register `DAT` writer"] +pub type W = crate::W; +#[doc = "Field `Data` reader - This register holds data values that have been received or are to be transmitted."] +pub type DataR = crate::FieldReader; +#[doc = "Field `Data` writer - This register holds data values that have been received or are to be transmitted."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - This register holds data values that have been received or are to be transmitted."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatSpec; +impl crate::RegisterSpec for DatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dat::R`](R) reader structure"] +impl crate::Readable for DatSpec {} +#[doc = "`write(|w| ..)` method takes [`dat::W`](W) writer structure"] +impl crate::Writable for DatSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DAT to value 0"] +impl crate::Resettable for DatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/data_buffer.rs b/rust-embedded/lpc111x-pac/src/i2c/data_buffer.rs new file mode 100644 index 0000000..d2d2aa3 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/data_buffer.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DATA_BUFFER` reader"] +pub type R = crate::R; +#[doc = "Field `Data` reader - This register holds contents of the 8 MSBs of the DAT shift register."] +pub type DataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - This register holds contents of the 8 MSBs of the DAT shift register."] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_buffer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataBufferSpec; +impl crate::RegisterSpec for DataBufferSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data_buffer::R`](R) reader structure"] +impl crate::Readable for DataBufferSpec {} +#[doc = "`reset()` method sets DATA_BUFFER to value 0"] +impl crate::Resettable for DataBufferSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/mask.rs b/rust-embedded/lpc111x-pac/src/i2c/mask.rs new file mode 100644 index 0000000..4726fd0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/mask.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MASK%s` reader"] +pub type R = crate::R; +#[doc = "Register `MASK%s` writer"] +pub type W = crate::W; +#[doc = "Field `MASK` reader - Mask bits."] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Mask bits."] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 1:7 - Mask bits."] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 1) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 1:7 - Mask bits."] + #[inline(always)] + #[must_use] + pub fn mask(&mut self) -> MaskW { + MaskW::new(self, 1) + } +} +#[doc = "I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MaskSpec; +impl crate::RegisterSpec for MaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mask::R`](R) reader structure"] +impl crate::Readable for MaskSpec {} +#[doc = "`write(|w| ..)` method takes [`mask::W`](W) writer structure"] +impl crate::Writable for MaskSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MASK%s to value 0"] +impl crate::Resettable for MaskSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs b/rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs new file mode 100644 index 0000000..cb12fd6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/mmctrl.rs @@ -0,0 +1,217 @@ +#[doc = "Register `MMCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MMCTRL` writer"] +pub type W = crate::W; +#[doc = "Monitor mode enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MmEna { + #[doc = "0: Monitor mode disabled."] + MonitorModeDisable = 0, + #[doc = "1: The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."] + TheI2cModuleWill_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MmEna) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MM_ENA` reader - Monitor mode enable."] +pub type MmEnaR = crate::BitReader; +impl MmEnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MmEna { + match self.bits { + false => MmEna::MonitorModeDisable, + true => MmEna::TheI2cModuleWill_, + } + } + #[doc = "Monitor mode disabled."] + #[inline(always)] + pub fn is_monitor_mode_disable(&self) -> bool { + *self == MmEna::MonitorModeDisable + } + #[doc = "The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."] + #[inline(always)] + pub fn is_the_i2c_module_will_(&self) -> bool { + *self == MmEna::TheI2cModuleWill_ + } +} +#[doc = "Field `MM_ENA` writer - Monitor mode enable."] +pub type MmEnaW<'a, REG> = crate::BitWriter<'a, REG, MmEna>; +impl<'a, REG> MmEnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Monitor mode disabled."] + #[inline(always)] + pub fn monitor_mode_disable(self) -> &'a mut crate::W { + self.variant(MmEna::MonitorModeDisable) + } + #[doc = "The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line."] + #[inline(always)] + pub fn the_i2c_module_will_(self) -> &'a mut crate::W { + self.variant(MmEna::TheI2cModuleWill_) + } +} +#[doc = "SCL output enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum EnaScl { + #[doc = "0: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."] + High = 0, + #[doc = "1: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"] + Normal = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: EnaScl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA_SCL` reader - SCL output enable."] +pub type EnaSclR = crate::BitReader; +impl EnaSclR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> EnaScl { + match self.bits { + false => EnaScl::High, + true => EnaScl::Normal, + } + } + #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == EnaScl::High + } + #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == EnaScl::Normal + } +} +#[doc = "Field `ENA_SCL` writer - SCL output enable."] +pub type EnaSclW<'a, REG> = crate::BitWriter<'a, REG, EnaScl>; +impl<'a, REG> EnaSclW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line."] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(EnaScl::High) + } + #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.\\[1\\]"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(EnaScl::Normal) + } +} +#[doc = "Select interrupt register match.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MatchAll { + #[doc = "0: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."] + Match = 0, + #[doc = "1: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."] + Anyaddress = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MatchAll) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MATCH_ALL` reader - Select interrupt register match."] +pub type MatchAllR = crate::BitReader; +impl MatchAllR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MatchAll { + match self.bits { + false => MatchAll::Match, + true => MatchAll::Anyaddress, + } + } + #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."] + #[inline(always)] + pub fn is_match(&self) -> bool { + *self == MatchAll::Match + } + #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."] + #[inline(always)] + pub fn is_anyaddress(&self) -> bool { + *self == MatchAll::Anyaddress + } +} +#[doc = "Field `MATCH_ALL` writer - Select interrupt register match."] +pub type MatchAllW<'a, REG> = crate::BitWriter<'a, REG, MatchAll>; +impl<'a, REG> MatchAllW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned."] + #[inline(always)] + pub fn match_(self) -> &'a mut crate::W { + self.variant(MatchAll::Match) + } + #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus."] + #[inline(always)] + pub fn anyaddress(self) -> &'a mut crate::W { + self.variant(MatchAll::Anyaddress) + } +} +impl R { + #[doc = "Bit 0 - Monitor mode enable."] + #[inline(always)] + pub fn mm_ena(&self) -> MmEnaR { + MmEnaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SCL output enable."] + #[inline(always)] + pub fn ena_scl(&self) -> EnaSclR { + EnaSclR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Select interrupt register match."] + #[inline(always)] + pub fn match_all(&self) -> MatchAllR { + MatchAllR::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Monitor mode enable."] + #[inline(always)] + #[must_use] + pub fn mm_ena(&mut self) -> MmEnaW { + MmEnaW::new(self, 0) + } + #[doc = "Bit 1 - SCL output enable."] + #[inline(always)] + #[must_use] + pub fn ena_scl(&mut self) -> EnaSclW { + EnaSclW::new(self, 1) + } + #[doc = "Bit 2 - Select interrupt register match."] + #[inline(always)] + #[must_use] + pub fn match_all(&mut self) -> MatchAllW { + MatchAllW::new(self, 2) + } +} +#[doc = "Monitor mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmctrlSpec; +impl crate::RegisterSpec for MmctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmctrl::R`](R) reader structure"] +impl crate::Readable for MmctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mmctrl::W`](W) writer structure"] +impl crate::Writable for MmctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMCTRL to value 0"] +impl crate::Resettable for MmctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/sclh.rs b/rust-embedded/lpc111x-pac/src/i2c/sclh.rs new file mode 100644 index 0000000..5ce18ed --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/sclh.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SCLH` reader"] +pub type R = crate::R; +#[doc = "Register `SCLH` writer"] +pub type W = crate::W; +#[doc = "Field `SCLH` reader - Count for SCL HIGH time period selection."] +pub type SclhR = crate::FieldReader; +#[doc = "Field `SCLH` writer - Count for SCL HIGH time period selection."] +pub type SclhW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Count for SCL HIGH time period selection."] + #[inline(always)] + pub fn sclh(&self) -> SclhR { + SclhR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Count for SCL HIGH time period selection."] + #[inline(always)] + #[must_use] + pub fn sclh(&mut self) -> SclhW { + SclhW::new(self, 0) + } +} +#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sclh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sclh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SclhSpec; +impl crate::RegisterSpec for SclhSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sclh::R`](R) reader structure"] +impl crate::Readable for SclhSpec {} +#[doc = "`write(|w| ..)` method takes [`sclh::W`](W) writer structure"] +impl crate::Writable for SclhSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCLH to value 0x04"] +impl crate::Resettable for SclhSpec { + const RESET_VALUE: u32 = 0x04; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/scll.rs b/rust-embedded/lpc111x-pac/src/i2c/scll.rs new file mode 100644 index 0000000..2a19201 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/scll.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SCLL` reader"] +pub type R = crate::R; +#[doc = "Register `SCLL` writer"] +pub type W = crate::W; +#[doc = "Field `SCLL` reader - Count for SCL low time period selection."] +pub type ScllR = crate::FieldReader; +#[doc = "Field `SCLL` writer - Count for SCL low time period selection."] +pub type ScllW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Count for SCL low time period selection."] + #[inline(always)] + pub fn scll(&self) -> ScllR { + ScllR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Count for SCL low time period selection."] + #[inline(always)] + #[must_use] + pub fn scll(&mut self) -> ScllW { + ScllW::new(self, 0) + } +} +#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scll::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScllSpec; +impl crate::RegisterSpec for ScllSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scll::R`](R) reader structure"] +impl crate::Readable for ScllSpec {} +#[doc = "`write(|w| ..)` method takes [`scll::W`](W) writer structure"] +impl crate::Writable for ScllSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCLL to value 0x04"] +impl crate::Resettable for ScllSpec { + const RESET_VALUE: u32 = 0x04; +} diff --git a/rust-embedded/lpc111x-pac/src/i2c/stat.rs b/rust-embedded/lpc111x-pac/src/i2c/stat.rs new file mode 100644 index 0000000..a7a2b4c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/i2c/stat.rs @@ -0,0 +1,22 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Field `Status` reader - These bits give the actual status information about the I 2C interface."] +pub type StatusR = crate::FieldReader; +impl R { + #[doc = "Bits 3:7 - These bits give the actual status information about the I 2C interface."] + #[inline(always)] + pub fn status(&self) -> StatusR { + StatusR::new(((self.bits >> 3) & 0x1f) as u8) + } +} +#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`reset()` method sets STAT to value 0xf8"] +impl crate::Resettable for StatSpec { + const RESET_VALUE: u32 = 0xf8; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon.rs b/rust-embedded/lpc111x-pac/src/iocon.rs new file mode 100644 index 0000000..8932d8c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon.rs @@ -0,0 +1,643 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + pio2_6: Pio2_6, + _reserved1: [u8; 0x04], + pio2_0: Pio2_0, + reset_pio0_0: ResetPio0_0, + pio0_1: Pio0_1, + pio1_8: Pio1_8, + ssel1_loc: Ssel1Loc, + pio0_2: Pio0_2, + pio2_7: Pio2_7, + pio2_8: Pio2_8, + pio2_1: Pio2_1, + pio0_3: Pio0_3, + pio0_4: Pio0_4, + pio0_5: Pio0_5, + pio1_9: Pio1_9, + pio3_4: Pio3_4, + pio2_4: Pio2_4, + pio2_5: Pio2_5, + pio3_5: Pio3_5, + pio0_6: Pio0_6, + pio0_7: Pio0_7, + pio2_9: Pio2_9, + pio2_10: Pio2_10, + pio2_2: Pio2_2, + pio0_8: Pio0_8, + pio0_9: Pio0_9, + swclk_pio0_10: SwclkPio0_10, + pio1_10: Pio1_10, + pio2_11: Pio2_11, + r_pio0_11: RPio0_11, + r_pio1_0: RPio1_0, + r_pio1_1: RPio1_1, + r_pio1_2: RPio1_2, + pio3_0: Pio3_0, + pio3_1: Pio3_1, + pio2_3: Pio2_3, + swdio_pio1_3: SwdioPio1_3, + pio1_4: Pio1_4, + pio1_11: Pio1_11, + pio3_2: Pio3_2, + pio1_5: Pio1_5, + pio1_6: Pio1_6, + pio1_7: Pio1_7, + pio3_3: Pio3_3, + sck0_loc: Sck0Loc, + dsr_loc: DsrLoc, + dcd_loc: DcdLoc, + ri_loc: RiLoc, + ct16b0_cap0_loc: Ct16b0Cap0Loc, + sck1_loc: Sck1Loc, + miso1_loc: Miso1Loc, + mosi1_loc: Mosi1Loc, + ct32b0_cap0_loc: Ct32b0Cap0Loc, + rxd_loc: RxdLoc, +} +impl RegisterBlock { + #[doc = "0x00 - I/O configuration for pin PIO2_6/ CT32B0_MAT1"] + #[inline(always)] + pub const fn pio2_6(&self) -> &Pio2_6 { + &self.pio2_6 + } + #[doc = "0x08 - I/O configuration for pin PIO2_0/DTR/SSEL1"] + #[inline(always)] + pub const fn pio2_0(&self) -> &Pio2_0 { + &self.pio2_0 + } + #[doc = "0x0c - I/O configuration for pin RESET/PIO0_0"] + #[inline(always)] + pub const fn reset_pio0_0(&self) -> &ResetPio0_0 { + &self.reset_pio0_0 + } + #[doc = "0x10 - I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2"] + #[inline(always)] + pub const fn pio0_1(&self) -> &Pio0_1 { + &self.pio0_1 + } + #[doc = "0x14 - I/O configuration for pin PIO1_8/CT16B1_CAP0"] + #[inline(always)] + pub const fn pio1_8(&self) -> &Pio1_8 { + &self.pio1_8 + } + #[doc = "0x18 - SSEL1 pin location select register"] + #[inline(always)] + pub const fn ssel1_loc(&self) -> &Ssel1Loc { + &self.ssel1_loc + } + #[doc = "0x1c - I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0"] + #[inline(always)] + pub const fn pio0_2(&self) -> &Pio0_2 { + &self.pio0_2 + } + #[doc = "0x20 - I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD"] + #[inline(always)] + pub const fn pio2_7(&self) -> &Pio2_7 { + &self.pio2_7 + } + #[doc = "0x24 - I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD"] + #[inline(always)] + pub const fn pio2_8(&self) -> &Pio2_8 { + &self.pio2_8 + } + #[doc = "0x28 - I/O configuration for pin PIO2_1/DSR/SCK1"] + #[inline(always)] + pub const fn pio2_1(&self) -> &Pio2_1 { + &self.pio2_1 + } + #[doc = "0x2c - I/O configuration for pin PIO0_3"] + #[inline(always)] + pub const fn pio0_3(&self) -> &Pio0_3 { + &self.pio0_3 + } + #[doc = "0x30 - I/O configuration for pin PIO0_4/SCL"] + #[inline(always)] + pub const fn pio0_4(&self) -> &Pio0_4 { + &self.pio0_4 + } + #[doc = "0x34 - I/O configuration for pin PIO0_5/SDA"] + #[inline(always)] + pub const fn pio0_5(&self) -> &Pio0_5 { + &self.pio0_5 + } + #[doc = "0x38 - I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1"] + #[inline(always)] + pub const fn pio1_9(&self) -> &Pio1_9 { + &self.pio1_9 + } + #[doc = "0x3c - I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD"] + #[inline(always)] + pub const fn pio3_4(&self) -> &Pio3_4 { + &self.pio3_4 + } + #[doc = "0x40 - I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1"] + #[inline(always)] + pub const fn pio2_4(&self) -> &Pio2_4 { + &self.pio2_4 + } + #[doc = "0x44 - I/O configuration for pin PIO2_5/ CT32B0_MAT0"] + #[inline(always)] + pub const fn pio2_5(&self) -> &Pio2_5 { + &self.pio2_5 + } + #[doc = "0x48 - I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD"] + #[inline(always)] + pub const fn pio3_5(&self) -> &Pio3_5 { + &self.pio3_5 + } + #[doc = "0x4c - I/O configuration for pin PIO0_6/SCK0"] + #[inline(always)] + pub const fn pio0_6(&self) -> &Pio0_6 { + &self.pio0_6 + } + #[doc = "0x50 - I/O configuration for pin PIO0_7/CTS"] + #[inline(always)] + pub const fn pio0_7(&self) -> &Pio0_7 { + &self.pio0_7 + } + #[doc = "0x54 - I/O configuration for pin PIO2_9/ CT32B0_CAP0"] + #[inline(always)] + pub const fn pio2_9(&self) -> &Pio2_9 { + &self.pio2_9 + } + #[doc = "0x58 - I/O configuration for pin PIO2_10"] + #[inline(always)] + pub const fn pio2_10(&self) -> &Pio2_10 { + &self.pio2_10 + } + #[doc = "0x5c - I/O configuration for pin PIO2_2/DCD/MISO1"] + #[inline(always)] + pub const fn pio2_2(&self) -> &Pio2_2 { + &self.pio2_2 + } + #[doc = "0x60 - I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0"] + #[inline(always)] + pub const fn pio0_8(&self) -> &Pio0_8 { + &self.pio0_8 + } + #[doc = "0x64 - I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1"] + #[inline(always)] + pub const fn pio0_9(&self) -> &Pio0_9 { + &self.pio0_9 + } + #[doc = "0x68 - I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2"] + #[inline(always)] + pub const fn swclk_pio0_10(&self) -> &SwclkPio0_10 { + &self.swclk_pio0_10 + } + #[doc = "0x6c - I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1"] + #[inline(always)] + pub const fn pio1_10(&self) -> &Pio1_10 { + &self.pio1_10 + } + #[doc = "0x70 - I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1"] + #[inline(always)] + pub const fn pio2_11(&self) -> &Pio2_11 { + &self.pio2_11 + } + #[doc = "0x74 - I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3"] + #[inline(always)] + pub const fn r_pio0_11(&self) -> &RPio0_11 { + &self.r_pio0_11 + } + #[doc = "0x78 - I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0"] + #[inline(always)] + pub const fn r_pio1_0(&self) -> &RPio1_0 { + &self.r_pio1_0 + } + #[doc = "0x7c - I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0"] + #[inline(always)] + pub const fn r_pio1_1(&self) -> &RPio1_1 { + &self.r_pio1_1 + } + #[doc = "0x80 - I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1"] + #[inline(always)] + pub const fn r_pio1_2(&self) -> &RPio1_2 { + &self.r_pio1_2 + } + #[doc = "0x84 - I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD"] + #[inline(always)] + pub const fn pio3_0(&self) -> &Pio3_0 { + &self.pio3_0 + } + #[doc = "0x88 - I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD"] + #[inline(always)] + pub const fn pio3_1(&self) -> &Pio3_1 { + &self.pio3_1 + } + #[doc = "0x8c - I/O configuration for pin PIO2_3/RI/MOSI1"] + #[inline(always)] + pub const fn pio2_3(&self) -> &Pio2_3 { + &self.pio2_3 + } + #[doc = "0x90 - I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2"] + #[inline(always)] + pub const fn swdio_pio1_3(&self) -> &SwdioPio1_3 { + &self.swdio_pio1_3 + } + #[doc = "0x94 - I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3"] + #[inline(always)] + pub const fn pio1_4(&self) -> &Pio1_4 { + &self.pio1_4 + } + #[doc = "0x98 - I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1"] + #[inline(always)] + pub const fn pio1_11(&self) -> &Pio1_11 { + &self.pio1_11 + } + #[doc = "0x9c - I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1"] + #[inline(always)] + pub const fn pio3_2(&self) -> &Pio3_2 { + &self.pio3_2 + } + #[doc = "0xa0 - I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0"] + #[inline(always)] + pub const fn pio1_5(&self) -> &Pio1_5 { + &self.pio1_5 + } + #[doc = "0xa4 - I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0"] + #[inline(always)] + pub const fn pio1_6(&self) -> &Pio1_6 { + &self.pio1_6 + } + #[doc = "0xa8 - I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1"] + #[inline(always)] + pub const fn pio1_7(&self) -> &Pio1_7 { + &self.pio1_7 + } + #[doc = "0xac - I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0"] + #[inline(always)] + pub const fn pio3_3(&self) -> &Pio3_3 { + &self.pio3_3 + } + #[doc = "0xb0 - SCK0 pin location select register"] + #[inline(always)] + pub const fn sck0_loc(&self) -> &Sck0Loc { + &self.sck0_loc + } + #[doc = "0xb4 - DSR pin location select register"] + #[inline(always)] + pub const fn dsr_loc(&self) -> &DsrLoc { + &self.dsr_loc + } + #[doc = "0xb8 - DCD pin location select register"] + #[inline(always)] + pub const fn dcd_loc(&self) -> &DcdLoc { + &self.dcd_loc + } + #[doc = "0xbc - RI pin location select register"] + #[inline(always)] + pub const fn ri_loc(&self) -> &RiLoc { + &self.ri_loc + } + #[doc = "0xc0 - CT16B0_CAP0 pin location select register"] + #[inline(always)] + pub const fn ct16b0_cap0_loc(&self) -> &Ct16b0Cap0Loc { + &self.ct16b0_cap0_loc + } + #[doc = "0xc4 - SCK1 pin location select register"] + #[inline(always)] + pub const fn sck1_loc(&self) -> &Sck1Loc { + &self.sck1_loc + } + #[doc = "0xc8 - MISO1 pin location select register"] + #[inline(always)] + pub const fn miso1_loc(&self) -> &Miso1Loc { + &self.miso1_loc + } + #[doc = "0xcc - MOSI1 pin location select register"] + #[inline(always)] + pub const fn mosi1_loc(&self) -> &Mosi1Loc { + &self.mosi1_loc + } + #[doc = "0xd0 - CT32B0_CAP0 pin location select register"] + #[inline(always)] + pub const fn ct32b0_cap0_loc(&self) -> &Ct32b0Cap0Loc { + &self.ct32b0_cap0_loc + } + #[doc = "0xd4 - RXD pin location select register"] + #[inline(always)] + pub const fn rxd_loc(&self) -> &RxdLoc { + &self.rxd_loc + } +} +#[doc = "PIO2_6 (rw) register accessor: I/O configuration for pin PIO2_6/ CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_6`] +module"] +#[doc(alias = "PIO2_6")] +pub type Pio2_6 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_6/ CT32B0_MAT1"] +pub mod pio2_6; +#[doc = "PIO2_0 (rw) register accessor: I/O configuration for pin PIO2_0/DTR/SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_0`] +module"] +#[doc(alias = "PIO2_0")] +pub type Pio2_0 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_0/DTR/SSEL1"] +pub mod pio2_0; +#[doc = "RESET_PIO0_0 (rw) register accessor: I/O configuration for pin RESET/PIO0_0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_pio0_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_pio0_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_pio0_0`] +module"] +#[doc(alias = "RESET_PIO0_0")] +pub type ResetPio0_0 = crate::Reg; +#[doc = "I/O configuration for pin RESET/PIO0_0"] +pub mod reset_pio0_0; +#[doc = "PIO0_1 (rw) register accessor: I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_1`] +module"] +#[doc(alias = "PIO0_1")] +pub type Pio0_1 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2"] +pub mod pio0_1; +#[doc = "PIO1_8 (rw) register accessor: I/O configuration for pin PIO1_8/CT16B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_8`] +module"] +#[doc(alias = "PIO1_8")] +pub type Pio1_8 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_8/CT16B1_CAP0"] +pub mod pio1_8; +#[doc = "PIO0_2 (rw) register accessor: I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_2`] +module"] +#[doc(alias = "PIO0_2")] +pub type Pio0_2 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0"] +pub mod pio0_2; +#[doc = "PIO2_7 (rw) register accessor: I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_7`] +module"] +#[doc(alias = "PIO2_7")] +pub type Pio2_7 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD"] +pub mod pio2_7; +#[doc = "PIO2_8 (rw) register accessor: I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_8`] +module"] +#[doc(alias = "PIO2_8")] +pub type Pio2_8 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD"] +pub mod pio2_8; +#[doc = "PIO2_1 (rw) register accessor: I/O configuration for pin PIO2_1/DSR/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_1`] +module"] +#[doc(alias = "PIO2_1")] +pub type Pio2_1 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_1/DSR/SCK1"] +pub mod pio2_1; +#[doc = "PIO0_3 (rw) register accessor: I/O configuration for pin PIO0_3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_3`] +module"] +#[doc(alias = "PIO0_3")] +pub type Pio0_3 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_3"] +pub mod pio0_3; +#[doc = "PIO0_4 (rw) register accessor: I/O configuration for pin PIO0_4/SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_4`] +module"] +#[doc(alias = "PIO0_4")] +pub type Pio0_4 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_4/SCL"] +pub mod pio0_4; +#[doc = "PIO0_5 (rw) register accessor: I/O configuration for pin PIO0_5/SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_5`] +module"] +#[doc(alias = "PIO0_5")] +pub type Pio0_5 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_5/SDA"] +pub mod pio0_5; +#[doc = "PIO1_9 (rw) register accessor: I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_9`] +module"] +#[doc(alias = "PIO1_9")] +pub type Pio1_9 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1"] +pub mod pio1_9; +#[doc = "PIO3_4 (rw) register accessor: I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_4`] +module"] +#[doc(alias = "PIO3_4")] +pub type Pio3_4 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD"] +pub mod pio3_4; +#[doc = "PIO2_4 (rw) register accessor: I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_4`] +module"] +#[doc(alias = "PIO2_4")] +pub type Pio2_4 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1"] +pub mod pio2_4; +#[doc = "PIO2_5 (rw) register accessor: I/O configuration for pin PIO2_5/ CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_5`] +module"] +#[doc(alias = "PIO2_5")] +pub type Pio2_5 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_5/ CT32B0_MAT0"] +pub mod pio2_5; +#[doc = "PIO3_5 (rw) register accessor: I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_5`] +module"] +#[doc(alias = "PIO3_5")] +pub type Pio3_5 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD"] +pub mod pio3_5; +#[doc = "PIO0_6 (rw) register accessor: I/O configuration for pin PIO0_6/SCK0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_6`] +module"] +#[doc(alias = "PIO0_6")] +pub type Pio0_6 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_6/SCK0"] +pub mod pio0_6; +#[doc = "PIO0_7 (rw) register accessor: I/O configuration for pin PIO0_7/CTS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_7`] +module"] +#[doc(alias = "PIO0_7")] +pub type Pio0_7 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_7/CTS"] +pub mod pio0_7; +#[doc = "PIO2_9 (rw) register accessor: I/O configuration for pin PIO2_9/ CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_9`] +module"] +#[doc(alias = "PIO2_9")] +pub type Pio2_9 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_9/ CT32B0_CAP0"] +pub mod pio2_9; +#[doc = "PIO2_10 (rw) register accessor: I/O configuration for pin PIO2_10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_10`] +module"] +#[doc(alias = "PIO2_10")] +pub type Pio2_10 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_10"] +pub mod pio2_10; +#[doc = "PIO2_2 (rw) register accessor: I/O configuration for pin PIO2_2/DCD/MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_2`] +module"] +#[doc(alias = "PIO2_2")] +pub type Pio2_2 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_2/DCD/MISO1"] +pub mod pio2_2; +#[doc = "PIO0_8 (rw) register accessor: I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_8`] +module"] +#[doc(alias = "PIO0_8")] +pub type Pio0_8 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0"] +pub mod pio0_8; +#[doc = "PIO0_9 (rw) register accessor: I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio0_9`] +module"] +#[doc(alias = "PIO0_9")] +pub type Pio0_9 = crate::Reg; +#[doc = "I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1"] +pub mod pio0_9; +#[doc = "SWCLK_PIO0_10 (rw) register accessor: I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swclk_pio0_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk_pio0_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swclk_pio0_10`] +module"] +#[doc(alias = "SWCLK_PIO0_10")] +pub type SwclkPio0_10 = crate::Reg; +#[doc = "I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2"] +pub mod swclk_pio0_10; +#[doc = "PIO1_10 (rw) register accessor: I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_10`] +module"] +#[doc(alias = "PIO1_10")] +pub type Pio1_10 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1"] +pub mod pio1_10; +#[doc = "PIO2_11 (rw) register accessor: I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_11`] +module"] +#[doc(alias = "PIO2_11")] +pub type Pio2_11 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1"] +pub mod pio2_11; +#[doc = "R_PIO0_11 (rw) register accessor: I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio0_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio0_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio0_11`] +module"] +#[doc(alias = "R_PIO0_11")] +pub type RPio0_11 = crate::Reg; +#[doc = "I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3"] +pub mod r_pio0_11; +#[doc = "R_PIO1_0 (rw) register accessor: I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_0`] +module"] +#[doc(alias = "R_PIO1_0")] +pub type RPio1_0 = crate::Reg; +#[doc = "I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0"] +pub mod r_pio1_0; +#[doc = "R_PIO1_1 (rw) register accessor: I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_1`] +module"] +#[doc(alias = "R_PIO1_1")] +pub type RPio1_1 = crate::Reg; +#[doc = "I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0"] +pub mod r_pio1_1; +#[doc = "R_PIO1_2 (rw) register accessor: I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r_pio1_2`] +module"] +#[doc(alias = "R_PIO1_2")] +pub type RPio1_2 = crate::Reg; +#[doc = "I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1"] +pub mod r_pio1_2; +#[doc = "PIO3_0 (rw) register accessor: I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_0`] +module"] +#[doc(alias = "PIO3_0")] +pub type Pio3_0 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD"] +pub mod pio3_0; +#[doc = "PIO3_1 (rw) register accessor: I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_1`] +module"] +#[doc(alias = "PIO3_1")] +pub type Pio3_1 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD"] +pub mod pio3_1; +#[doc = "PIO2_3 (rw) register accessor: I/O configuration for pin PIO2_3/RI/MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio2_3`] +module"] +#[doc(alias = "PIO2_3")] +pub type Pio2_3 = crate::Reg; +#[doc = "I/O configuration for pin PIO2_3/RI/MOSI1"] +pub mod pio2_3; +#[doc = "SWDIO_PIO1_3 (rw) register accessor: I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swdio_pio1_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swdio_pio1_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdio_pio1_3`] +module"] +#[doc(alias = "SWDIO_PIO1_3")] +pub type SwdioPio1_3 = crate::Reg; +#[doc = "I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2"] +pub mod swdio_pio1_3; +#[doc = "PIO1_4 (rw) register accessor: I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_4`] +module"] +#[doc(alias = "PIO1_4")] +pub type Pio1_4 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3"] +pub mod pio1_4; +#[doc = "PIO1_11 (rw) register accessor: I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_11`] +module"] +#[doc(alias = "PIO1_11")] +pub type Pio1_11 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1"] +pub mod pio1_11; +#[doc = "PIO3_2 (rw) register accessor: I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_2`] +module"] +#[doc(alias = "PIO3_2")] +pub type Pio3_2 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1"] +pub mod pio3_2; +#[doc = "PIO1_5 (rw) register accessor: I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_5`] +module"] +#[doc(alias = "PIO1_5")] +pub type Pio1_5 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0"] +pub mod pio1_5; +#[doc = "PIO1_6 (rw) register accessor: I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_6`] +module"] +#[doc(alias = "PIO1_6")] +pub type Pio1_6 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0"] +pub mod pio1_6; +#[doc = "PIO1_7 (rw) register accessor: I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio1_7`] +module"] +#[doc(alias = "PIO1_7")] +pub type Pio1_7 = crate::Reg; +#[doc = "I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1"] +pub mod pio1_7; +#[doc = "PIO3_3 (rw) register accessor: I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pio3_3`] +module"] +#[doc(alias = "PIO3_3")] +pub type Pio3_3 = crate::Reg; +#[doc = "I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0"] +pub mod pio3_3; +#[doc = "SCK0_LOC (rw) register accessor: SCK0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sck0_loc`] +module"] +#[doc(alias = "SCK0_LOC")] +pub type Sck0Loc = crate::Reg; +#[doc = "SCK0 pin location select register"] +pub mod sck0_loc; +#[doc = "DSR_LOC (rw) register accessor: DSR pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsr_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsr_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsr_loc`] +module"] +#[doc(alias = "DSR_LOC")] +pub type DsrLoc = crate::Reg; +#[doc = "DSR pin location select register"] +pub mod dsr_loc; +#[doc = "DCD_LOC (rw) register accessor: DCD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcd_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcd_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcd_loc`] +module"] +#[doc(alias = "DCD_LOC")] +pub type DcdLoc = crate::Reg; +#[doc = "DCD pin location select register"] +pub mod dcd_loc; +#[doc = "RI_LOC (rw) register accessor: RI pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ri_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ri_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ri_loc`] +module"] +#[doc(alias = "RI_LOC")] +pub type RiLoc = crate::Reg; +#[doc = "RI pin location select register"] +pub mod ri_loc; +#[doc = "SSEL1_LOC (rw) register accessor: SSEL1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssel1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssel1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssel1_loc`] +module"] +#[doc(alias = "SSEL1_LOC")] +pub type Ssel1Loc = crate::Reg; +#[doc = "SSEL1 pin location select register"] +pub mod ssel1_loc; +#[doc = "CT16B0_CAP0_LOC (rw) register accessor: CT16B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct16b0_cap0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct16b0_cap0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct16b0_cap0_loc`] +module"] +#[doc(alias = "CT16B0_CAP0_LOC")] +pub type Ct16b0Cap0Loc = crate::Reg; +#[doc = "CT16B0_CAP0 pin location select register"] +pub mod ct16b0_cap0_loc; +#[doc = "SCK1_LOC (rw) register accessor: SCK1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sck1_loc`] +module"] +#[doc(alias = "SCK1_LOC")] +pub type Sck1Loc = crate::Reg; +#[doc = "SCK1 pin location select register"] +pub mod sck1_loc; +#[doc = "MISO1_LOC (rw) register accessor: MISO1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miso1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miso1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@miso1_loc`] +module"] +#[doc(alias = "MISO1_LOC")] +pub type Miso1Loc = crate::Reg; +#[doc = "MISO1 pin location select register"] +pub mod miso1_loc; +#[doc = "MOSI1_LOC (rw) register accessor: MOSI1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mosi1_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mosi1_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mosi1_loc`] +module"] +#[doc(alias = "MOSI1_LOC")] +pub type Mosi1Loc = crate::Reg; +#[doc = "MOSI1 pin location select register"] +pub mod mosi1_loc; +#[doc = "CT32B0_CAP0_LOC (rw) register accessor: CT32B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct32b0_cap0_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct32b0_cap0_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ct32b0_cap0_loc`] +module"] +#[doc(alias = "CT32B0_CAP0_LOC")] +pub type Ct32b0Cap0Loc = crate::Reg; +#[doc = "CT32B0_CAP0 pin location select register"] +pub mod ct32b0_cap0_loc; +#[doc = "RXD_LOC (rw) register accessor: RXD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_loc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxd_loc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxd_loc`] +module"] +#[doc(alias = "RXD_LOC")] +pub type RxdLoc = crate::Reg; +#[doc = "RXD pin location select register"] +pub mod rxd_loc; diff --git a/rust-embedded/lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs new file mode 100644 index 0000000..1a58f08 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/ct16b0_cap0_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CT16B0_CAP0_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `CT16B0_CAP0_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for CT16B0_CAP0 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ct16b0Cap0loc { + #[doc = "0: `0`"] + Pio0_2 = 0, + #[doc = "1: `1`"] + Pio3_3 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ct16b0Cap0loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ct16b0Cap0loc { + type Ux = u8; +} +#[doc = "Field `CT16B0_CAP0LOC` reader - Selects pin location for CT16B0_CAP0 function."] +pub type Ct16b0Cap0locR = crate::FieldReader; +impl Ct16b0Cap0locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ct16b0Cap0loc::Pio0_2), + 1 => Some(Ct16b0Cap0loc::Pio3_3), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio0_2(&self) -> bool { + *self == Ct16b0Cap0loc::Pio0_2 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_3(&self) -> bool { + *self == Ct16b0Cap0loc::Pio3_3 + } +} +#[doc = "Field `CT16B0_CAP0LOC` writer - Selects pin location for CT16B0_CAP0 function."] +pub type Ct16b0Cap0locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ct16b0Cap0loc>; +impl<'a, REG> Ct16b0Cap0locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio0_2(self) -> &'a mut crate::W { + self.variant(Ct16b0Cap0loc::Pio0_2) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_3(self) -> &'a mut crate::W { + self.variant(Ct16b0Cap0loc::Pio3_3) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for CT16B0_CAP0 function."] + #[inline(always)] + pub fn ct16b0_cap0loc(&self) -> Ct16b0Cap0locR { + Ct16b0Cap0locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for CT16B0_CAP0 function."] + #[inline(always)] + #[must_use] + pub fn ct16b0_cap0loc(&mut self) -> Ct16b0Cap0locW { + Ct16b0Cap0locW::new(self, 0) + } +} +#[doc = "CT16B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct16b0_cap0_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct16b0_cap0_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ct16b0Cap0LocSpec; +impl crate::RegisterSpec for Ct16b0Cap0LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ct16b0_cap0_loc::R`](R) reader structure"] +impl crate::Readable for Ct16b0Cap0LocSpec {} +#[doc = "`write(|w| ..)` method takes [`ct16b0_cap0_loc::W`](W) writer structure"] +impl crate::Writable for Ct16b0Cap0LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CT16B0_CAP0_LOC to value 0"] +impl crate::Resettable for Ct16b0Cap0LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs new file mode 100644 index 0000000..9e7eb17 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/ct32b0_cap0_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CT32B0_CAP0_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `CT32B0_CAP0_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for the CT32B0_CAP0 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ct32b0Cap0loc { + #[doc = "0: `0`"] + Pio1_5 = 0, + #[doc = "1: `1`"] + Pio2_9 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ct32b0Cap0loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ct32b0Cap0loc { + type Ux = u8; +} +#[doc = "Field `CT32B0_CAP0LOC` reader - Selects pin location for the CT32B0_CAP0 function."] +pub type Ct32b0Cap0locR = crate::FieldReader; +impl Ct32b0Cap0locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ct32b0Cap0loc::Pio1_5), + 1 => Some(Ct32b0Cap0loc::Pio2_9), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio1_5(&self) -> bool { + *self == Ct32b0Cap0loc::Pio1_5 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio2_9(&self) -> bool { + *self == Ct32b0Cap0loc::Pio2_9 + } +} +#[doc = "Field `CT32B0_CAP0LOC` writer - Selects pin location for the CT32B0_CAP0 function."] +pub type Ct32b0Cap0locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ct32b0Cap0loc>; +impl<'a, REG> Ct32b0Cap0locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio1_5(self) -> &'a mut crate::W { + self.variant(Ct32b0Cap0loc::Pio1_5) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio2_9(self) -> &'a mut crate::W { + self.variant(Ct32b0Cap0loc::Pio2_9) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for the CT32B0_CAP0 function."] + #[inline(always)] + pub fn ct32b0_cap0loc(&self) -> Ct32b0Cap0locR { + Ct32b0Cap0locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for the CT32B0_CAP0 function."] + #[inline(always)] + #[must_use] + pub fn ct32b0_cap0loc(&mut self) -> Ct32b0Cap0locW { + Ct32b0Cap0locW::new(self, 0) + } +} +#[doc = "CT32B0_CAP0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ct32b0_cap0_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ct32b0_cap0_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ct32b0Cap0LocSpec; +impl crate::RegisterSpec for Ct32b0Cap0LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ct32b0_cap0_loc::R`](R) reader structure"] +impl crate::Readable for Ct32b0Cap0LocSpec {} +#[doc = "`write(|w| ..)` method takes [`ct32b0_cap0_loc::W`](W) writer structure"] +impl crate::Writable for Ct32b0Cap0LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CT32B0_CAP0_LOC to value 0"] +impl crate::Resettable for Ct32b0Cap0LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/dcd_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/dcd_loc.rs new file mode 100644 index 0000000..c41ba90 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/dcd_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DCD_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DCD_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for DCD function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dcdloc { + #[doc = "0: `0`"] + Pio2_2 = 0, + #[doc = "1: `1`"] + Pio3_2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dcdloc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dcdloc { + type Ux = u8; +} +#[doc = "Field `DCDLOC` reader - Selects pin location for DCD function."] +pub type DcdlocR = crate::FieldReader; +impl DcdlocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dcdloc::Pio2_2), + 1 => Some(Dcdloc::Pio3_2), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_2(&self) -> bool { + *self == Dcdloc::Pio2_2 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_2(&self) -> bool { + *self == Dcdloc::Pio3_2 + } +} +#[doc = "Field `DCDLOC` writer - Selects pin location for DCD function."] +pub type DcdlocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dcdloc>; +impl<'a, REG> DcdlocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_2(self) -> &'a mut crate::W { + self.variant(Dcdloc::Pio2_2) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_2(self) -> &'a mut crate::W { + self.variant(Dcdloc::Pio3_2) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for DCD function."] + #[inline(always)] + pub fn dcdloc(&self) -> DcdlocR { + DcdlocR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for DCD function."] + #[inline(always)] + #[must_use] + pub fn dcdloc(&mut self) -> DcdlocW { + DcdlocW::new(self, 0) + } +} +#[doc = "DCD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcd_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcd_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DcdLocSpec; +impl crate::RegisterSpec for DcdLocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcd_loc::R`](R) reader structure"] +impl crate::Readable for DcdLocSpec {} +#[doc = "`write(|w| ..)` method takes [`dcd_loc::W`](W) writer structure"] +impl crate::Writable for DcdLocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCD_LOC to value 0"] +impl crate::Resettable for DcdLocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/dsr_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/dsr_loc.rs new file mode 100644 index 0000000..33d32fb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/dsr_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DSR_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `DSR_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for DSR function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dsrloc { + #[doc = "0: `0`"] + Pio2_1 = 0, + #[doc = "1: `1`"] + Pio3_1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dsrloc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dsrloc { + type Ux = u8; +} +#[doc = "Field `DSRLOC` reader - Selects pin location for DSR function."] +pub type DsrlocR = crate::FieldReader; +impl DsrlocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Dsrloc::Pio2_1), + 1 => Some(Dsrloc::Pio3_1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_1(&self) -> bool { + *self == Dsrloc::Pio2_1 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_1(&self) -> bool { + *self == Dsrloc::Pio3_1 + } +} +#[doc = "Field `DSRLOC` writer - Selects pin location for DSR function."] +pub type DsrlocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dsrloc>; +impl<'a, REG> DsrlocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_1(self) -> &'a mut crate::W { + self.variant(Dsrloc::Pio2_1) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_1(self) -> &'a mut crate::W { + self.variant(Dsrloc::Pio3_1) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for DSR function."] + #[inline(always)] + pub fn dsrloc(&self) -> DsrlocR { + DsrlocR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for DSR function."] + #[inline(always)] + #[must_use] + pub fn dsrloc(&mut self) -> DsrlocW { + DsrlocW::new(self, 0) + } +} +#[doc = "DSR pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsr_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsr_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DsrLocSpec; +impl crate::RegisterSpec for DsrLocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dsr_loc::R`](R) reader structure"] +impl crate::Readable for DsrLocSpec {} +#[doc = "`write(|w| ..)` method takes [`dsr_loc::W`](W) writer structure"] +impl crate::Writable for DsrLocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DSR_LOC to value 0"] +impl crate::Resettable for DsrLocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/miso1_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/miso1_loc.rs new file mode 100644 index 0000000..3d3fb7b --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/miso1_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `MISO1_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `MISO1_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for the MISO1 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Miso1loc { + #[doc = "0: `0`"] + Pio2_2 = 0, + #[doc = "1: `1`"] + Pio1_10 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Miso1loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Miso1loc { + type Ux = u8; +} +#[doc = "Field `MISO1LOC` reader - Selects pin location for the MISO1 function."] +pub type Miso1locR = crate::FieldReader; +impl Miso1locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Miso1loc::Pio2_2), + 1 => Some(Miso1loc::Pio1_10), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_2(&self) -> bool { + *self == Miso1loc::Pio2_2 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio1_10(&self) -> bool { + *self == Miso1loc::Pio1_10 + } +} +#[doc = "Field `MISO1LOC` writer - Selects pin location for the MISO1 function."] +pub type Miso1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Miso1loc>; +impl<'a, REG> Miso1locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_2(self) -> &'a mut crate::W { + self.variant(Miso1loc::Pio2_2) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio1_10(self) -> &'a mut crate::W { + self.variant(Miso1loc::Pio1_10) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for the MISO1 function."] + #[inline(always)] + pub fn miso1loc(&self) -> Miso1locR { + Miso1locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for the MISO1 function."] + #[inline(always)] + #[must_use] + pub fn miso1loc(&mut self) -> Miso1locW { + Miso1locW::new(self, 0) + } +} +#[doc = "MISO1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`miso1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`miso1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Miso1LocSpec; +impl crate::RegisterSpec for Miso1LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`miso1_loc::R`](R) reader structure"] +impl crate::Readable for Miso1LocSpec {} +#[doc = "`write(|w| ..)` method takes [`miso1_loc::W`](W) writer structure"] +impl crate::Writable for Miso1LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MISO1_LOC to value 0"] +impl crate::Resettable for Miso1LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/mosi1_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/mosi1_loc.rs new file mode 100644 index 0000000..2fbb011 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/mosi1_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `MOSI1_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `MOSI1_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for the MOSI1 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mosi1loc { + #[doc = "0: `0`"] + Pio2_3 = 0, + #[doc = "1: `1`"] + Pio1_9 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mosi1loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mosi1loc { + type Ux = u8; +} +#[doc = "Field `MOSI1LOC` reader - Selects pin location for the MOSI1 function."] +pub type Mosi1locR = crate::FieldReader; +impl Mosi1locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Mosi1loc::Pio2_3), + 1 => Some(Mosi1loc::Pio1_9), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_3(&self) -> bool { + *self == Mosi1loc::Pio2_3 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio1_9(&self) -> bool { + *self == Mosi1loc::Pio1_9 + } +} +#[doc = "Field `MOSI1LOC` writer - Selects pin location for the MOSI1 function."] +pub type Mosi1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mosi1loc>; +impl<'a, REG> Mosi1locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_3(self) -> &'a mut crate::W { + self.variant(Mosi1loc::Pio2_3) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio1_9(self) -> &'a mut crate::W { + self.variant(Mosi1loc::Pio1_9) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for the MOSI1 function."] + #[inline(always)] + pub fn mosi1loc(&self) -> Mosi1locR { + Mosi1locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for the MOSI1 function."] + #[inline(always)] + #[must_use] + pub fn mosi1loc(&mut self) -> Mosi1locW { + Mosi1locW::new(self, 0) + } +} +#[doc = "MOSI1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mosi1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mosi1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Mosi1LocSpec; +impl crate::RegisterSpec for Mosi1LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mosi1_loc::R`](R) reader structure"] +impl crate::Readable for Mosi1LocSpec {} +#[doc = "`write(|w| ..)` method takes [`mosi1_loc::W`](W) writer structure"] +impl crate::Writable for Mosi1LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MOSI1_LOC to value 0"] +impl crate::Resettable for Mosi1LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs new file mode 100644 index 0000000..7330640 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_1.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO0_1` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_1` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_1."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CLKOUT."] + SelectsFunctionClk = 1, + #[doc = "2: Selects function CT32B0_MAT2."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionClk), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO0_1."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CLKOUT."] + #[inline(always)] + pub fn is_selects_function_clk(&self) -> bool { + *self == Func::SelectsFunctionClk + } + #[doc = "Selects function CT32B0_MAT2."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_1."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CLKOUT."] + #[inline(always)] + pub fn selects_function_clk(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionClk) + } + #[doc = "Selects function CT32B0_MAT2."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_1Spec; +impl crate::RegisterSpec for Pio0_1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_1::R`](R) reader structure"] +impl crate::Readable for Pio0_1Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_1::W`](W) writer structure"] +impl crate::Writable for Pio0_1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_1 to value 0xd0"] +impl crate::Resettable for Pio0_1Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs new file mode 100644 index 0000000..d44a4ae --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_2.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO0_2` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_2` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_2."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function SSEL0."] + SelectsFunctionSse = 1, + #[doc = "2: Selects function CT16B0_CAP0."] + SelectsFunctionCt1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionSse), + 2 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function PIO0_2."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function SSEL0."] + #[inline(always)] + pub fn is_selects_function_sse(&self) -> bool { + *self == Func::SelectsFunctionSse + } + #[doc = "Selects function CT16B0_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_2."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function SSEL0."] + #[inline(always)] + pub fn selects_function_sse(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSse) + } + #[doc = "Selects function CT16B0_CAP0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_2Spec; +impl crate::RegisterSpec for Pio0_2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_2::R`](R) reader structure"] +impl crate::Readable for Pio0_2Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_2::W`](W) writer structure"] +impl crate::Writable for Pio0_2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_2 to value 0xd0"] +impl crate::Resettable for Pio0_2Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs new file mode 100644 index 0000000..2076670 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_3.rs @@ -0,0 +1,306 @@ +#[doc = "Register `PIO0_3` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_3` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_3."] + SelectsFunctionPio = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + _ => None, + } + } + #[doc = "Selects function PIO0_3."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_3."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_3Spec; +impl crate::RegisterSpec for Pio0_3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_3::R`](R) reader structure"] +impl crate::Readable for Pio0_3Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_3::W`](W) writer structure"] +impl crate::Writable for Pio0_3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_3 to value 0xd0"] +impl crate::Resettable for Pio0_3Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs new file mode 100644 index 0000000..b9d6ce5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_4.rs @@ -0,0 +1,178 @@ +#[doc = "Register `PIO0_4` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_4` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_4 (open-drain pin)."] + SelectsFunctionPio = 0, + #[doc = "1: Selects I2C function SCL (open-drain pin)."] + SelectsI2cFunction = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsI2cFunction), + _ => None, + } + } + #[doc = "Selects function PIO0_4 (open-drain pin)."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects I2C function SCL (open-drain pin)."] + #[inline(always)] + pub fn is_selects_i2c_function(&self) -> bool { + *self == Func::SelectsI2cFunction + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_4 (open-drain pin)."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects I2C function SCL (open-drain pin)."] + #[inline(always)] + pub fn selects_i2c_function(self) -> &'a mut crate::W { + self.variant(Func::SelectsI2cFunction) + } +} +#[doc = "Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum I2cmode { + #[doc = "0: Standard mode/Fast-mode I2C"] + StandardI2c = 0, + #[doc = "1: Standard I/O"] + StandardIo = 1, + #[doc = "2: Fast-mode Plus I2C"] + FastPlusI2c = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: I2cmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for I2cmode { + type Ux = u8; +} +#[doc = "Field `I2CMODE` reader - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] +pub type I2cmodeR = crate::FieldReader; +impl I2cmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(I2cmode::StandardI2c), + 1 => Some(I2cmode::StandardIo), + 2 => Some(I2cmode::FastPlusI2c), + _ => None, + } + } + #[doc = "Standard mode/Fast-mode I2C"] + #[inline(always)] + pub fn is_standard_i2c(&self) -> bool { + *self == I2cmode::StandardI2c + } + #[doc = "Standard I/O"] + #[inline(always)] + pub fn is_standard_io(&self) -> bool { + *self == I2cmode::StandardIo + } + #[doc = "Fast-mode Plus I2C"] + #[inline(always)] + pub fn is_fast_plus_i2c(&self) -> bool { + *self == I2cmode::FastPlusI2c + } +} +#[doc = "Field `I2CMODE` writer - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] +pub type I2cmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, I2cmode>; +impl<'a, REG> I2cmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Standard mode/Fast-mode I2C"] + #[inline(always)] + pub fn standard_i2c(self) -> &'a mut crate::W { + self.variant(I2cmode::StandardI2c) + } + #[doc = "Standard I/O"] + #[inline(always)] + pub fn standard_io(self) -> &'a mut crate::W { + self.variant(I2cmode::StandardIo) + } + #[doc = "Fast-mode Plus I2C"] + #[inline(always)] + pub fn fast_plus_i2c(self) -> &'a mut crate::W { + self.variant(I2cmode::FastPlusI2c) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] + #[inline(always)] + pub fn i2cmode(&self) -> I2cmodeR { + I2cmodeR::new(((self.bits >> 8) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] + #[inline(always)] + #[must_use] + pub fn i2cmode(&mut self) -> I2cmodeW { + I2cmodeW::new(self, 8) + } +} +#[doc = "I/O configuration for pin PIO0_4/SCL\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_4Spec; +impl crate::RegisterSpec for Pio0_4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_4::R`](R) reader structure"] +impl crate::Readable for Pio0_4Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_4::W`](W) writer structure"] +impl crate::Writable for Pio0_4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_4 to value 0"] +impl crate::Resettable for Pio0_4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs new file mode 100644 index 0000000..afd0ec2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_5.rs @@ -0,0 +1,178 @@ +#[doc = "Register `PIO0_5` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_5` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_5 (open-drain pin)."] + SelectsFunctionPio = 0, + #[doc = "1: Selects I2C function SDA (open-drain pin)."] + SelectsI2cFunction = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsI2cFunction), + _ => None, + } + } + #[doc = "Selects function PIO0_5 (open-drain pin)."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects I2C function SDA (open-drain pin)."] + #[inline(always)] + pub fn is_selects_i2c_function(&self) -> bool { + *self == Func::SelectsI2cFunction + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_5 (open-drain pin)."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects I2C function SDA (open-drain pin)."] + #[inline(always)] + pub fn selects_i2c_function(self) -> &'a mut crate::W { + self.variant(Func::SelectsI2cFunction) + } +} +#[doc = "Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum I2cmode { + #[doc = "0: Standard mode/Fast-mode I2C"] + StandardI2c = 0, + #[doc = "1: Standard I/O"] + StandardIo = 1, + #[doc = "2: Fast-mode Plus I2C"] + FastPlusI2c = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: I2cmode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for I2cmode { + type Ux = u8; +} +#[doc = "Field `I2CMODE` reader - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] +pub type I2cmodeR = crate::FieldReader; +impl I2cmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(I2cmode::StandardI2c), + 1 => Some(I2cmode::StandardIo), + 2 => Some(I2cmode::FastPlusI2c), + _ => None, + } + } + #[doc = "Standard mode/Fast-mode I2C"] + #[inline(always)] + pub fn is_standard_i2c(&self) -> bool { + *self == I2cmode::StandardI2c + } + #[doc = "Standard I/O"] + #[inline(always)] + pub fn is_standard_io(&self) -> bool { + *self == I2cmode::StandardIo + } + #[doc = "Fast-mode Plus I2C"] + #[inline(always)] + pub fn is_fast_plus_i2c(&self) -> bool { + *self == I2cmode::FastPlusI2c + } +} +#[doc = "Field `I2CMODE` writer - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] +pub type I2cmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, I2cmode>; +impl<'a, REG> I2cmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Standard mode/Fast-mode I2C"] + #[inline(always)] + pub fn standard_i2c(self) -> &'a mut crate::W { + self.variant(I2cmode::StandardI2c) + } + #[doc = "Standard I/O"] + #[inline(always)] + pub fn standard_io(self) -> &'a mut crate::W { + self.variant(I2cmode::StandardIo) + } + #[doc = "Fast-mode Plus I2C"] + #[inline(always)] + pub fn fast_plus_i2c(self) -> &'a mut crate::W { + self.variant(I2cmode::FastPlusI2c) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] + #[inline(always)] + pub fn i2cmode(&self) -> I2cmodeR { + I2cmodeR::new(((self.bits >> 8) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 8:9 - Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000)."] + #[inline(always)] + #[must_use] + pub fn i2cmode(&mut self) -> I2cmodeW { + I2cmodeW::new(self, 8) + } +} +#[doc = "I/O configuration for pin PIO0_5/SDA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_5Spec; +impl crate::RegisterSpec for Pio0_5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_5::R`](R) reader structure"] +impl crate::Readable for Pio0_5Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_5::W`](W) writer structure"] +impl crate::Writable for Pio0_5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_5 to value 0"] +impl crate::Resettable for Pio0_5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs new file mode 100644 index 0000000..a2fd1eb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_6.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO0_6` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_6` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_6."] + SelectsFunctionPio = 0, + #[doc = "1: Reserved."] + Reserved_ = 1, + #[doc = "2: Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."] + SelectsFunctionSck = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::Reserved_), + 2 => Some(Func::SelectsFunctionSck), + _ => None, + } + } + #[doc = "Selects function PIO0_6."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Reserved."] + #[inline(always)] + pub fn is_reserved_(&self) -> bool { + *self == Func::Reserved_ + } + #[doc = "Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."] + #[inline(always)] + pub fn is_selects_function_sck(&self) -> bool { + *self == Func::SelectsFunctionSck + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_6."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Reserved."] + #[inline(always)] + pub fn reserved_(self) -> &'a mut crate::W { + self.variant(Func::Reserved_) + } + #[doc = "Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147)."] + #[inline(always)] + pub fn selects_function_sck(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSck) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_6/SCK0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_6Spec; +impl crate::RegisterSpec for Pio0_6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_6::R`](R) reader structure"] +impl crate::Readable for Pio0_6Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_6::W`](W) writer structure"] +impl crate::Writable for Pio0_6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_6 to value 0xd0"] +impl crate::Resettable for Pio0_6Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs new file mode 100644 index 0000000..9822d15 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_7.rs @@ -0,0 +1,319 @@ +#[doc = "Register `PIO0_7` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_7` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_7."] + SelectsFunctionPio = 0, + #[doc = "1: Select function CTS."] + SelectFunctionCts_ = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectFunctionCts_), + _ => None, + } + } + #[doc = "Selects function PIO0_7."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Select function CTS."] + #[inline(always)] + pub fn is_select_function_cts_(&self) -> bool { + *self == Func::SelectFunctionCts_ + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_7."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Select function CTS."] + #[inline(always)] + pub fn select_function_cts_(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionCts_) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_7/CTS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_7Spec; +impl crate::RegisterSpec for Pio0_7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_7::R`](R) reader structure"] +impl crate::Readable for Pio0_7Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_7::W`](W) writer structure"] +impl crate::Writable for Pio0_7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_7 to value 0xd0"] +impl crate::Resettable for Pio0_7Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs new file mode 100644 index 0000000..60eae55 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_8.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO0_8` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_8` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_8."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function MISO0."] + SelectsFunctionMis = 1, + #[doc = "2: Selects function CT16B0_MAT0."] + SelectsFunctionCt1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionMis), + 2 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function PIO0_8."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function MISO0."] + #[inline(always)] + pub fn is_selects_function_mis(&self) -> bool { + *self == Func::SelectsFunctionMis + } + #[doc = "Selects function CT16B0_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_8."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function MISO0."] + #[inline(always)] + pub fn selects_function_mis(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionMis) + } + #[doc = "Selects function CT16B0_MAT0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_8Spec; +impl crate::RegisterSpec for Pio0_8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_8::R`](R) reader structure"] +impl crate::Readable for Pio0_8Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_8::W`](W) writer structure"] +impl crate::Writable for Pio0_8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_8 to value 0xd0"] +impl crate::Resettable for Pio0_8Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs b/rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs new file mode 100644 index 0000000..168a36d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio0_9.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO0_9` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0_9` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO0_9."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function MOSI0."] + SelectsFunctionMos = 1, + #[doc = "2: Selects function CT16B0_MAT1."] + SelectsFunctionCt1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionMos), + 2 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function PIO0_9."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function MOSI0."] + #[inline(always)] + pub fn is_selects_function_mos(&self) -> bool { + *self == Func::SelectsFunctionMos + } + #[doc = "Selects function CT16B0_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO0_9."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function MOSI0."] + #[inline(always)] + pub fn selects_function_mos(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionMos) + } + #[doc = "Selects function CT16B0_MAT1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio0_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio0_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio0_9Spec; +impl crate::RegisterSpec for Pio0_9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0_9::R`](R) reader structure"] +impl crate::Readable for Pio0_9Spec {} +#[doc = "`write(|w| ..)` method takes [`pio0_9::W`](W) writer structure"] +impl crate::Writable for Pio0_9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0_9 to value 0xd0"] +impl crate::Resettable for Pio0_9Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_10.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_10.rs new file mode 100644 index 0000000..62458b4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_10.rs @@ -0,0 +1,409 @@ +#[doc = "Register `PIO1_10` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_10` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_10."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function AD6."] + SelectsFunctionAd6 = 1, + #[doc = "2: Selects function CT16B1_MAT1."] + SelectsFunctionCt1 = 2, + #[doc = "3: Selects function MISO1."] + SelectsFunctionMis = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionAd6), + 2 => Some(Func::SelectsFunctionCt1), + 3 => Some(Func::SelectsFunctionMis), + _ => None, + } + } + #[doc = "Selects function PIO1_10."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD6."] + #[inline(always)] + pub fn is_selects_function_ad6(&self) -> bool { + *self == Func::SelectsFunctionAd6 + } + #[doc = "Selects function CT16B1_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function MISO1."] + #[inline(always)] + pub fn is_selects_function_mis(&self) -> bool { + *self == Func::SelectsFunctionMis + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_10."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD6."] + #[inline(always)] + pub fn selects_function_ad6(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd6) + } + #[doc = "Selects function CT16B1_MAT1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function MISO1."] + #[inline(always)] + pub fn selects_function_mis(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionMis) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_10Spec; +impl crate::RegisterSpec for Pio1_10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_10::R`](R) reader structure"] +impl crate::Readable for Pio1_10Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_10::W`](W) writer structure"] +impl crate::Writable for Pio1_10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_10 to value 0xd0"] +impl crate::Resettable for Pio1_10Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_11.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_11.rs new file mode 100644 index 0000000..87ad4c0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_11.rs @@ -0,0 +1,396 @@ +#[doc = "Register `PIO1_11` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_11` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_11."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function AD7."] + SelectsFunctionAd7 = 1, + #[doc = "2: Selects function CT32B1_CAP1."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionAd7), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO1_11."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD7."] + #[inline(always)] + pub fn is_selects_function_ad7(&self) -> bool { + *self == Func::SelectsFunctionAd7 + } + #[doc = "Selects function CT32B1_CAP1."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_11."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD7."] + #[inline(always)] + pub fn selects_function_ad7(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd7) + } + #[doc = "Selects function CT32B1_CAP1."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_11Spec; +impl crate::RegisterSpec for Pio1_11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_11::R`](R) reader structure"] +impl crate::Readable for Pio1_11Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_11::W`](W) writer structure"] +impl crate::Writable for Pio1_11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_11 to value 0xd0"] +impl crate::Resettable for Pio1_11Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs new file mode 100644 index 0000000..8a28d67 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_4.rs @@ -0,0 +1,396 @@ +#[doc = "Register `PIO1_4` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_4` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_4."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function AD5."] + SelectsFunctionAd5 = 1, + #[doc = "2: Selects function CT32B1_MAT3."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionAd5), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO1_4."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD5."] + #[inline(always)] + pub fn is_selects_function_ad5(&self) -> bool { + *self == Func::SelectsFunctionAd5 + } + #[doc = "Selects function CT32B1_MAT3."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_4."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD5."] + #[inline(always)] + pub fn selects_function_ad5(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd5) + } + #[doc = "Selects function CT32B1_MAT3."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_4Spec; +impl crate::RegisterSpec for Pio1_4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_4::R`](R) reader structure"] +impl crate::Readable for Pio1_4Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_4::W`](W) writer structure"] +impl crate::Writable for Pio1_4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_4 to value 0xd0"] +impl crate::Resettable for Pio1_4Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs new file mode 100644 index 0000000..e3fc7ee --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_5.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO1_5` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_5` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_5."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function RTS."] + SelectsFunctionRts = 1, + #[doc = "2: Selects function CT32B0_CAP0."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionRts), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO1_5."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function RTS."] + #[inline(always)] + pub fn is_selects_function_rts(&self) -> bool { + *self == Func::SelectsFunctionRts + } + #[doc = "Selects function CT32B0_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_5."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function RTS."] + #[inline(always)] + pub fn selects_function_rts(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRts) + } + #[doc = "Selects function CT32B0_CAP0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_5Spec; +impl crate::RegisterSpec for Pio1_5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_5::R`](R) reader structure"] +impl crate::Readable for Pio1_5Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_5::W`](W) writer structure"] +impl crate::Writable for Pio1_5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_5 to value 0xd0"] +impl crate::Resettable for Pio1_5Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs new file mode 100644 index 0000000..045341d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_6.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO1_6` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_6` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_6."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function RXD."] + SelectsFunctionRxd = 1, + #[doc = "2: Selects function CT32B0_MAT0."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionRxd), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO1_6."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn is_selects_function_rxd(&self) -> bool { + *self == Func::SelectsFunctionRxd + } + #[doc = "Selects function CT32B0_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_6."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn selects_function_rxd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRxd) + } + #[doc = "Selects function CT32B0_MAT0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_6Spec; +impl crate::RegisterSpec for Pio1_6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_6::R`](R) reader structure"] +impl crate::Readable for Pio1_6Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_6::W`](W) writer structure"] +impl crate::Writable for Pio1_6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_6 to value 0xd0"] +impl crate::Resettable for Pio1_6Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs new file mode 100644 index 0000000..dbe0dbb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_7.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO1_7` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_7` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_7."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function TXD."] + SelectsFunctionTxd = 1, + #[doc = "2: Selects function CT32B0_MAT1."] + SelectsFunctionCt3 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionTxd), + 2 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO1_7."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn is_selects_function_txd(&self) -> bool { + *self == Func::SelectsFunctionTxd + } + #[doc = "Selects function CT32B0_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_7."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn selects_function_txd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionTxd) + } + #[doc = "Selects function CT32B0_MAT1."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_7Spec; +impl crate::RegisterSpec for Pio1_7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_7::R`](R) reader structure"] +impl crate::Readable for Pio1_7Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_7::W`](W) writer structure"] +impl crate::Writable for Pio1_7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_7 to value 0xd0"] +impl crate::Resettable for Pio1_7Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs new file mode 100644 index 0000000..c249009 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_8.rs @@ -0,0 +1,319 @@ +#[doc = "Register `PIO1_8` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_8` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_8."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT16B1_CAP0."] + SelectsFunctionCt1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function PIO1_8."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT16B1_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_8."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT16B1_CAP0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_8/CT16B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_8Spec; +impl crate::RegisterSpec for Pio1_8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_8::R`](R) reader structure"] +impl crate::Readable for Pio1_8Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_8::W`](W) writer structure"] +impl crate::Writable for Pio1_8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_8 to value 0xd0"] +impl crate::Resettable for Pio1_8Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs b/rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs new file mode 100644 index 0000000..d10bc7e --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio1_9.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO1_9` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1_9` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO1_9."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT16B1_MAT0."] + SelectsFunctionCt1 = 1, + #[doc = "2: Selects function MOSI1."] + SelectsFunctionMos = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt1), + 2 => Some(Func::SelectsFunctionMos), + _ => None, + } + } + #[doc = "Selects function PIO1_9."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT16B1_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function MOSI1."] + #[inline(always)] + pub fn is_selects_function_mos(&self) -> bool { + *self == Func::SelectsFunctionMos + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO1_9."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT16B1_MAT0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function MOSI1."] + #[inline(always)] + pub fn selects_function_mos(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionMos) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio1_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio1_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio1_9Spec; +impl crate::RegisterSpec for Pio1_9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1_9::R`](R) reader structure"] +impl crate::Readable for Pio1_9Spec {} +#[doc = "`write(|w| ..)` method takes [`pio1_9::W`](W) writer structure"] +impl crate::Writable for Pio1_9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1_9 to value 0xd0"] +impl crate::Resettable for Pio1_9Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs new file mode 100644 index 0000000..59cbc4a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_0.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_0` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_0` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_0."] + SelectsFunctionPio = 0, + #[doc = "1: Select function DTR."] + SelectFunctionDtr_ = 1, + #[doc = "2: Select function SSEL1."] + SelectFunctionSsel = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectFunctionDtr_), + 2 => Some(Func::SelectFunctionSsel), + _ => None, + } + } + #[doc = "Selects function PIO2_0."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Select function DTR."] + #[inline(always)] + pub fn is_select_function_dtr_(&self) -> bool { + *self == Func::SelectFunctionDtr_ + } + #[doc = "Select function SSEL1."] + #[inline(always)] + pub fn is_select_function_ssel(&self) -> bool { + *self == Func::SelectFunctionSsel + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_0."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Select function DTR."] + #[inline(always)] + pub fn select_function_dtr_(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionDtr_) + } + #[doc = "Select function SSEL1."] + #[inline(always)] + pub fn select_function_ssel(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionSsel) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_0/DTR/SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_0Spec; +impl crate::RegisterSpec for Pio2_0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_0::R`](R) reader structure"] +impl crate::Readable for Pio2_0Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_0::W`](W) writer structure"] +impl crate::Writable for Pio2_0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_0 to value 0xd0"] +impl crate::Resettable for Pio2_0Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs new file mode 100644 index 0000000..eb30ad5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_1.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_1` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_1` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_1."] + SelectsFunctionPio = 0, + #[doc = "1: Select function DSR."] + SelectFunctionDsr_ = 1, + #[doc = "2: Select function SCK1."] + SelectFunctionSck1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectFunctionDsr_), + 2 => Some(Func::SelectFunctionSck1), + _ => None, + } + } + #[doc = "Selects function PIO2_1."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Select function DSR."] + #[inline(always)] + pub fn is_select_function_dsr_(&self) -> bool { + *self == Func::SelectFunctionDsr_ + } + #[doc = "Select function SCK1."] + #[inline(always)] + pub fn is_select_function_sck1(&self) -> bool { + *self == Func::SelectFunctionSck1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_1."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Select function DSR."] + #[inline(always)] + pub fn select_function_dsr_(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionDsr_) + } + #[doc = "Select function SCK1."] + #[inline(always)] + pub fn select_function_sck1(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionSck1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_1/DSR/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_1Spec; +impl crate::RegisterSpec for Pio2_1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_1::R`](R) reader structure"] +impl crate::Readable for Pio2_1Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_1::W`](W) writer structure"] +impl crate::Writable for Pio2_1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_1 to value 0xd0"] +impl crate::Resettable for Pio2_1Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_10.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_10.rs new file mode 100644 index 0000000..ddb30fe --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_10.rs @@ -0,0 +1,306 @@ +#[doc = "Register `PIO2_10` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_10` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_10."] + SelectsFunctionPio = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + _ => None, + } + } + #[doc = "Selects function PIO2_10."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_10."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_10\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_10Spec; +impl crate::RegisterSpec for Pio2_10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_10::R`](R) reader structure"] +impl crate::Readable for Pio2_10Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_10::W`](W) writer structure"] +impl crate::Writable for Pio2_10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_10 to value 0xd0"] +impl crate::Resettable for Pio2_10Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_11.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_11.rs new file mode 100644 index 0000000..cd986cb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_11.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_11` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_11` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_11."] + SelectsFunctionPio = 0, + #[doc = "1: Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."] + SelectFunctionSck0 = 1, + #[doc = "2: Select function CT32B0_CAP1."] + SelectFunctionCt32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectFunctionSck0), + 2 => Some(Func::SelectFunctionCt32), + _ => None, + } + } + #[doc = "Selects function PIO2_11."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."] + #[inline(always)] + pub fn is_select_function_sck0(&self) -> bool { + *self == Func::SelectFunctionSck0 + } + #[doc = "Select function CT32B0_CAP1."] + #[inline(always)] + pub fn is_select_function_ct32(&self) -> bool { + *self == Func::SelectFunctionCt32 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_11."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147)."] + #[inline(always)] + pub fn select_function_sck0(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionSck0) + } + #[doc = "Select function CT32B0_CAP1."] + #[inline(always)] + pub fn select_function_ct32(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionCt32) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_11Spec; +impl crate::RegisterSpec for Pio2_11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_11::R`](R) reader structure"] +impl crate::Readable for Pio2_11Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_11::W`](W) writer structure"] +impl crate::Writable for Pio2_11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_11 to value 0xd0"] +impl crate::Resettable for Pio2_11Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs new file mode 100644 index 0000000..ba9792a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_2.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_2` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_2` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_2."] + SelectsFunctionPio = 0, + #[doc = "1: Select function DCD."] + SelectFunctionDcd_ = 1, + #[doc = "2: Select function MISO1."] + SelectFunctionMiso = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectFunctionDcd_), + 2 => Some(Func::SelectFunctionMiso), + _ => None, + } + } + #[doc = "Selects function PIO2_2."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Select function DCD."] + #[inline(always)] + pub fn is_select_function_dcd_(&self) -> bool { + *self == Func::SelectFunctionDcd_ + } + #[doc = "Select function MISO1."] + #[inline(always)] + pub fn is_select_function_miso(&self) -> bool { + *self == Func::SelectFunctionMiso + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_2."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Select function DCD."] + #[inline(always)] + pub fn select_function_dcd_(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionDcd_) + } + #[doc = "Select function MISO1."] + #[inline(always)] + pub fn select_function_miso(self) -> &'a mut crate::W { + self.variant(Func::SelectFunctionMiso) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_2/DCD/MISO1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_2Spec; +impl crate::RegisterSpec for Pio2_2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_2::R`](R) reader structure"] +impl crate::Readable for Pio2_2Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_2::W`](W) writer structure"] +impl crate::Writable for Pio2_2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_2 to value 0xd0"] +impl crate::Resettable for Pio2_2Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs new file mode 100644 index 0000000..cadd3c3 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_3.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_3` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_3` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_3."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function RI."] + SelectsFunctionRi_ = 1, + #[doc = "2: Selects function MOSI1."] + SelectsFunctionMos = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionRi_), + 2 => Some(Func::SelectsFunctionMos), + _ => None, + } + } + #[doc = "Selects function PIO2_3."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function RI."] + #[inline(always)] + pub fn is_selects_function_ri_(&self) -> bool { + *self == Func::SelectsFunctionRi_ + } + #[doc = "Selects function MOSI1."] + #[inline(always)] + pub fn is_selects_function_mos(&self) -> bool { + *self == Func::SelectsFunctionMos + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_3."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function RI."] + #[inline(always)] + pub fn selects_function_ri_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRi_) + } + #[doc = "Selects function MOSI1."] + #[inline(always)] + pub fn selects_function_mos(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionMos) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_3/RI/MOSI1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_3Spec; +impl crate::RegisterSpec for Pio2_3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_3::R`](R) reader structure"] +impl crate::Readable for Pio2_3Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_3::W`](W) writer structure"] +impl crate::Writable for Pio2_3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_3 to value 0xd0"] +impl crate::Resettable for Pio2_3Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs new file mode 100644 index 0000000..64c0b7c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_4.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_4` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_4` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_4."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT16B1_MAT1."] + SelectsFunctionCt1 = 1, + #[doc = "2: Selects function SSEL1."] + SelectsFunctionSse = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt1), + 2 => Some(Func::SelectsFunctionSse), + _ => None, + } + } + #[doc = "Selects function PIO2_4."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT16B1_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function SSEL1."] + #[inline(always)] + pub fn is_selects_function_sse(&self) -> bool { + *self == Func::SelectsFunctionSse + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_4."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT16B1_MAT1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function SSEL1."] + #[inline(always)] + pub fn selects_function_sse(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSse) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_4Spec; +impl crate::RegisterSpec for Pio2_4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_4::R`](R) reader structure"] +impl crate::Readable for Pio2_4Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_4::W`](W) writer structure"] +impl crate::Writable for Pio2_4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_4 to value 0xd0"] +impl crate::Resettable for Pio2_4Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs new file mode 100644 index 0000000..cb441fc --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_5.rs @@ -0,0 +1,319 @@ +#[doc = "Register `PIO2_5` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_5` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_5."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT32B0_MAT0."] + SelectsFunctionCt3 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO2_5."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT32B0_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_5."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT32B0_MAT0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_5/ CT32B0_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_5Spec; +impl crate::RegisterSpec for Pio2_5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_5::R`](R) reader structure"] +impl crate::Readable for Pio2_5Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_5::W`](W) writer structure"] +impl crate::Writable for Pio2_5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_5 to value 0xd0"] +impl crate::Resettable for Pio2_5Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs new file mode 100644 index 0000000..2f464af --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_6.rs @@ -0,0 +1,319 @@ +#[doc = "Register `PIO2_6` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_6` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_6."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT32B0_MAT1."] + SelectsFunctionCt3 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO2_6."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT32B0_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_6."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT32B0_MAT1."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_6/ CT32B0_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_6Spec; +impl crate::RegisterSpec for Pio2_6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_6::R`](R) reader structure"] +impl crate::Readable for Pio2_6Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_6::W`](W) writer structure"] +impl crate::Writable for Pio2_6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_6 to value 0xd0"] +impl crate::Resettable for Pio2_6Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_7.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_7.rs new file mode 100644 index 0000000..702e50b --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_7.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_7` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_7` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_7."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT32B0_MAT2."] + SelectsFunctionCt3 = 1, + #[doc = "2: Selects function RXD."] + SelectsFunctionRxd = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt3), + 2 => Some(Func::SelectsFunctionRxd), + _ => None, + } + } + #[doc = "Selects function PIO2_7."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT32B0_MAT2."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn is_selects_function_rxd(&self) -> bool { + *self == Func::SelectsFunctionRxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_7."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT32B0_MAT2."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn selects_function_rxd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_7Spec; +impl crate::RegisterSpec for Pio2_7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_7::R`](R) reader structure"] +impl crate::Readable for Pio2_7Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_7::W`](W) writer structure"] +impl crate::Writable for Pio2_7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_7 to value 0xd0"] +impl crate::Resettable for Pio2_7Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_8.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_8.rs new file mode 100644 index 0000000..2ac09fe --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_8.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO2_8` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_8` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_8."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT32B0_MAT3."] + SelectsFunctionCt3 = 1, + #[doc = "2: Selects function TXD."] + SelectsFunctionTxd = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt3), + 2 => Some(Func::SelectsFunctionTxd), + _ => None, + } + } + #[doc = "Selects function PIO2_8."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT32B0_MAT3."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn is_selects_function_txd(&self) -> bool { + *self == Func::SelectsFunctionTxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_8."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT32B0_MAT3."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn selects_function_txd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionTxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_8Spec; +impl crate::RegisterSpec for Pio2_8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_8::R`](R) reader structure"] +impl crate::Readable for Pio2_8Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_8::W`](W) writer structure"] +impl crate::Writable for Pio2_8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_8 to value 0xd0"] +impl crate::Resettable for Pio2_8Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio2_9.rs b/rust-embedded/lpc111x-pac/src/iocon/pio2_9.rs new file mode 100644 index 0000000..ae2ef56 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio2_9.rs @@ -0,0 +1,319 @@ +#[doc = "Register `PIO2_9` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2_9` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO2_9."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT32B0_CAP0."] + SelectsFunctionCt3 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function PIO2_9."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT32B0_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO2_9."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT32B0_CAP0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO2_9/ CT32B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio2_9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio2_9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio2_9Spec; +impl crate::RegisterSpec for Pio2_9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2_9::R`](R) reader structure"] +impl crate::Readable for Pio2_9Spec {} +#[doc = "`write(|w| ..)` method takes [`pio2_9::W`](W) writer structure"] +impl crate::Writable for Pio2_9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2_9 to value 0xd0"] +impl crate::Resettable for Pio2_9Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_0.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_0.rs new file mode 100644 index 0000000..de0c329 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_0.rs @@ -0,0 +1,345 @@ +#[doc = "Register `PIO3_0` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_0` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_0."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function DTR."] + SelectsFunctionDtr = 1, + #[doc = "2: Selects function CT16B0_MAT0."] + SelectsFunctionCt1 = 2, + #[doc = "3: Selects function TXD."] + SelectsFunctionTxd = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionDtr), + 2 => Some(Func::SelectsFunctionCt1), + 3 => Some(Func::SelectsFunctionTxd), + _ => None, + } + } + #[doc = "Selects function PIO3_0."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function DTR."] + #[inline(always)] + pub fn is_selects_function_dtr(&self) -> bool { + *self == Func::SelectsFunctionDtr + } + #[doc = "Selects function CT16B0_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn is_selects_function_txd(&self) -> bool { + *self == Func::SelectsFunctionTxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_0."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function DTR."] + #[inline(always)] + pub fn selects_function_dtr(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionDtr) + } + #[doc = "Selects function CT16B0_MAT0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn selects_function_txd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionTxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_0Spec; +impl crate::RegisterSpec for Pio3_0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_0::R`](R) reader structure"] +impl crate::Readable for Pio3_0Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_0::W`](W) writer structure"] +impl crate::Writable for Pio3_0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_0 to value 0xd0"] +impl crate::Resettable for Pio3_0Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_1.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_1.rs new file mode 100644 index 0000000..0b38ed2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_1.rs @@ -0,0 +1,345 @@ +#[doc = "Register `PIO3_1` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_1` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_1."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function DSR."] + SelectsFunctionDsr = 1, + #[doc = "2: Selects function CT16B0_MAT1."] + SelectsFunctionCt1 = 2, + #[doc = "3: Selects function RXD."] + SelectsFunctionRxd = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionDsr), + 2 => Some(Func::SelectsFunctionCt1), + 3 => Some(Func::SelectsFunctionRxd), + _ => None, + } + } + #[doc = "Selects function PIO3_1."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function DSR."] + #[inline(always)] + pub fn is_selects_function_dsr(&self) -> bool { + *self == Func::SelectsFunctionDsr + } + #[doc = "Selects function CT16B0_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn is_selects_function_rxd(&self) -> bool { + *self == Func::SelectsFunctionRxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_1."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function DSR."] + #[inline(always)] + pub fn selects_function_dsr(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionDsr) + } + #[doc = "Selects function CT16B0_MAT1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn selects_function_rxd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_1Spec; +impl crate::RegisterSpec for Pio3_1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_1::R`](R) reader structure"] +impl crate::Readable for Pio3_1Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_1::W`](W) writer structure"] +impl crate::Writable for Pio3_1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_1 to value 0xd0"] +impl crate::Resettable for Pio3_1Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_2.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_2.rs new file mode 100644 index 0000000..a231fae --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_2.rs @@ -0,0 +1,345 @@ +#[doc = "Register `PIO3_2` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_2` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_2."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function DCD."] + SelectsFunctionDcd = 1, + #[doc = "2: Selects function CT16B0_MAT2."] + SelectsFunctionCt1 = 2, + #[doc = "3: Selects function SCK1."] + SelectsFunctionSck = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionDcd), + 2 => Some(Func::SelectsFunctionCt1), + 3 => Some(Func::SelectsFunctionSck), + _ => None, + } + } + #[doc = "Selects function PIO3_2."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function DCD."] + #[inline(always)] + pub fn is_selects_function_dcd(&self) -> bool { + *self == Func::SelectsFunctionDcd + } + #[doc = "Selects function CT16B0_MAT2."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function SCK1."] + #[inline(always)] + pub fn is_selects_function_sck(&self) -> bool { + *self == Func::SelectsFunctionSck + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_2."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function DCD."] + #[inline(always)] + pub fn selects_function_dcd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionDcd) + } + #[doc = "Selects function CT16B0_MAT2."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function SCK1."] + #[inline(always)] + pub fn selects_function_sck(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSck) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_2Spec; +impl crate::RegisterSpec for Pio3_2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_2::R`](R) reader structure"] +impl crate::Readable for Pio3_2Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_2::W`](W) writer structure"] +impl crate::Writable for Pio3_2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_2 to value 0xd0"] +impl crate::Resettable for Pio3_2Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_3.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_3.rs new file mode 100644 index 0000000..4d47e06 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_3.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO3_3` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_3` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_3."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function RI."] + SelectsFunctionRi_ = 1, + #[doc = "2: Selects function CT16B0_CAP0."] + SelectsFunctionCt1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionRi_), + 2 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function PIO3_3."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function RI."] + #[inline(always)] + pub fn is_selects_function_ri_(&self) -> bool { + *self == Func::SelectsFunctionRi_ + } + #[doc = "Selects function CT16B0_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_3."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function RI."] + #[inline(always)] + pub fn selects_function_ri_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRi_) + } + #[doc = "Selects function CT16B0_CAP0."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_3Spec; +impl crate::RegisterSpec for Pio3_3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_3::R`](R) reader structure"] +impl crate::Readable for Pio3_3Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_3::W`](W) writer structure"] +impl crate::Writable for Pio3_3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_3 to value 0xd0"] +impl crate::Resettable for Pio3_3Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_4.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_4.rs new file mode 100644 index 0000000..d6dc381 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_4.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO3_4` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_4` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_4."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT16B0_CAP1."] + SelectsFunctionCt1 = 1, + #[doc = "2: Selects function RXD."] + SelectsFunctionRxd = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt1), + 2 => Some(Func::SelectsFunctionRxd), + _ => None, + } + } + #[doc = "Selects function PIO3_4."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT16B0_CAP1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn is_selects_function_rxd(&self) -> bool { + *self == Func::SelectsFunctionRxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_4."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT16B0_CAP1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function RXD."] + #[inline(always)] + pub fn selects_function_rxd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_4Spec; +impl crate::RegisterSpec for Pio3_4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_4::R`](R) reader structure"] +impl crate::Readable for Pio3_4Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_4::W`](W) writer structure"] +impl crate::Writable for Pio3_4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_4 to value 0xd0"] +impl crate::Resettable for Pio3_4Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/pio3_5.rs b/rust-embedded/lpc111x-pac/src/iocon/pio3_5.rs new file mode 100644 index 0000000..2e3d3da --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/pio3_5.rs @@ -0,0 +1,332 @@ +#[doc = "Register `PIO3_5` reader"] +pub type R = crate::R; +#[doc = "Register `PIO3_5` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function PIO3_5."] + SelectsFunctionPio = 0, + #[doc = "1: Selects function CT16B1_CAP1."] + SelectsFunctionCt1 = 1, + #[doc = "2: Selects function TXD."] + SelectsFunctionTxd = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionPio), + 1 => Some(Func::SelectsFunctionCt1), + 2 => Some(Func::SelectsFunctionTxd), + _ => None, + } + } + #[doc = "Selects function PIO3_5."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function CT16B1_CAP1."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn is_selects_function_txd(&self) -> bool { + *self == Func::SelectsFunctionTxd + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function PIO3_5."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function CT16B1_CAP1."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } + #[doc = "Selects function TXD."] + #[inline(always)] + pub fn selects_function_txd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionTxd) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio3_5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio3_5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pio3_5Spec; +impl crate::RegisterSpec for Pio3_5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio3_5::R`](R) reader structure"] +impl crate::Readable for Pio3_5Spec {} +#[doc = "`write(|w| ..)` method takes [`pio3_5::W`](W) writer structure"] +impl crate::Writable for Pio3_5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO3_5 to value 0xd0"] +impl crate::Resettable for Pio3_5Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/r_pio0_11.rs b/rust-embedded/lpc111x-pac/src/iocon/r_pio0_11.rs new file mode 100644 index 0000000..a867301 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/r_pio0_11.rs @@ -0,0 +1,409 @@ +#[doc = "Register `R_PIO0_11` reader"] +pub type R = crate::R; +#[doc = "Register `R_PIO0_11` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function R. This function is reserved. Select one of the alternate functions below."] + SelectsFunctionR_ = 0, + #[doc = "1: Selects function PIO0_11."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function AD0."] + SelectsFunctionAd0 = 2, + #[doc = "3: Selects function CT32B0_MAT3."] + SelectsFunctionCt3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionR_), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionAd0), + 3 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn is_selects_function_r_(&self) -> bool { + *self == Func::SelectsFunctionR_ + } + #[doc = "Selects function PIO0_11."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD0."] + #[inline(always)] + pub fn is_selects_function_ad0(&self) -> bool { + *self == Func::SelectsFunctionAd0 + } + #[doc = "Selects function CT32B0_MAT3."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn selects_function_r_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionR_) + } + #[doc = "Selects function PIO0_11."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD0."] + #[inline(always)] + pub fn selects_function_ad0(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd0) + } + #[doc = "Selects function CT32B0_MAT3."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio0_11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio0_11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RPio0_11Spec; +impl crate::RegisterSpec for RPio0_11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`r_pio0_11::R`](R) reader structure"] +impl crate::Readable for RPio0_11Spec {} +#[doc = "`write(|w| ..)` method takes [`r_pio0_11::W`](W) writer structure"] +impl crate::Writable for RPio0_11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets R_PIO0_11 to value 0xd0"] +impl crate::Resettable for RPio0_11Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/r_pio1_0.rs b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_0.rs new file mode 100644 index 0000000..e805bbb --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_0.rs @@ -0,0 +1,409 @@ +#[doc = "Register `R_PIO1_0` reader"] +pub type R = crate::R; +#[doc = "Register `R_PIO1_0` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function R. This function is reserved. Select one of the alternate functions below."] + SelectsFunctionR_ = 0, + #[doc = "1: Selects function PIO1_0."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function AD1."] + SelectsFunctionAd1 = 2, + #[doc = "3: Selects function CT32B1_CAP0."] + SelectsFunctionCt3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionR_), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionAd1), + 3 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn is_selects_function_r_(&self) -> bool { + *self == Func::SelectsFunctionR_ + } + #[doc = "Selects function PIO1_0."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD1."] + #[inline(always)] + pub fn is_selects_function_ad1(&self) -> bool { + *self == Func::SelectsFunctionAd1 + } + #[doc = "Selects function CT32B1_CAP0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn selects_function_r_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionR_) + } + #[doc = "Selects function PIO1_0."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD1."] + #[inline(always)] + pub fn selects_function_ad1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd1) + } + #[doc = "Selects function CT32B1_CAP0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RPio1_0Spec; +impl crate::RegisterSpec for RPio1_0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`r_pio1_0::R`](R) reader structure"] +impl crate::Readable for RPio1_0Spec {} +#[doc = "`write(|w| ..)` method takes [`r_pio1_0::W`](W) writer structure"] +impl crate::Writable for RPio1_0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets R_PIO1_0 to value 0xd0"] +impl crate::Resettable for RPio1_0Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/r_pio1_1.rs b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_1.rs new file mode 100644 index 0000000..bc6191d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_1.rs @@ -0,0 +1,409 @@ +#[doc = "Register `R_PIO1_1` reader"] +pub type R = crate::R; +#[doc = "Register `R_PIO1_1` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function R. This function is reserved. Select one of the alternate functions below."] + SelectsFunctionR_ = 0, + #[doc = "1: Selects function PIO1_1."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function AD2."] + SelectsFunctionAd2 = 2, + #[doc = "3: Selects function CT32B1_MAT0."] + SelectsFunctionCt3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionR_), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionAd2), + 3 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn is_selects_function_r_(&self) -> bool { + *self == Func::SelectsFunctionR_ + } + #[doc = "Selects function PIO1_1."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD2."] + #[inline(always)] + pub fn is_selects_function_ad2(&self) -> bool { + *self == Func::SelectsFunctionAd2 + } + #[doc = "Selects function CT32B1_MAT0."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn selects_function_r_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionR_) + } + #[doc = "Selects function PIO1_1."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD2."] + #[inline(always)] + pub fn selects_function_ad2(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd2) + } + #[doc = "Selects function CT32B1_MAT0."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RPio1_1Spec; +impl crate::RegisterSpec for RPio1_1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`r_pio1_1::R`](R) reader structure"] +impl crate::Readable for RPio1_1Spec {} +#[doc = "`write(|w| ..)` method takes [`r_pio1_1::W`](W) writer structure"] +impl crate::Writable for RPio1_1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets R_PIO1_1 to value 0xd0"] +impl crate::Resettable for RPio1_1Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/r_pio1_2.rs b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_2.rs new file mode 100644 index 0000000..25d987d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/r_pio1_2.rs @@ -0,0 +1,409 @@ +#[doc = "Register `R_PIO1_2` reader"] +pub type R = crate::R; +#[doc = "Register `R_PIO1_2` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function R. This function is reserved. Select one of the alternate functions below."] + SelectsFunctionR_ = 0, + #[doc = "1: Selects function PIO1_2."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function AD3."] + SelectsFunctionAd3 = 2, + #[doc = "3: Selects function CT32B1_MAT1."] + SelectsFunctionCt3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionR_), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionAd3), + 3 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn is_selects_function_r_(&self) -> bool { + *self == Func::SelectsFunctionR_ + } + #[doc = "Selects function PIO1_2."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD3."] + #[inline(always)] + pub fn is_selects_function_ad3(&self) -> bool { + *self == Func::SelectsFunctionAd3 + } + #[doc = "Selects function CT32B1_MAT1."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function R. This function is reserved. Select one of the alternate functions below."] + #[inline(always)] + pub fn selects_function_r_(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionR_) + } + #[doc = "Selects function PIO1_2."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD3."] + #[inline(always)] + pub fn selects_function_ad3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd3) + } + #[doc = "Selects function CT32B1_MAT1."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r_pio1_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r_pio1_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RPio1_2Spec; +impl crate::RegisterSpec for RPio1_2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`r_pio1_2::R`](R) reader structure"] +impl crate::Readable for RPio1_2Spec {} +#[doc = "`write(|w| ..)` method takes [`r_pio1_2::W`](W) writer structure"] +impl crate::Writable for RPio1_2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets R_PIO1_2 to value 0xd0"] +impl crate::Resettable for RPio1_2Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/reset_pio0_0.rs b/rust-embedded/lpc111x-pac/src/iocon/reset_pio0_0.rs new file mode 100644 index 0000000..20e3f08 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/reset_pio0_0.rs @@ -0,0 +1,319 @@ +#[doc = "Register `RESET_PIO0_0` reader"] +pub type R = crate::R; +#[doc = "Register `RESET_PIO0_0` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function RESET."] + SelectsFunctionRes = 0, + #[doc = "1: Selects function PIO0_0."] + SelectsFunctionPio = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionRes), + 1 => Some(Func::SelectsFunctionPio), + _ => None, + } + } + #[doc = "Selects function RESET."] + #[inline(always)] + pub fn is_selects_function_res(&self) -> bool { + *self == Func::SelectsFunctionRes + } + #[doc = "Selects function PIO0_0."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function RESET."] + #[inline(always)] + pub fn selects_function_res(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionRes) + } + #[doc = "Selects function PIO0_0."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin RESET/PIO0_0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_pio0_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_pio0_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ResetPio0_0Spec; +impl crate::RegisterSpec for ResetPio0_0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset_pio0_0::R`](R) reader structure"] +impl crate::Readable for ResetPio0_0Spec {} +#[doc = "`write(|w| ..)` method takes [`reset_pio0_0::W`](W) writer structure"] +impl crate::Writable for ResetPio0_0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RESET_PIO0_0 to value 0xd0"] +impl crate::Resettable for ResetPio0_0Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/ri_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/ri_loc.rs new file mode 100644 index 0000000..372624c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/ri_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `RI_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `RI_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for RI function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Riloc { + #[doc = "0: `0`"] + Pio2_3 = 0, + #[doc = "1: `1`"] + Pio3_3 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Riloc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Riloc { + type Ux = u8; +} +#[doc = "Field `RILOC` reader - Selects pin location for RI function."] +pub type RilocR = crate::FieldReader; +impl RilocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Riloc::Pio2_3), + 1 => Some(Riloc::Pio3_3), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_3(&self) -> bool { + *self == Riloc::Pio2_3 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_3(&self) -> bool { + *self == Riloc::Pio3_3 + } +} +#[doc = "Field `RILOC` writer - Selects pin location for RI function."] +pub type RilocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Riloc>; +impl<'a, REG> RilocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_3(self) -> &'a mut crate::W { + self.variant(Riloc::Pio2_3) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_3(self) -> &'a mut crate::W { + self.variant(Riloc::Pio3_3) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for RI function."] + #[inline(always)] + pub fn riloc(&self) -> RilocR { + RilocR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for RI function."] + #[inline(always)] + #[must_use] + pub fn riloc(&mut self) -> RilocW { + RilocW::new(self, 0) + } +} +#[doc = "RI pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ri_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ri_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RiLocSpec; +impl crate::RegisterSpec for RiLocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ri_loc::R`](R) reader structure"] +impl crate::Readable for RiLocSpec {} +#[doc = "`write(|w| ..)` method takes [`ri_loc::W`](W) writer structure"] +impl crate::Writable for RiLocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RI_LOC to value 0"] +impl crate::Resettable for RiLocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/rxd_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/rxd_loc.rs new file mode 100644 index 0000000..776be34 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/rxd_loc.rs @@ -0,0 +1,121 @@ +#[doc = "Register `RXD_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `RXD_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for the RXD function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxdloc { + #[doc = "0: `0`"] + Pio1_6 = 0, + #[doc = "1: `1`"] + Pio2_7 = 1, + #[doc = "2: `10`"] + Pio3_1 = 2, + #[doc = "3: `11`"] + Pio3_4 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxdloc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxdloc { + type Ux = u8; +} +#[doc = "Field `RXDLOC` reader - Selects pin location for the RXD function."] +pub type RxdlocR = crate::FieldReader; +impl RxdlocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxdloc { + match self.bits { + 0 => Rxdloc::Pio1_6, + 1 => Rxdloc::Pio2_7, + 2 => Rxdloc::Pio3_1, + 3 => Rxdloc::Pio3_4, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio1_6(&self) -> bool { + *self == Rxdloc::Pio1_6 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio2_7(&self) -> bool { + *self == Rxdloc::Pio2_7 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_pio3_1(&self) -> bool { + *self == Rxdloc::Pio3_1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_pio3_4(&self) -> bool { + *self == Rxdloc::Pio3_4 + } +} +#[doc = "Field `RXDLOC` writer - Selects pin location for the RXD function."] +pub type RxdlocW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Rxdloc>; +impl<'a, REG> RxdlocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio1_6(self) -> &'a mut crate::W { + self.variant(Rxdloc::Pio1_6) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio2_7(self) -> &'a mut crate::W { + self.variant(Rxdloc::Pio2_7) + } + #[doc = "`10`"] + #[inline(always)] + pub fn pio3_1(self) -> &'a mut crate::W { + self.variant(Rxdloc::Pio3_1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn pio3_4(self) -> &'a mut crate::W { + self.variant(Rxdloc::Pio3_4) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for the RXD function."] + #[inline(always)] + pub fn rxdloc(&self) -> RxdlocR { + RxdlocR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for the RXD function."] + #[inline(always)] + #[must_use] + pub fn rxdloc(&mut self) -> RxdlocW { + RxdlocW::new(self, 0) + } +} +#[doc = "RXD pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxd_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxdLocSpec; +impl crate::RegisterSpec for RxdLocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxd_loc::R`](R) reader structure"] +impl crate::Readable for RxdLocSpec {} +#[doc = "`write(|w| ..)` method takes [`rxd_loc::W`](W) writer structure"] +impl crate::Writable for RxdLocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXD_LOC to value 0"] +impl crate::Resettable for RxdLocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/sck0_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/sck0_loc.rs new file mode 100644 index 0000000..848bc8a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/sck0_loc.rs @@ -0,0 +1,108 @@ +#[doc = "Register `SCK0_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `SCK0_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for SCK0 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sckloc { + #[doc = "0: `0`"] + Pi00_10 = 0, + #[doc = "1: `1`"] + Pi02_11 = 1, + #[doc = "2: `10`"] + Pi00_6 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sckloc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sckloc { + type Ux = u8; +} +#[doc = "Field `SCKLOC` reader - Selects pin location for SCK0 function."] +pub type ScklocR = crate::FieldReader; +impl ScklocR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sckloc::Pi00_10), + 1 => Some(Sckloc::Pi02_11), + 2 => Some(Sckloc::Pi00_6), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pi00_10(&self) -> bool { + *self == Sckloc::Pi00_10 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pi02_11(&self) -> bool { + *self == Sckloc::Pi02_11 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_pi00_6(&self) -> bool { + *self == Sckloc::Pi00_6 + } +} +#[doc = "Field `SCKLOC` writer - Selects pin location for SCK0 function."] +pub type ScklocW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sckloc>; +impl<'a, REG> ScklocW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pi00_10(self) -> &'a mut crate::W { + self.variant(Sckloc::Pi00_10) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pi02_11(self) -> &'a mut crate::W { + self.variant(Sckloc::Pi02_11) + } + #[doc = "`10`"] + #[inline(always)] + pub fn pi00_6(self) -> &'a mut crate::W { + self.variant(Sckloc::Pi00_6) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for SCK0 function."] + #[inline(always)] + pub fn sckloc(&self) -> ScklocR { + ScklocR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for SCK0 function."] + #[inline(always)] + #[must_use] + pub fn sckloc(&mut self) -> ScklocW { + ScklocW::new(self, 0) + } +} +#[doc = "SCK0 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck0_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck0_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sck0LocSpec; +impl crate::RegisterSpec for Sck0LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sck0_loc::R`](R) reader structure"] +impl crate::Readable for Sck0LocSpec {} +#[doc = "`write(|w| ..)` method takes [`sck0_loc::W`](W) writer structure"] +impl crate::Writable for Sck0LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCK0_LOC to value 0"] +impl crate::Resettable for Sck0LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/sck1_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/sck1_loc.rs new file mode 100644 index 0000000..d071855 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/sck1_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `SCK1_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `SCK1_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for SCK1 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sck1loc { + #[doc = "0: `0`"] + Pio2_1 = 0, + #[doc = "1: `1`"] + Pio3_2 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sck1loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sck1loc { + type Ux = u8; +} +#[doc = "Field `SCK1LOC` reader - Selects pin location for SCK1 function."] +pub type Sck1locR = crate::FieldReader; +impl Sck1locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Sck1loc::Pio2_1), + 1 => Some(Sck1loc::Pio3_2), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_1(&self) -> bool { + *self == Sck1loc::Pio2_1 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_2(&self) -> bool { + *self == Sck1loc::Pio3_2 + } +} +#[doc = "Field `SCK1LOC` writer - Selects pin location for SCK1 function."] +pub type Sck1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sck1loc>; +impl<'a, REG> Sck1locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_1(self) -> &'a mut crate::W { + self.variant(Sck1loc::Pio2_1) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_2(self) -> &'a mut crate::W { + self.variant(Sck1loc::Pio3_2) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for SCK1 function."] + #[inline(always)] + pub fn sck1loc(&self) -> Sck1locR { + Sck1locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for SCK1 function."] + #[inline(always)] + #[must_use] + pub fn sck1loc(&mut self) -> Sck1locW { + Sck1locW::new(self, 0) + } +} +#[doc = "SCK1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sck1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sck1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Sck1LocSpec; +impl crate::RegisterSpec for Sck1LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sck1_loc::R`](R) reader structure"] +impl crate::Readable for Sck1LocSpec {} +#[doc = "`write(|w| ..)` method takes [`sck1_loc::W`](W) writer structure"] +impl crate::Writable for Sck1LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCK1_LOC to value 0"] +impl crate::Resettable for Sck1LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/ssel1_loc.rs b/rust-embedded/lpc111x-pac/src/iocon/ssel1_loc.rs new file mode 100644 index 0000000..c3604c0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/ssel1_loc.rs @@ -0,0 +1,95 @@ +#[doc = "Register `SSEL1_LOC` reader"] +pub type R = crate::R; +#[doc = "Register `SSEL1_LOC` writer"] +pub type W = crate::W; +#[doc = "Selects pin location for SSEL1 function.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ssel1loc { + #[doc = "0: `0`"] + Pio2_2 = 0, + #[doc = "1: `1`"] + Pio3_4 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ssel1loc) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ssel1loc { + type Ux = u8; +} +#[doc = "Field `SSEL1LOC` reader - Selects pin location for SSEL1 function."] +pub type Ssel1locR = crate::FieldReader; +impl Ssel1locR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Ssel1loc::Pio2_2), + 1 => Some(Ssel1loc::Pio3_4), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_pio2_2(&self) -> bool { + *self == Ssel1loc::Pio2_2 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pio3_4(&self) -> bool { + *self == Ssel1loc::Pio3_4 + } +} +#[doc = "Field `SSEL1LOC` writer - Selects pin location for SSEL1 function."] +pub type Ssel1locW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ssel1loc>; +impl<'a, REG> Ssel1locW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn pio2_2(self) -> &'a mut crate::W { + self.variant(Ssel1loc::Pio2_2) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pio3_4(self) -> &'a mut crate::W { + self.variant(Ssel1loc::Pio3_4) + } +} +impl R { + #[doc = "Bits 0:1 - Selects pin location for SSEL1 function."] + #[inline(always)] + pub fn ssel1loc(&self) -> Ssel1locR { + Ssel1locR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects pin location for SSEL1 function."] + #[inline(always)] + #[must_use] + pub fn ssel1loc(&mut self) -> Ssel1locW { + Ssel1locW::new(self, 0) + } +} +#[doc = "SSEL1 pin location select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssel1_loc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssel1_loc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ssel1LocSpec; +impl crate::RegisterSpec for Ssel1LocSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssel1_loc::R`](R) reader structure"] +impl crate::Readable for Ssel1LocSpec {} +#[doc = "`write(|w| ..)` method takes [`ssel1_loc::W`](W) writer structure"] +impl crate::Writable for Ssel1LocSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSEL1_LOC to value 0"] +impl crate::Resettable for Ssel1LocSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/swclk_pio0_10.rs b/rust-embedded/lpc111x-pac/src/iocon/swclk_pio0_10.rs new file mode 100644 index 0000000..69d94fc --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/swclk_pio0_10.rs @@ -0,0 +1,345 @@ +#[doc = "Register `SWCLK_PIO0_10` reader"] +pub type R = crate::R; +#[doc = "Register `SWCLK_PIO0_10` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function SWCLK."] + SelectsFunctionSwc = 0, + #[doc = "1: Selects function PIO0_10."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 147)."] + SelectsFunctionSck = 2, + #[doc = "3: Selects function CT16B0_MAT2."] + SelectsFunctionCt1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionSwc), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionSck), + 3 => Some(Func::SelectsFunctionCt1), + _ => None, + } + } + #[doc = "Selects function SWCLK."] + #[inline(always)] + pub fn is_selects_function_swc(&self) -> bool { + *self == Func::SelectsFunctionSwc + } + #[doc = "Selects function PIO0_10."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 147)."] + #[inline(always)] + pub fn is_selects_function_sck(&self) -> bool { + *self == Func::SelectsFunctionSck + } + #[doc = "Selects function CT16B0_MAT2."] + #[inline(always)] + pub fn is_selects_function_ct1(&self) -> bool { + *self == Func::SelectsFunctionCt1 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function SWCLK."] + #[inline(always)] + pub fn selects_function_swc(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSwc) + } + #[doc = "Selects function PIO0_10."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 147)."] + #[inline(always)] + pub fn selects_function_sck(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSck) + } + #[doc = "Selects function CT16B0_MAT2."] + #[inline(always)] + pub fn selects_function_ct1(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt1) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swclk_pio0_10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swclk_pio0_10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwclkPio0_10Spec; +impl crate::RegisterSpec for SwclkPio0_10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`swclk_pio0_10::R`](R) reader structure"] +impl crate::Readable for SwclkPio0_10Spec {} +#[doc = "`write(|w| ..)` method takes [`swclk_pio0_10::W`](W) writer structure"] +impl crate::Writable for SwclkPio0_10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SWCLK_PIO0_10 to value 0xd0"] +impl crate::Resettable for SwclkPio0_10Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/iocon/swdio_pio1_3.rs b/rust-embedded/lpc111x-pac/src/iocon/swdio_pio1_3.rs new file mode 100644 index 0000000..9a43891 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/iocon/swdio_pio1_3.rs @@ -0,0 +1,409 @@ +#[doc = "Register `SWDIO_PIO1_3` reader"] +pub type R = crate::R; +#[doc = "Register `SWDIO_PIO1_3` writer"] +pub type W = crate::W; +#[doc = "Selects pin function. All other values are reserved.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Func { + #[doc = "0: Selects function SWDIO."] + SelectsFunctionSwd = 0, + #[doc = "1: Selects function PIO1_3."] + SelectsFunctionPio = 1, + #[doc = "2: Selects function AD4."] + SelectsFunctionAd4 = 2, + #[doc = "3: Selects function CT32B1_MAT2."] + SelectsFunctionCt3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Func) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Func { + type Ux = u8; +} +#[doc = "Field `FUNC` reader - Selects pin function. All other values are reserved."] +pub type FuncR = crate::FieldReader; +impl FuncR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Func::SelectsFunctionSwd), + 1 => Some(Func::SelectsFunctionPio), + 2 => Some(Func::SelectsFunctionAd4), + 3 => Some(Func::SelectsFunctionCt3), + _ => None, + } + } + #[doc = "Selects function SWDIO."] + #[inline(always)] + pub fn is_selects_function_swd(&self) -> bool { + *self == Func::SelectsFunctionSwd + } + #[doc = "Selects function PIO1_3."] + #[inline(always)] + pub fn is_selects_function_pio(&self) -> bool { + *self == Func::SelectsFunctionPio + } + #[doc = "Selects function AD4."] + #[inline(always)] + pub fn is_selects_function_ad4(&self) -> bool { + *self == Func::SelectsFunctionAd4 + } + #[doc = "Selects function CT32B1_MAT2."] + #[inline(always)] + pub fn is_selects_function_ct3(&self) -> bool { + *self == Func::SelectsFunctionCt3 + } +} +#[doc = "Field `FUNC` writer - Selects pin function. All other values are reserved."] +pub type FuncW<'a, REG> = crate::FieldWriter<'a, REG, 3, Func>; +impl<'a, REG> FuncW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Selects function SWDIO."] + #[inline(always)] + pub fn selects_function_swd(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionSwd) + } + #[doc = "Selects function PIO1_3."] + #[inline(always)] + pub fn selects_function_pio(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionPio) + } + #[doc = "Selects function AD4."] + #[inline(always)] + pub fn selects_function_ad4(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionAd4) + } + #[doc = "Selects function CT32B1_MAT2."] + #[inline(always)] + pub fn selects_function_ct3(self) -> &'a mut crate::W { + self.variant(Func::SelectsFunctionCt3) + } +} +#[doc = "Selects function mode (on-chip pull-up/pull-down resistor control).\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Mode { + #[doc = "0: Inactive (no pull-down/pull-up resistor enabled)."] + InactiveNoPullDo = 0, + #[doc = "1: Pull-down resistor enabled."] + PullDownResistorE = 1, + #[doc = "2: Pull-up resistor enabled."] + PullUpResistorEna = 2, + #[doc = "3: Repeater mode."] + RepeaterMode_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Mode { + type Ux = u8; +} +#[doc = "Field `MODE` reader - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeR = crate::FieldReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + 0 => Mode::InactiveNoPullDo, + 1 => Mode::PullDownResistorE, + 2 => Mode::PullUpResistorEna, + 3 => Mode::RepeaterMode_, + _ => unreachable!(), + } + } + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn is_inactive_no_pull_do(&self) -> bool { + *self == Mode::InactiveNoPullDo + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn is_pull_down_resistor_e(&self) -> bool { + *self == Mode::PullDownResistorE + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn is_pull_up_resistor_ena(&self) -> bool { + *self == Mode::PullUpResistorEna + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn is_repeater_mode_(&self) -> bool { + *self == Mode::RepeaterMode_ + } +} +#[doc = "Field `MODE` writer - Selects function mode (on-chip pull-up/pull-down resistor control)."] +pub type ModeW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Inactive (no pull-down/pull-up resistor enabled)."] + #[inline(always)] + pub fn inactive_no_pull_do(self) -> &'a mut crate::W { + self.variant(Mode::InactiveNoPullDo) + } + #[doc = "Pull-down resistor enabled."] + #[inline(always)] + pub fn pull_down_resistor_e(self) -> &'a mut crate::W { + self.variant(Mode::PullDownResistorE) + } + #[doc = "Pull-up resistor enabled."] + #[inline(always)] + pub fn pull_up_resistor_ena(self) -> &'a mut crate::W { + self.variant(Mode::PullUpResistorEna) + } + #[doc = "Repeater mode."] + #[inline(always)] + pub fn repeater_mode_(self) -> &'a mut crate::W { + self.variant(Mode::RepeaterMode_) + } +} +#[doc = "Hysteresis.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Hys { + #[doc = "0: Disable."] + Disable_ = 0, + #[doc = "1: Enable."] + Enable_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Hys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `HYS` reader - Hysteresis."] +pub type HysR = crate::BitReader; +impl HysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Hys { + match self.bits { + false => Hys::Disable_, + true => Hys::Enable_, + } + } + #[doc = "Disable."] + #[inline(always)] + pub fn is_disable_(&self) -> bool { + *self == Hys::Disable_ + } + #[doc = "Enable."] + #[inline(always)] + pub fn is_enable_(&self) -> bool { + *self == Hys::Enable_ + } +} +#[doc = "Field `HYS` writer - Hysteresis."] +pub type HysW<'a, REG> = crate::BitWriter<'a, REG, Hys>; +impl<'a, REG> HysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable."] + #[inline(always)] + pub fn disable_(self) -> &'a mut crate::W { + self.variant(Hys::Disable_) + } + #[doc = "Enable."] + #[inline(always)] + pub fn enable_(self) -> &'a mut crate::W { + self.variant(Hys::Enable_) + } +} +#[doc = "Selects Analog/Digital mode\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Admode { + #[doc = "0: Analog input mode"] + AnalogInputMode = 0, + #[doc = "1: Digital functional mode"] + DigitalFunctionalM = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Admode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADMODE` reader - Selects Analog/Digital mode"] +pub type AdmodeR = crate::BitReader; +impl AdmodeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Admode { + match self.bits { + false => Admode::AnalogInputMode, + true => Admode::DigitalFunctionalM, + } + } + #[doc = "Analog input mode"] + #[inline(always)] + pub fn is_analog_input_mode(&self) -> bool { + *self == Admode::AnalogInputMode + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn is_digital_functional_m(&self) -> bool { + *self == Admode::DigitalFunctionalM + } +} +#[doc = "Field `ADMODE` writer - Selects Analog/Digital mode"] +pub type AdmodeW<'a, REG> = crate::BitWriter<'a, REG, Admode>; +impl<'a, REG> AdmodeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Analog input mode"] + #[inline(always)] + pub fn analog_input_mode(self) -> &'a mut crate::W { + self.variant(Admode::AnalogInputMode) + } + #[doc = "Digital functional mode"] + #[inline(always)] + pub fn digital_functional_m(self) -> &'a mut crate::W { + self.variant(Admode::DigitalFunctionalM) + } +} +#[doc = "Selects pseudo open-drain mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Od { + #[doc = "0: Standard GPIO output"] + StandardGpioOutput = 0, + #[doc = "1: Open-drain output"] + OpenDrainOutput = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Od) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OD` reader - Selects pseudo open-drain mode."] +pub type OdR = crate::BitReader; +impl OdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Od { + match self.bits { + false => Od::StandardGpioOutput, + true => Od::OpenDrainOutput, + } + } + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn is_standard_gpio_output(&self) -> bool { + *self == Od::StandardGpioOutput + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn is_open_drain_output(&self) -> bool { + *self == Od::OpenDrainOutput + } +} +#[doc = "Field `OD` writer - Selects pseudo open-drain mode."] +pub type OdW<'a, REG> = crate::BitWriter<'a, REG, Od>; +impl<'a, REG> OdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Standard GPIO output"] + #[inline(always)] + pub fn standard_gpio_output(self) -> &'a mut crate::W { + self.variant(Od::StandardGpioOutput) + } + #[doc = "Open-drain output"] + #[inline(always)] + pub fn open_drain_output(self) -> &'a mut crate::W { + self.variant(Od::OpenDrainOutput) + } +} +impl R { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + pub fn func(&self) -> FuncR { + FuncR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + pub fn hys(&self) -> HysR { + HysR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + pub fn admode(&self) -> AdmodeR { + AdmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + pub fn od(&self) -> OdR { + OdR::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects pin function. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn func(&mut self) -> FuncW { + FuncW::new(self, 0) + } + #[doc = "Bits 3:4 - Selects function mode (on-chip pull-up/pull-down resistor control)."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 3) + } + #[doc = "Bit 5 - Hysteresis."] + #[inline(always)] + #[must_use] + pub fn hys(&mut self) -> HysW { + HysW::new(self, 5) + } + #[doc = "Bit 7 - Selects Analog/Digital mode"] + #[inline(always)] + #[must_use] + pub fn admode(&mut self) -> AdmodeW { + AdmodeW::new(self, 7) + } + #[doc = "Bit 10 - Selects pseudo open-drain mode."] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OdW { + OdW::new(self, 10) + } +} +#[doc = "I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swdio_pio1_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swdio_pio1_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwdioPio1_3Spec; +impl crate::RegisterSpec for SwdioPio1_3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`swdio_pio1_3::R`](R) reader structure"] +impl crate::Readable for SwdioPio1_3Spec {} +#[doc = "`write(|w| ..)` method takes [`swdio_pio1_3::W`](W) writer structure"] +impl crate::Writable for SwdioPio1_3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SWDIO_PIO1_3 to value 0xd0"] +impl crate::Resettable for SwdioPio1_3Spec { + const RESET_VALUE: u32 = 0xd0; +} diff --git a/rust-embedded/lpc111x-pac/src/lib.rs b/rust-embedded/lpc111x-pac/src/lib.rs new file mode 100644 index 0000000..bd15a5f --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/lib.rs @@ -0,0 +1,1106 @@ +#![doc = "Peripheral access API for LPC111X microcontrollers (generated using svd2rust v0.32.0 (untracked))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn PIO0_0(); + fn PIO0_1(); + fn PIO0_2(); + fn PIO0_3(); + fn PIO0_4(); + fn PIO0_5(); + fn PIO0_6(); + fn PIO0_7(); + fn PIO0_8(); + fn PIO0_9(); + fn PIO0_10(); + fn PIO0_11(); + fn PIO1_0(); + fn SPI1(); + fn I2C(); + fn CT16B0(); + fn CT16B1(); + fn CT32B0(); + fn CT32B1(); + fn SPI0(); + fn UART(); + fn ADC(); + fn WDT(); + fn BOD(); + fn FMC(); + fn GPIO3(); + fn GPIO2(); + fn GPIO1(); + fn GPIO0(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 32] = [ + Vector { _handler: PIO0_0 }, + Vector { _handler: PIO0_1 }, + Vector { _handler: PIO0_2 }, + Vector { _handler: PIO0_3 }, + Vector { _handler: PIO0_4 }, + Vector { _handler: PIO0_5 }, + Vector { _handler: PIO0_6 }, + Vector { _handler: PIO0_7 }, + Vector { _handler: PIO0_8 }, + Vector { _handler: PIO0_9 }, + Vector { _handler: PIO0_10 }, + Vector { _handler: PIO0_11 }, + Vector { _handler: PIO1_0 }, + Vector { _reserved: 0 }, + Vector { _handler: SPI1 }, + Vector { _handler: I2C }, + Vector { _handler: CT16B0 }, + Vector { _handler: CT16B1 }, + Vector { _handler: CT32B0 }, + Vector { _handler: CT32B1 }, + Vector { _handler: SPI0 }, + Vector { _handler: UART }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: ADC }, + Vector { _handler: WDT }, + Vector { _handler: BOD }, + Vector { _handler: FMC }, + Vector { _handler: GPIO3 }, + Vector { _handler: GPIO2 }, + Vector { _handler: GPIO1 }, + Vector { _handler: GPIO0 }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - PIO0_0"] + PIO0_0 = 0, + #[doc = "1 - PIO0_1"] + PIO0_1 = 1, + #[doc = "2 - PIO0_2"] + PIO0_2 = 2, + #[doc = "3 - PIO0_3"] + PIO0_3 = 3, + #[doc = "4 - PIO0_4"] + PIO0_4 = 4, + #[doc = "5 - PIO0_5"] + PIO0_5 = 5, + #[doc = "6 - PIO0_6"] + PIO0_6 = 6, + #[doc = "7 - PIO0_7"] + PIO0_7 = 7, + #[doc = "8 - PIO0_8"] + PIO0_8 = 8, + #[doc = "9 - PIO0_9"] + PIO0_9 = 9, + #[doc = "10 - PIO0_10"] + PIO0_10 = 10, + #[doc = "11 - PIO0_11"] + PIO0_11 = 11, + #[doc = "12 - PIO1_0"] + PIO1_0 = 12, + #[doc = "14 - SPI1"] + SPI1 = 14, + #[doc = "15 - I2C"] + I2C = 15, + #[doc = "16 - CT16B0"] + CT16B0 = 16, + #[doc = "17 - CT16B1"] + CT16B1 = 17, + #[doc = "18 - CT32B0"] + CT32B0 = 18, + #[doc = "19 - CT32B1"] + CT32B1 = 19, + #[doc = "20 - SPI0"] + SPI0 = 20, + #[doc = "21 - UART"] + UART = 21, + #[doc = "24 - ADC"] + ADC = 24, + #[doc = "25 - WDT"] + WDT = 25, + #[doc = "26 - BOD"] + BOD = 26, + #[doc = "27 - FMC"] + FMC = 27, + #[doc = "28 - GPIO3"] + GPIO3 = 28, + #[doc = "29 - GPIO2"] + GPIO2 = 29, + #[doc = "30 - GPIO1"] + GPIO1 = 30, + #[doc = "31 - GPIO0"] + GPIO0 = 31, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "I2C-bus interface"] +pub struct I2c { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2c {} +impl I2c { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2c { + type Target = i2c::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2c { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c").finish() + } +} +#[doc = "I2C-bus interface"] +pub mod i2c; +#[doc = "Windowed WatchDog Timer (WDT)"] +pub struct Wwdt { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Wwdt {} +impl Wwdt { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wwdt::RegisterBlock = 0x4000_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wwdt::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Wwdt { + type Target = wwdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Wwdt { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Wwdt").finish() + } +} +#[doc = "Windowed WatchDog Timer (WDT)"] +pub mod wwdt; +#[doc = "UART"] +pub struct Uart { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Uart {} +impl Uart { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Uart { + type Target = uart::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Uart { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart").finish() + } +} +#[doc = "UART"] +pub mod uart; +#[doc = "16-bit counter/timer CT16B0/1"] +pub struct Ct16b0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Ct16b0 {} +impl Ct16b0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ct16b0::RegisterBlock = 0x4000_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ct16b0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Ct16b0 { + type Target = ct16b0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Ct16b0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ct16b0").finish() + } +} +#[doc = "16-bit counter/timer CT16B0/1"] +pub mod ct16b0; +#[doc = "16-bit counter/timer CT16B0/1"] +pub struct Ct16b1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Ct16b1 {} +impl Ct16b1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ct16b0::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ct16b0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Ct16b1 { + type Target = ct16b0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Ct16b1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ct16b1").finish() + } +} +#[doc = "16-bit counter/timer CT16B0/1"] +pub use self::ct16b0 as ct16b1; +#[doc = "32-bit counter/timer CT32B0/1"] +pub struct Ct32b0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Ct32b0 {} +impl Ct32b0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ct32b0::RegisterBlock = 0x4001_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ct32b0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Ct32b0 { + type Target = ct32b0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Ct32b0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ct32b0").finish() + } +} +#[doc = "32-bit counter/timer CT32B0/1"] +pub mod ct32b0; +#[doc = "32-bit counter/timer CT32B0/1"] +pub struct Ct32b1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Ct32b1 {} +impl Ct32b1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ct32b0::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ct32b0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Ct32b1 { + type Target = ct32b0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Ct32b1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ct32b1").finish() + } +} +#[doc = "32-bit counter/timer CT32B0/1"] +pub use self::ct32b0 as ct32b1; +#[doc = "10-bit ADC"] +pub struct Adc { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Adc {} +impl Adc { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4001_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Adc { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Adc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc").finish() + } +} +#[doc = "10-bit ADC"] +pub mod adc; +#[doc = "Power management unit"] +pub struct Pmu { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Pmu {} +impl Pmu { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pmu::RegisterBlock = 0x4003_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pmu::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Pmu { + type Target = pmu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Pmu { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Pmu").finish() + } +} +#[doc = "Power management unit"] +pub mod pmu; +#[doc = "Flash programming firmware"] +pub struct Flashctrl { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Flashctrl {} +impl Flashctrl { + #[doc = r"Pointer to the register block"] + pub const PTR: *const flashctrl::RegisterBlock = 0x4003_c000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const flashctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Flashctrl { + type Target = flashctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Flashctrl { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Flashctrl").finish() + } +} +#[doc = "Flash programming firmware"] +pub mod flashctrl; +#[doc = "SPI0"] +pub struct Spi0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi0 {} +impl Spi0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4004_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi0").finish() + } +} +#[doc = "SPI0"] +pub mod spi0; +#[doc = "I/O configuration (IOCONFIG)"] +pub struct Iocon { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Iocon {} +impl Iocon { + #[doc = r"Pointer to the register block"] + pub const PTR: *const iocon::RegisterBlock = 0x4004_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const iocon::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Iocon { + type Target = iocon::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Iocon { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Iocon").finish() + } +} +#[doc = "I/O configuration (IOCONFIG)"] +pub mod iocon; +#[doc = "System configuration (SYSCON)"] +pub struct Syscon { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Syscon {} +impl Syscon { + #[doc = r"Pointer to the register block"] + pub const PTR: *const syscon::RegisterBlock = 0x4004_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const syscon::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Syscon { + type Target = syscon::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Syscon { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Syscon").finish() + } +} +#[doc = "System configuration (SYSCON)"] +pub mod syscon; +#[doc = "SPI0"] +pub struct Spi1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi1 {} +impl Spi1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4005_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi1").finish() + } +} +#[doc = "SPI0"] +pub use self::spi0 as spi1; +#[doc = "GPIO0"] +pub struct Gpio0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Gpio0 {} +impl Gpio0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio0::RegisterBlock = 0x5000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Gpio0 { + type Target = gpio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Gpio0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio0").finish() + } +} +#[doc = "GPIO0"] +pub mod gpio0; +#[doc = "GPIO0"] +pub struct Gpio1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Gpio1 {} +impl Gpio1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio0::RegisterBlock = 0x5001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Gpio1 { + type Target = gpio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Gpio1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio1").finish() + } +} +#[doc = "GPIO0"] +pub use self::gpio0 as gpio1; +#[doc = "GPIO0"] +pub struct Gpio2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Gpio2 {} +impl Gpio2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio0::RegisterBlock = 0x5002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Gpio2 { + type Target = gpio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Gpio2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio2").finish() + } +} +#[doc = "GPIO0"] +pub use self::gpio0 as gpio2; +#[doc = "GPIO0"] +pub struct Gpio3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Gpio3 {} +impl Gpio3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gpio0::RegisterBlock = 0x5003_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gpio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Gpio3 { + type Target = gpio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Gpio3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Gpio3").finish() + } +} +#[doc = "GPIO0"] +pub use self::gpio0 as gpio3; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "I2C"] + pub i2c: I2c, + #[doc = "WWDT"] + pub wwdt: Wwdt, + #[doc = "UART"] + pub uart: Uart, + #[doc = "CT16B0"] + pub ct16b0: Ct16b0, + #[doc = "CT16B1"] + pub ct16b1: Ct16b1, + #[doc = "CT32B0"] + pub ct32b0: Ct32b0, + #[doc = "CT32B1"] + pub ct32b1: Ct32b1, + #[doc = "ADC"] + pub adc: Adc, + #[doc = "PMU"] + pub pmu: Pmu, + #[doc = "FLASHCTRL"] + pub flashctrl: Flashctrl, + #[doc = "SPI0"] + pub spi0: Spi0, + #[doc = "IOCON"] + pub iocon: Iocon, + #[doc = "SYSCON"] + pub syscon: Syscon, + #[doc = "SPI1"] + pub spi1: Spi1, + #[doc = "GPIO0"] + pub gpio0: Gpio0, + #[doc = "GPIO1"] + pub gpio1: Gpio1, + #[doc = "GPIO2"] + pub gpio2: Gpio2, + #[doc = "GPIO3"] + pub gpio3: Gpio3, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + i2c: I2c { + _marker: PhantomData, + }, + wwdt: Wwdt { + _marker: PhantomData, + }, + uart: Uart { + _marker: PhantomData, + }, + ct16b0: Ct16b0 { + _marker: PhantomData, + }, + ct16b1: Ct16b1 { + _marker: PhantomData, + }, + ct32b0: Ct32b0 { + _marker: PhantomData, + }, + ct32b1: Ct32b1 { + _marker: PhantomData, + }, + adc: Adc { + _marker: PhantomData, + }, + pmu: Pmu { + _marker: PhantomData, + }, + flashctrl: Flashctrl { + _marker: PhantomData, + }, + spi0: Spi0 { + _marker: PhantomData, + }, + iocon: Iocon { + _marker: PhantomData, + }, + syscon: Syscon { + _marker: PhantomData, + }, + spi1: Spi1 { + _marker: PhantomData, + }, + gpio0: Gpio0 { + _marker: PhantomData, + }, + gpio1: Gpio1 { + _marker: PhantomData, + }, + gpio2: Gpio2 { + _marker: PhantomData, + }, + gpio3: Gpio3 { + _marker: PhantomData, + }, + } + } +} diff --git a/rust-embedded/lpc111x-pac/src/pmu.rs b/rust-embedded/lpc111x-pac/src/pmu.rs new file mode 100644 index 0000000..cc6836f --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/pmu.rs @@ -0,0 +1,48 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + pcon: Pcon, + gpreg: [Gpreg; 4], + gpreg4: Gpreg4, +} +impl RegisterBlock { + #[doc = "0x00 - Power control register"] + #[inline(always)] + pub const fn pcon(&self) -> &Pcon { + &self.pcon + } + #[doc = "0x04..0x14 - General purpose register"] + #[inline(always)] + pub const fn gpreg(&self, n: usize) -> &Gpreg { + &self.gpreg[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x04..0x14 - General purpose register"] + #[inline(always)] + pub fn gpreg_iter(&self) -> impl Iterator { + self.gpreg.iter() + } + #[doc = "0x14 - General purpose register 4"] + #[inline(always)] + pub const fn gpreg4(&self) -> &Gpreg4 { + &self.gpreg4 + } +} +#[doc = "PCON (rw) register accessor: Power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcon::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcon::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pcon`] +module"] +#[doc(alias = "PCON")] +pub type Pcon = crate::Reg; +#[doc = "Power control register"] +pub mod pcon; +#[doc = "GPREG (rw) register accessor: General purpose register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpreg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpreg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpreg`] +module"] +#[doc(alias = "GPREG")] +pub type Gpreg = crate::Reg; +#[doc = "General purpose register"] +pub mod gpreg; +#[doc = "GPREG4 (rw) register accessor: General purpose register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpreg4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpreg4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpreg4`] +module"] +#[doc(alias = "GPREG4")] +pub type Gpreg4 = crate::Reg; +#[doc = "General purpose register 4"] +pub mod gpreg4; diff --git a/rust-embedded/lpc111x-pac/src/pmu/gpreg.rs b/rust-embedded/lpc111x-pac/src/pmu/gpreg.rs new file mode 100644 index 0000000..5614045 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/pmu/gpreg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `GPREG%s` reader"] +pub type R = crate::R; +#[doc = "Register `GPREG%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPDATA` reader - Data retained during Deep power-down mode."] +pub type GpdataR = crate::FieldReader; +#[doc = "Field `GPDATA` writer - Data retained during Deep power-down mode."] +pub type GpdataW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data retained during Deep power-down mode."] + #[inline(always)] + pub fn gpdata(&self) -> GpdataR { + GpdataR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data retained during Deep power-down mode."] + #[inline(always)] + #[must_use] + pub fn gpdata(&mut self) -> GpdataW { + GpdataW::new(self, 0) + } +} +#[doc = "General purpose register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpreg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GpregSpec; +impl crate::RegisterSpec for GpregSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpreg::R`](R) reader structure"] +impl crate::Readable for GpregSpec {} +#[doc = "`write(|w| ..)` method takes [`gpreg::W`](W) writer structure"] +impl crate::Writable for GpregSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPREG%s to value 0"] +impl crate::Resettable for GpregSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/pmu/gpreg4.rs b/rust-embedded/lpc111x-pac/src/pmu/gpreg4.rs new file mode 100644 index 0000000..08a65ad --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/pmu/gpreg4.rs @@ -0,0 +1,104 @@ +#[doc = "Register `GPREG4` reader"] +pub type R = crate::R; +#[doc = "Register `GPREG4` writer"] +pub type W = crate::W; +#[doc = "WAKEUP pin hysteresis enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wakeuphys { + #[doc = "1: Hysteresis for WAKEUP pin enabled."] + Enabled = 1, + #[doc = "0: Hysteresis for WAKUP pin disabled."] + Disabled = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wakeuphys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WAKEUPHYS` reader - WAKEUP pin hysteresis enable"] +pub type WakeuphysR = crate::BitReader; +impl WakeuphysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wakeuphys { + match self.bits { + true => Wakeuphys::Enabled, + false => Wakeuphys::Disabled, + } + } + #[doc = "Hysteresis for WAKEUP pin enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Wakeuphys::Enabled + } + #[doc = "Hysteresis for WAKUP pin disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Wakeuphys::Disabled + } +} +#[doc = "Field `WAKEUPHYS` writer - WAKEUP pin hysteresis enable"] +pub type WakeuphysW<'a, REG> = crate::BitWriter<'a, REG, Wakeuphys>; +impl<'a, REG> WakeuphysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Hysteresis for WAKEUP pin enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Wakeuphys::Enabled) + } + #[doc = "Hysteresis for WAKUP pin disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Wakeuphys::Disabled) + } +} +#[doc = "Field `GPDATA` reader - Data retained during Deep power-down mode."] +pub type GpdataR = crate::FieldReader; +#[doc = "Field `GPDATA` writer - Data retained during Deep power-down mode."] +pub type GpdataW<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>; +impl R { + #[doc = "Bit 10 - WAKEUP pin hysteresis enable"] + #[inline(always)] + pub fn wakeuphys(&self) -> WakeuphysR { + WakeuphysR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 11:31 - Data retained during Deep power-down mode."] + #[inline(always)] + pub fn gpdata(&self) -> GpdataR { + GpdataR::new((self.bits >> 11) & 0x001f_ffff) + } +} +impl W { + #[doc = "Bit 10 - WAKEUP pin hysteresis enable"] + #[inline(always)] + #[must_use] + pub fn wakeuphys(&mut self) -> WakeuphysW { + WakeuphysW::new(self, 10) + } + #[doc = "Bits 11:31 - Data retained during Deep power-down mode."] + #[inline(always)] + #[must_use] + pub fn gpdata(&mut self) -> GpdataW { + GpdataW::new(self, 11) + } +} +#[doc = "General purpose register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpreg4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpreg4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Gpreg4Spec; +impl crate::RegisterSpec for Gpreg4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpreg4::R`](R) reader structure"] +impl crate::Readable for Gpreg4Spec {} +#[doc = "`write(|w| ..)` method takes [`gpreg4::W`](W) writer structure"] +impl crate::Writable for Gpreg4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPREG4 to value 0"] +impl crate::Resettable for Gpreg4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/pmu/pcon.rs b/rust-embedded/lpc111x-pac/src/pmu/pcon.rs new file mode 100644 index 0000000..eb9d464 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/pmu/pcon.rs @@ -0,0 +1,217 @@ +#[doc = "Register `PCON` reader"] +pub type R = crate::R; +#[doc = "Register `PCON` writer"] +pub type W = crate::W; +#[doc = "Deep power-down mode enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dpden { + #[doc = "0: ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off)."] + Sleepmode = 0, + #[doc = "1: ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)."] + Deeppowerdown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dpden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPDEN` reader - Deep power-down mode enable"] +pub type DpdenR = crate::BitReader; +impl DpdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dpden { + match self.bits { + false => Dpden::Sleepmode, + true => Dpden::Deeppowerdown, + } + } + #[doc = "ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off)."] + #[inline(always)] + pub fn is_sleepmode(&self) -> bool { + *self == Dpden::Sleepmode + } + #[doc = "ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)."] + #[inline(always)] + pub fn is_deeppowerdown(&self) -> bool { + *self == Dpden::Deeppowerdown + } +} +#[doc = "Field `DPDEN` writer - Deep power-down mode enable"] +pub type DpdenW<'a, REG> = crate::BitWriter<'a, REG, Dpden>; +impl<'a, REG> DpdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off)."] + #[inline(always)] + pub fn sleepmode(self) -> &'a mut crate::W { + self.variant(Dpden::Sleepmode) + } + #[doc = "ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down)."] + #[inline(always)] + pub fn deeppowerdown(self) -> &'a mut crate::W { + self.variant(Dpden::Deeppowerdown) + } +} +#[doc = "Sleep mode flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sleepflag { + #[doc = "0: Read: No power-down mode entered. LPC111x is in Active mode. Write: No effect."] + Nopowerdown = 0, + #[doc = "1: Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0."] + Powerdown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sleepflag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLEEPFLAG` reader - Sleep mode flag"] +pub type SleepflagR = crate::BitReader; +impl SleepflagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sleepflag { + match self.bits { + false => Sleepflag::Nopowerdown, + true => Sleepflag::Powerdown, + } + } + #[doc = "Read: No power-down mode entered. LPC111x is in Active mode. Write: No effect."] + #[inline(always)] + pub fn is_nopowerdown(&self) -> bool { + *self == Sleepflag::Nopowerdown + } + #[doc = "Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0."] + #[inline(always)] + pub fn is_powerdown(&self) -> bool { + *self == Sleepflag::Powerdown + } +} +#[doc = "Field `SLEEPFLAG` writer - Sleep mode flag"] +pub type SleepflagW<'a, REG> = crate::BitWriter<'a, REG, Sleepflag>; +impl<'a, REG> SleepflagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read: No power-down mode entered. LPC111x is in Active mode. Write: No effect."] + #[inline(always)] + pub fn nopowerdown(self) -> &'a mut crate::W { + self.variant(Sleepflag::Nopowerdown) + } + #[doc = "Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0."] + #[inline(always)] + pub fn powerdown(self) -> &'a mut crate::W { + self.variant(Sleepflag::Powerdown) + } +} +#[doc = "Deep power-down flag\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dpdflag { + #[doc = "0: Read: Deep power-down mode not entered. Write: No effect."] + Nodeeppowerdown = 0, + #[doc = "1: Read: Deep power-down mode entered. Write: Clear the Deep power-down flag."] + Deeppowerdown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dpdflag) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DPDFLAG` reader - Deep power-down flag"] +pub type DpdflagR = crate::BitReader; +impl DpdflagR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dpdflag { + match self.bits { + false => Dpdflag::Nodeeppowerdown, + true => Dpdflag::Deeppowerdown, + } + } + #[doc = "Read: Deep power-down mode not entered. Write: No effect."] + #[inline(always)] + pub fn is_nodeeppowerdown(&self) -> bool { + *self == Dpdflag::Nodeeppowerdown + } + #[doc = "Read: Deep power-down mode entered. Write: Clear the Deep power-down flag."] + #[inline(always)] + pub fn is_deeppowerdown(&self) -> bool { + *self == Dpdflag::Deeppowerdown + } +} +#[doc = "Field `DPDFLAG` writer - Deep power-down flag"] +pub type DpdflagW<'a, REG> = crate::BitWriter<'a, REG, Dpdflag>; +impl<'a, REG> DpdflagW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Read: Deep power-down mode not entered. Write: No effect."] + #[inline(always)] + pub fn nodeeppowerdown(self) -> &'a mut crate::W { + self.variant(Dpdflag::Nodeeppowerdown) + } + #[doc = "Read: Deep power-down mode entered. Write: Clear the Deep power-down flag."] + #[inline(always)] + pub fn deeppowerdown(self) -> &'a mut crate::W { + self.variant(Dpdflag::Deeppowerdown) + } +} +impl R { + #[doc = "Bit 1 - Deep power-down mode enable"] + #[inline(always)] + pub fn dpden(&self) -> DpdenR { + DpdenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Sleep mode flag"] + #[inline(always)] + pub fn sleepflag(&self) -> SleepflagR { + SleepflagR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 11 - Deep power-down flag"] + #[inline(always)] + pub fn dpdflag(&self) -> DpdflagR { + DpdflagR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Deep power-down mode enable"] + #[inline(always)] + #[must_use] + pub fn dpden(&mut self) -> DpdenW { + DpdenW::new(self, 1) + } + #[doc = "Bit 8 - Sleep mode flag"] + #[inline(always)] + #[must_use] + pub fn sleepflag(&mut self) -> SleepflagW { + SleepflagW::new(self, 8) + } + #[doc = "Bit 11 - Deep power-down flag"] + #[inline(always)] + #[must_use] + pub fn dpdflag(&mut self) -> DpdflagW { + DpdflagW::new(self, 11) + } +} +#[doc = "Power control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcon::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcon::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PconSpec; +impl crate::RegisterSpec for PconSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pcon::R`](R) reader structure"] +impl crate::Readable for PconSpec {} +#[doc = "`write(|w| ..)` method takes [`pcon::W`](W) writer structure"] +impl crate::Writable for PconSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PCON to value 0"] +impl crate::Resettable for PconSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0.rs b/rust-embedded/lpc111x-pac/src/spi0.rs new file mode 100644 index 0000000..718c34d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0.rs @@ -0,0 +1,114 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cr0: Cr0, + cr1: Cr1, + dr: Dr, + sr: Sr, + cpsr: Cpsr, + imsc: Imsc, + ris: Ris, + mis: Mis, + icr: Icr, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0. Selects the serial clock rate, bus type, and data size."] + #[inline(always)] + pub const fn cr0(&self) -> &Cr0 { + &self.cr0 + } + #[doc = "0x04 - Control Register 1. Selects master/slave and other modes."] + #[inline(always)] + pub const fn cr1(&self) -> &Cr1 { + &self.cr1 + } + #[doc = "0x08 - Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."] + #[inline(always)] + pub const fn dr(&self) -> &Dr { + &self.dr + } + #[doc = "0x0c - Status Register"] + #[inline(always)] + pub const fn sr(&self) -> &Sr { + &self.sr + } + #[doc = "0x10 - Clock Prescale Register"] + #[inline(always)] + pub const fn cpsr(&self) -> &Cpsr { + &self.cpsr + } + #[doc = "0x14 - Interrupt Mask Set and Clear Register"] + #[inline(always)] + pub const fn imsc(&self) -> &Imsc { + &self.imsc + } + #[doc = "0x18 - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn ris(&self) -> &Ris { + &self.ris + } + #[doc = "0x1c - Masked Interrupt Status Register"] + #[inline(always)] + pub const fn mis(&self) -> &Mis { + &self.mis + } + #[doc = "0x20 - SSPICR Interrupt Clear Register"] + #[inline(always)] + pub const fn icr(&self) -> &Icr { + &self.icr + } +} +#[doc = "CR0 (rw) register accessor: Control Register 0. Selects the serial clock rate, bus type, and data size.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr0`] +module"] +#[doc(alias = "CR0")] +pub type Cr0 = crate::Reg; +#[doc = "Control Register 0. Selects the serial clock rate, bus type, and data size."] +pub mod cr0; +#[doc = "CR1 (rw) register accessor: Control Register 1. Selects master/slave and other modes.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr1`] +module"] +#[doc(alias = "CR1")] +pub type Cr1 = crate::Reg; +#[doc = "Control Register 1. Selects master/slave and other modes."] +pub mod cr1; +#[doc = "DR (rw) register accessor: Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. WARN: The register is **modified** in some way after a read operation. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`] +module"] +#[doc(alias = "DR")] +pub type Dr = crate::Reg; +#[doc = "Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO."] +pub mod dr; +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`] +module"] +#[doc(alias = "SR")] +pub type Sr = crate::Reg; +#[doc = "Status Register"] +pub mod sr; +#[doc = "CPSR (rw) register accessor: Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsr`] +module"] +#[doc(alias = "CPSR")] +pub type Cpsr = crate::Reg; +#[doc = "Clock Prescale Register"] +pub mod cpsr; +#[doc = "IMSC (rw) register accessor: Interrupt Mask Set and Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imsc`] +module"] +#[doc(alias = "IMSC")] +pub type Imsc = crate::Reg; +#[doc = "Interrupt Mask Set and Clear Register"] +pub mod imsc; +#[doc = "RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`] +module"] +#[doc(alias = "RIS")] +pub type Ris = crate::Reg; +#[doc = "Raw Interrupt Status Register"] +pub mod ris; +#[doc = "MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`] +module"] +#[doc(alias = "MIS")] +pub type Mis = crate::Reg; +#[doc = "Masked Interrupt Status Register"] +pub mod mis; +#[doc = "ICR (w) register accessor: SSPICR Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] +module"] +#[doc(alias = "ICR")] +pub type Icr = crate::Reg; +#[doc = "SSPICR Interrupt Clear Register"] +pub mod icr; diff --git a/rust-embedded/lpc111x-pac/src/spi0/cpsr.rs b/rust-embedded/lpc111x-pac/src/spi0/cpsr.rs new file mode 100644 index 0000000..31e60f0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/cpsr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CPSR` reader"] +pub type R = crate::R; +#[doc = "Register `CPSR` writer"] +pub type W = crate::W; +#[doc = "Field `CPSDVSR` reader - This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."] +pub type CpsdvsrR = crate::FieldReader; +#[doc = "Field `CPSDVSR` writer - This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."] +pub type CpsdvsrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CpsdvsrR { + CpsdvsrR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CpsdvsrW { + CpsdvsrW::new(self, 0) + } +} +#[doc = "Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CpsrSpec; +impl crate::RegisterSpec for CpsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpsr::R`](R) reader structure"] +impl crate::Readable for CpsrSpec {} +#[doc = "`write(|w| ..)` method takes [`cpsr::W`](W) writer structure"] +impl crate::Writable for CpsrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CPSR to value 0"] +impl crate::Resettable for CpsrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/cr0.rs b/rust-embedded/lpc111x-pac/src/spi0/cr0.rs new file mode 100644 index 0000000..aa5a1d4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/cr0.rs @@ -0,0 +1,464 @@ +#[doc = "Register `CR0` reader"] +pub type R = crate::R; +#[doc = "Register `CR0` writer"] +pub type W = crate::W; +#[doc = "Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Dss { + #[doc = "3: 4-bit transfer"] + _4BitTransfer = 3, + #[doc = "4: 5-bit transfer"] + _5BitTransfer = 4, + #[doc = "5: 6-bit transfer"] + _6BitTransfer = 5, + #[doc = "6: 7-bit transfer"] + _7BitTransfer = 6, + #[doc = "7: 8-bit transfer"] + _8BitTransfer = 7, + #[doc = "8: 9-bit transfer"] + _9BitTransfer = 8, + #[doc = "9: 10-bit transfer"] + _10BitTransfer = 9, + #[doc = "10: 11-bit transfer"] + _11BitTransfer = 10, + #[doc = "11: 12-bit transfer"] + _12BitTransfer = 11, + #[doc = "12: 13-bit transfer"] + _13BitTransfer = 12, + #[doc = "13: 14-bit transfer"] + _14BitTransfer = 13, + #[doc = "14: 15-bit transfer"] + _15BitTransfer = 14, + #[doc = "15: 16-bit transfer"] + _16BitTransfer = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Dss) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Dss { + type Ux = u8; +} +#[doc = "Field `DSS` reader - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."] +pub type DssR = crate::FieldReader; +impl DssR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 3 => Some(Dss::_4BitTransfer), + 4 => Some(Dss::_5BitTransfer), + 5 => Some(Dss::_6BitTransfer), + 6 => Some(Dss::_7BitTransfer), + 7 => Some(Dss::_8BitTransfer), + 8 => Some(Dss::_9BitTransfer), + 9 => Some(Dss::_10BitTransfer), + 10 => Some(Dss::_11BitTransfer), + 11 => Some(Dss::_12BitTransfer), + 12 => Some(Dss::_13BitTransfer), + 13 => Some(Dss::_14BitTransfer), + 14 => Some(Dss::_15BitTransfer), + 15 => Some(Dss::_16BitTransfer), + _ => None, + } + } + #[doc = "4-bit transfer"] + #[inline(always)] + pub fn is_4_bit_transfer(&self) -> bool { + *self == Dss::_4BitTransfer + } + #[doc = "5-bit transfer"] + #[inline(always)] + pub fn is_5_bit_transfer(&self) -> bool { + *self == Dss::_5BitTransfer + } + #[doc = "6-bit transfer"] + #[inline(always)] + pub fn is_6_bit_transfer(&self) -> bool { + *self == Dss::_6BitTransfer + } + #[doc = "7-bit transfer"] + #[inline(always)] + pub fn is_7_bit_transfer(&self) -> bool { + *self == Dss::_7BitTransfer + } + #[doc = "8-bit transfer"] + #[inline(always)] + pub fn is_8_bit_transfer(&self) -> bool { + *self == Dss::_8BitTransfer + } + #[doc = "9-bit transfer"] + #[inline(always)] + pub fn is_9_bit_transfer(&self) -> bool { + *self == Dss::_9BitTransfer + } + #[doc = "10-bit transfer"] + #[inline(always)] + pub fn is_10_bit_transfer(&self) -> bool { + *self == Dss::_10BitTransfer + } + #[doc = "11-bit transfer"] + #[inline(always)] + pub fn is_11_bit_transfer(&self) -> bool { + *self == Dss::_11BitTransfer + } + #[doc = "12-bit transfer"] + #[inline(always)] + pub fn is_12_bit_transfer(&self) -> bool { + *self == Dss::_12BitTransfer + } + #[doc = "13-bit transfer"] + #[inline(always)] + pub fn is_13_bit_transfer(&self) -> bool { + *self == Dss::_13BitTransfer + } + #[doc = "14-bit transfer"] + #[inline(always)] + pub fn is_14_bit_transfer(&self) -> bool { + *self == Dss::_14BitTransfer + } + #[doc = "15-bit transfer"] + #[inline(always)] + pub fn is_15_bit_transfer(&self) -> bool { + *self == Dss::_15BitTransfer + } + #[doc = "16-bit transfer"] + #[inline(always)] + pub fn is_16_bit_transfer(&self) -> bool { + *self == Dss::_16BitTransfer + } +} +#[doc = "Field `DSS` writer - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."] +pub type DssW<'a, REG> = crate::FieldWriter<'a, REG, 4, Dss>; +impl<'a, REG> DssW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "4-bit transfer"] + #[inline(always)] + pub fn _4_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_4BitTransfer) + } + #[doc = "5-bit transfer"] + #[inline(always)] + pub fn _5_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_5BitTransfer) + } + #[doc = "6-bit transfer"] + #[inline(always)] + pub fn _6_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_6BitTransfer) + } + #[doc = "7-bit transfer"] + #[inline(always)] + pub fn _7_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_7BitTransfer) + } + #[doc = "8-bit transfer"] + #[inline(always)] + pub fn _8_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_8BitTransfer) + } + #[doc = "9-bit transfer"] + #[inline(always)] + pub fn _9_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_9BitTransfer) + } + #[doc = "10-bit transfer"] + #[inline(always)] + pub fn _10_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_10BitTransfer) + } + #[doc = "11-bit transfer"] + #[inline(always)] + pub fn _11_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_11BitTransfer) + } + #[doc = "12-bit transfer"] + #[inline(always)] + pub fn _12_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_12BitTransfer) + } + #[doc = "13-bit transfer"] + #[inline(always)] + pub fn _13_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_13BitTransfer) + } + #[doc = "14-bit transfer"] + #[inline(always)] + pub fn _14_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_14BitTransfer) + } + #[doc = "15-bit transfer"] + #[inline(always)] + pub fn _15_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_15BitTransfer) + } + #[doc = "16-bit transfer"] + #[inline(always)] + pub fn _16_bit_transfer(self) -> &'a mut crate::W { + self.variant(Dss::_16BitTransfer) + } +} +#[doc = "Frame Format.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Frf { + #[doc = "0: SPI"] + Spi = 0, + #[doc = "1: TI"] + Ti = 1, + #[doc = "2: Microwire"] + Microwire = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Frf) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Frf { + type Ux = u8; +} +#[doc = "Field `FRF` reader - Frame Format."] +pub type FrfR = crate::FieldReader; +impl FrfR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Frf { + match self.bits { + 0 => Frf::Spi, + 1 => Frf::Ti, + 2 => Frf::Microwire, + _ => unreachable!(), + } + } + #[doc = "SPI"] + #[inline(always)] + pub fn is_spi(&self) -> bool { + *self == Frf::Spi + } + #[doc = "TI"] + #[inline(always)] + pub fn is_ti(&self) -> bool { + *self == Frf::Ti + } + #[doc = "Microwire"] + #[inline(always)] + pub fn is_microwire(&self) -> bool { + *self == Frf::Microwire + } +} +#[doc = "Field `FRF` writer - Frame Format."] +pub type FrfW<'a, REG> = crate::FieldWriter<'a, REG, 2, Frf>; +impl<'a, REG> FrfW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "SPI"] + #[inline(always)] + pub fn spi(self) -> &'a mut crate::W { + self.variant(Frf::Spi) + } + #[doc = "TI"] + #[inline(always)] + pub fn ti(self) -> &'a mut crate::W { + self.variant(Frf::Ti) + } + #[doc = "Microwire"] + #[inline(always)] + pub fn microwire(self) -> &'a mut crate::W { + self.variant(Frf::Microwire) + } +} +#[doc = "Clock Out Polarity. This bit is only used in SPI mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpol { + #[doc = "0: SPI controller maintains the bus clock low between frames."] + Low = 0, + #[doc = "1: SPI controller maintains the bus clock high between frames."] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpol) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPOL` reader - Clock Out Polarity. This bit is only used in SPI mode."] +pub type CpolR = crate::BitReader; +impl CpolR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpol { + match self.bits { + false => Cpol::Low, + true => Cpol::High, + } + } + #[doc = "SPI controller maintains the bus clock low between frames."] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Cpol::Low + } + #[doc = "SPI controller maintains the bus clock high between frames."] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Cpol::High + } +} +#[doc = "Field `CPOL` writer - Clock Out Polarity. This bit is only used in SPI mode."] +pub type CpolW<'a, REG> = crate::BitWriter<'a, REG, Cpol>; +impl<'a, REG> CpolW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPI controller maintains the bus clock low between frames."] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Cpol::Low) + } + #[doc = "SPI controller maintains the bus clock high between frames."] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Cpol::High) + } +} +#[doc = "Clock Out Phase. This bit is only used in SPI mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Cpha { + #[doc = "0: SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."] + Firstclock = 0, + #[doc = "1: SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."] + Secondclock = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Cpha) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CPHA` reader - Clock Out Phase. This bit is only used in SPI mode."] +pub type CphaR = crate::BitReader; +impl CphaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Cpha { + match self.bits { + false => Cpha::Firstclock, + true => Cpha::Secondclock, + } + } + #[doc = "SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."] + #[inline(always)] + pub fn is_firstclock(&self) -> bool { + *self == Cpha::Firstclock + } + #[doc = "SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."] + #[inline(always)] + pub fn is_secondclock(&self) -> bool { + *self == Cpha::Secondclock + } +} +#[doc = "Field `CPHA` writer - Clock Out Phase. This bit is only used in SPI mode."] +pub type CphaW<'a, REG> = crate::BitWriter<'a, REG, Cpha>; +impl<'a, REG> CphaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line."] + #[inline(always)] + pub fn firstclock(self) -> &'a mut crate::W { + self.variant(Cpha::Firstclock) + } + #[doc = "SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line."] + #[inline(always)] + pub fn secondclock(self) -> &'a mut crate::W { + self.variant(Cpha::Secondclock) + } +} +#[doc = "Field `SCR` reader - Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."] +pub type ScrR = crate::FieldReader; +#[doc = "Field `SCR` writer - Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."] +pub type ScrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."] + #[inline(always)] + pub fn dss(&self) -> DssR { + DssR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame Format."] + #[inline(always)] + pub fn frf(&self) -> FrfR { + FrfR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Clock Out Polarity. This bit is only used in SPI mode."] + #[inline(always)] + pub fn cpol(&self) -> CpolR { + CpolR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock Out Phase. This bit is only used in SPI mode."] + #[inline(always)] + pub fn cpha(&self) -> CphaR { + CphaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."] + #[inline(always)] + pub fn scr(&self) -> ScrR { + ScrR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used."] + #[inline(always)] + #[must_use] + pub fn dss(&mut self) -> DssW { + DssW::new(self, 0) + } + #[doc = "Bits 4:5 - Frame Format."] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FrfW { + FrfW::new(self, 4) + } + #[doc = "Bit 6 - Clock Out Polarity. This bit is only used in SPI mode."] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CpolW { + CpolW::new(self, 6) + } + #[doc = "Bit 7 - Clock Out Phase. This bit is only used in SPI mode."] + #[inline(always)] + #[must_use] + pub fn cpha(&mut self) -> CphaW { + CphaW::new(self, 7) + } + #[doc = "Bits 8:15 - Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X \\[SCR+1\\])."] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> ScrW { + ScrW::new(self, 8) + } +} +#[doc = "Control Register 0. Selects the serial clock rate, bus type, and data size.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cr0Spec; +impl crate::RegisterSpec for Cr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr0::R`](R) reader structure"] +impl crate::Readable for Cr0Spec {} +#[doc = "`write(|w| ..)` method takes [`cr0::W`](W) writer structure"] +impl crate::Writable for Cr0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CR0 to value 0"] +impl crate::Resettable for Cr0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/cr1.rs b/rust-embedded/lpc111x-pac/src/spi0/cr1.rs new file mode 100644 index 0000000..9cb515a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/cr1.rs @@ -0,0 +1,232 @@ +#[doc = "Register `CR1` reader"] +pub type R = crate::R; +#[doc = "Register `CR1` writer"] +pub type W = crate::W; +#[doc = "Loop Back Mode.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lbm { + #[doc = "0: During normal operation."] + Normal = 0, + #[doc = "1: Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."] + Loopback = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lbm) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LBM` reader - Loop Back Mode."] +pub type LbmR = crate::BitReader; +impl LbmR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lbm { + match self.bits { + false => Lbm::Normal, + true => Lbm::Loopback, + } + } + #[doc = "During normal operation."] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == Lbm::Normal + } + #[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."] + #[inline(always)] + pub fn is_loopback(&self) -> bool { + *self == Lbm::Loopback + } +} +#[doc = "Field `LBM` writer - Loop Back Mode."] +pub type LbmW<'a, REG> = crate::BitWriter<'a, REG, Lbm>; +impl<'a, REG> LbmW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "During normal operation."] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(Lbm::Normal) + } + #[doc = "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively)."] + #[inline(always)] + pub fn loopback(self) -> &'a mut crate::W { + self.variant(Lbm::Loopback) + } +} +#[doc = "SPI Enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sse { + #[doc = "0: The SPI controller is disabled."] + Disable = 0, + #[doc = "1: The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit."] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sse) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSE` reader - SPI Enable."] +pub type SseR = crate::BitReader; +impl SseR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sse { + match self.bits { + false => Sse::Disable, + true => Sse::Enable, + } + } + #[doc = "The SPI controller is disabled."] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Sse::Disable + } + #[doc = "The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit."] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Sse::Enable + } +} +#[doc = "Field `SSE` writer - SPI Enable."] +pub type SseW<'a, REG> = crate::BitWriter<'a, REG, Sse>; +impl<'a, REG> SseW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SPI controller is disabled."] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Sse::Disable) + } + #[doc = "The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit."] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Sse::Enable) + } +} +#[doc = "Master/Slave Mode.This bit can only be written when the SSE bit is 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ms { + #[doc = "0: The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."] + Master = 0, + #[doc = "1: The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."] + Slave = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ms) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MS` reader - Master/Slave Mode.This bit can only be written when the SSE bit is 0."] +pub type MsR = crate::BitReader; +impl MsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ms { + match self.bits { + false => Ms::Master, + true => Ms::Slave, + } + } + #[doc = "The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."] + #[inline(always)] + pub fn is_master(&self) -> bool { + *self == Ms::Master + } + #[doc = "The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."] + #[inline(always)] + pub fn is_slave(&self) -> bool { + *self == Ms::Slave + } +} +#[doc = "Field `MS` writer - Master/Slave Mode.This bit can only be written when the SSE bit is 0."] +pub type MsW<'a, REG> = crate::BitWriter<'a, REG, Ms>; +impl<'a, REG> MsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line."] + #[inline(always)] + pub fn master(self) -> &'a mut crate::W { + self.variant(Ms::Master) + } + #[doc = "The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines."] + #[inline(always)] + pub fn slave(self) -> &'a mut crate::W { + self.variant(Ms::Slave) + } +} +#[doc = "Field `SOD` reader - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)."] +pub type SodR = crate::BitReader; +#[doc = "Field `SOD` writer - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)."] +pub type SodW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Loop Back Mode."] + #[inline(always)] + pub fn lbm(&self) -> LbmR { + LbmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SPI Enable."] + #[inline(always)] + pub fn sse(&self) -> SseR { + SseR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master/Slave Mode.This bit can only be written when the SSE bit is 0."] + #[inline(always)] + pub fn ms(&self) -> MsR { + MsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)."] + #[inline(always)] + pub fn sod(&self) -> SodR { + SodR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop Back Mode."] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LbmW { + LbmW::new(self, 0) + } + #[doc = "Bit 1 - SPI Enable."] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SseW { + SseW::new(self, 1) + } + #[doc = "Bit 2 - Master/Slave Mode.This bit can only be written when the SSE bit is 0."] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MsW { + MsW::new(self, 2) + } + #[doc = "Bit 3 - Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO)."] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SodW { + SodW::new(self, 3) + } +} +#[doc = "Control Register 1. Selects master/slave and other modes.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cr1Spec; +impl crate::RegisterSpec for Cr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cr1::R`](R) reader structure"] +impl crate::Readable for Cr1Spec {} +#[doc = "`write(|w| ..)` method takes [`cr1::W`](W) writer structure"] +impl crate::Writable for Cr1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CR1 to value 0"] +impl crate::Resettable for Cr1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/dr.rs b/rust-embedded/lpc111x-pac/src/spi0/dr.rs new file mode 100644 index 0000000..ee457e8 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/dr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DR` reader"] +pub type R = crate::R; +#[doc = "Register `DR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s."] +pub type DataR = crate::FieldReader; +#[doc = "Field `DATA` writer - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s."] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s."] + #[inline(always)] + pub fn data(&self) -> DataR { + DataR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). WARN: The register is **modified** in some way after a read operation. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DrSpec; +impl crate::RegisterSpec for DrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dr::R`](R) reader structure"] +impl crate::Readable for DrSpec {} +#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"] +impl crate::Writable for DrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DR to value 0"] +impl crate::Resettable for DrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/icr.rs b/rust-embedded/lpc111x-pac/src/spi0/icr.rs new file mode 100644 index 0000000..dc91da6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/icr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `ICR` writer"] +pub type W = crate::W; +#[doc = "Field `RORIC` writer - Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt."] +pub type RoricW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIC` writer - Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] +pub type RticW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt."] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RoricW { + RoricW::new(self, 0) + } + #[doc = "Bit 1 - Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RticW { + RticW::new(self, 1) + } +} +#[doc = "SSPICR Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IcrSpec; +impl crate::RegisterSpec for IcrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] +impl crate::Writable for IcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for IcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/imsc.rs b/rust-embedded/lpc111x-pac/src/spi0/imsc.rs new file mode 100644 index 0000000..5193ee7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/imsc.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IMSC` reader"] +pub type R = crate::R; +#[doc = "Register `IMSC` writer"] +pub type W = crate::W; +#[doc = "Field `RORIM` reader - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] +pub type RorimR = crate::BitReader; +#[doc = "Field `RORIM` writer - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] +pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] +pub type RtimR = crate::BitReader; +#[doc = "Field `RTIM` writer - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] +pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."] +pub type RximR = crate::BitReader; +#[doc = "Field `RXIM` writer - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."] +pub type RximW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."] +pub type TximR = crate::BitReader; +#[doc = "Field `TXIM` writer - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."] +pub type TximW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] + #[inline(always)] + pub fn rorim(&self) -> RorimR { + RorimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] + #[inline(always)] + pub fn rtim(&self) -> RtimR { + RtimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."] + #[inline(always)] + pub fn rxim(&self) -> RximR { + RximR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."] + #[inline(always)] + pub fn txim(&self) -> TximR { + TximR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RorimW { + RorimW::new(self, 0) + } + #[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RtimW { + RtimW::new(self, 1) + } + #[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RximW { + RximW::new(self, 2) + } + #[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TximW { + TximW::new(self, 3) + } +} +#[doc = "Interrupt Mask Set and Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ImscSpec; +impl crate::RegisterSpec for ImscSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`imsc::R`](R) reader structure"] +impl crate::Readable for ImscSpec {} +#[doc = "`write(|w| ..)` method takes [`imsc::W`](W) writer structure"] +impl crate::Writable for ImscSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IMSC to value 0"] +impl crate::Resettable for ImscSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/mis.rs b/rust-embedded/lpc111x-pac/src/spi0/mis.rs new file mode 100644 index 0000000..573bdef --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/mis.rs @@ -0,0 +1,43 @@ +#[doc = "Register `MIS` reader"] +pub type R = crate::R; +#[doc = "Field `RORMIS` reader - This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled."] +pub type RormisR = crate::BitReader; +#[doc = "Field `RTMIS` reader - This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] +pub type RtmisR = crate::BitReader; +#[doc = "Field `RXMIS` reader - This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled."] +pub type RxmisR = crate::BitReader; +#[doc = "Field `TXMIS` reader - This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled."] +pub type TxmisR = crate::BitReader; +impl R { + #[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled."] + #[inline(always)] + pub fn rormis(&self) -> RormisR { + RormisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] + #[inline(always)] + pub fn rtmis(&self) -> RtmisR { + RtmisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled."] + #[inline(always)] + pub fn rxmis(&self) -> RxmisR { + RxmisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled."] + #[inline(always)] + pub fn txmis(&self) -> TxmisR { + TxmisR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MisSpec; +impl crate::RegisterSpec for MisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mis::R`](R) reader structure"] +impl crate::Readable for MisSpec {} +#[doc = "`reset()` method sets MIS to value 0"] +impl crate::Resettable for MisSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/ris.rs b/rust-embedded/lpc111x-pac/src/spi0/ris.rs new file mode 100644 index 0000000..488425e --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/ris.rs @@ -0,0 +1,43 @@ +#[doc = "Register `RIS` reader"] +pub type R = crate::R; +#[doc = "Field `RORRIS` reader - This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] +pub type RorrisR = crate::BitReader; +#[doc = "Field `RTRIS` reader - This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] +pub type RtrisR = crate::BitReader; +#[doc = "Field `RXRIS` reader - This bit is 1 if the Rx FIFO is at least half full."] +pub type RxrisR = crate::BitReader; +#[doc = "Field `TXRIS` reader - This bit is 1 if the Tx FIFO is at least half empty."] +pub type TxrisR = crate::BitReader; +impl R { + #[doc = "Bit 0 - This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."] + #[inline(always)] + pub fn rorris(&self) -> RorrisR { + RorrisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."] + #[inline(always)] + pub fn rtris(&self) -> RtrisR { + RtrisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit is 1 if the Rx FIFO is at least half full."] + #[inline(always)] + pub fn rxris(&self) -> RxrisR { + RxrisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This bit is 1 if the Tx FIFO is at least half empty."] + #[inline(always)] + pub fn txris(&self) -> TxrisR { + TxrisR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RisSpec; +impl crate::RegisterSpec for RisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ris::R`](R) reader structure"] +impl crate::Readable for RisSpec {} +#[doc = "`reset()` method sets RIS to value 0x08"] +impl crate::Resettable for RisSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/rust-embedded/lpc111x-pac/src/spi0/sr.rs b/rust-embedded/lpc111x-pac/src/spi0/sr.rs new file mode 100644 index 0000000..6dab1d5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/spi0/sr.rs @@ -0,0 +1,50 @@ +#[doc = "Register `SR` reader"] +pub type R = crate::R; +#[doc = "Field `TFE` reader - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not."] +pub type TfeR = crate::BitReader; +#[doc = "Field `TNF` reader - Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not."] +pub type TnfR = crate::BitReader; +#[doc = "Field `RNE` reader - Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not."] +pub type RneR = crate::BitReader; +#[doc = "Field `RFF` reader - Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not."] +pub type RffR = crate::BitReader; +#[doc = "Field `BSY` reader - Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty."] +pub type BsyR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not."] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not."] + #[inline(always)] + pub fn tnf(&self) -> TnfR { + TnfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not."] + #[inline(always)] + pub fn rne(&self) -> RneR { + RneR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not."] + #[inline(always)] + pub fn rff(&self) -> RffR { + RffR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BsyR { + BsyR::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SrSpec; +impl crate::RegisterSpec for SrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SrSpec {} +#[doc = "`reset()` method sets SR to value 0x03"] +impl crate::Resettable for SrSpec { + const RESET_VALUE: u32 = 0x03; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon.rs b/rust-embedded/lpc111x-pac/src/syscon.rs new file mode 100644 index 0000000..3c91f07 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon.rs @@ -0,0 +1,452 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + sysmemremap: Sysmemremap, + presetctrl: Presetctrl, + syspllctrl: Syspllctrl, + syspllstat: Syspllstat, + _reserved4: [u8; 0x10], + sysoscctrl: Sysoscctrl, + wdtoscctrl: Wdtoscctrl, + ircctrl: Ircctrl, + _reserved7: [u8; 0x04], + sysrststat: Sysrststat, + _reserved8: [u8; 0x0c], + syspllclksel: Syspllclksel, + syspllclkuen: Syspllclkuen, + _reserved10: [u8; 0x28], + mainclksel: Mainclksel, + mainclkuen: Mainclkuen, + sysahbclkdiv: Sysahbclkdiv, + _reserved13: [u8; 0x04], + sysahbclkctrl: Sysahbclkctrl, + _reserved14: [u8; 0x10], + ssp0clkdiv: Ssp0clkdiv, + uartclkdiv: Uartclkdiv, + ssp1clkdiv: Ssp1clkdiv, + _reserved17: [u8; 0x30], + wdtclksel: Wdtclksel, + wdtclkuen: Wdtclkuen, + wdtclkdiv: Wdtclkdiv, + _reserved20: [u8; 0x04], + clkoutclksel: Clkoutclksel, + clkoutuen: Clkoutuen, + clkoutclkdiv: Clkoutclkdiv, + _reserved23: [u8; 0x14], + pioporcap0: Pioporcap0, + pioporcap1: Pioporcap1, + _reserved25: [u8; 0x48], + bodctrl: Bodctrl, + systckcal: Systckcal, + _reserved27: [u8; 0x1c], + nmisrc: Nmisrc, + _reserved28: [u8; 0x88], + startaprp0: Startaprp0, + starterp0: Starterp0, + startrsrp0clr: Startrsrp0clr, + startsrp0: Startsrp0, + _reserved32: [u8; 0x20], + pdsleepcfg: Pdsleepcfg, + pdawakecfg: Pdawakecfg, + pdruncfg: Pdruncfg, + _reserved35: [u8; 0x01b8], + device_id: DeviceId, +} +impl RegisterBlock { + #[doc = "0x00 - System memory remap"] + #[inline(always)] + pub const fn sysmemremap(&self) -> &Sysmemremap { + &self.sysmemremap + } + #[doc = "0x04 - Peripheral reset control"] + #[inline(always)] + pub const fn presetctrl(&self) -> &Presetctrl { + &self.presetctrl + } + #[doc = "0x08 - System PLL control"] + #[inline(always)] + pub const fn syspllctrl(&self) -> &Syspllctrl { + &self.syspllctrl + } + #[doc = "0x0c - System PLL status"] + #[inline(always)] + pub const fn syspllstat(&self) -> &Syspllstat { + &self.syspllstat + } + #[doc = "0x20 - System oscillator control"] + #[inline(always)] + pub const fn sysoscctrl(&self) -> &Sysoscctrl { + &self.sysoscctrl + } + #[doc = "0x24 - Watchdog oscillator control"] + #[inline(always)] + pub const fn wdtoscctrl(&self) -> &Wdtoscctrl { + &self.wdtoscctrl + } + #[doc = "0x28 - IRC control"] + #[inline(always)] + pub const fn ircctrl(&self) -> &Ircctrl { + &self.ircctrl + } + #[doc = "0x30 - System reset status register"] + #[inline(always)] + pub const fn sysrststat(&self) -> &Sysrststat { + &self.sysrststat + } + #[doc = "0x40 - System PLL clock source select"] + #[inline(always)] + pub const fn syspllclksel(&self) -> &Syspllclksel { + &self.syspllclksel + } + #[doc = "0x44 - System PLL clock source update enable"] + #[inline(always)] + pub const fn syspllclkuen(&self) -> &Syspllclkuen { + &self.syspllclkuen + } + #[doc = "0x70 - Main clock source select"] + #[inline(always)] + pub const fn mainclksel(&self) -> &Mainclksel { + &self.mainclksel + } + #[doc = "0x74 - Main clock source update enable"] + #[inline(always)] + pub const fn mainclkuen(&self) -> &Mainclkuen { + &self.mainclkuen + } + #[doc = "0x78 - System AHB clock divider"] + #[inline(always)] + pub const fn sysahbclkdiv(&self) -> &Sysahbclkdiv { + &self.sysahbclkdiv + } + #[doc = "0x80 - System AHB clock control"] + #[inline(always)] + pub const fn sysahbclkctrl(&self) -> &Sysahbclkctrl { + &self.sysahbclkctrl + } + #[doc = "0x94 - SPI0 clock divider"] + #[inline(always)] + pub const fn ssp0clkdiv(&self) -> &Ssp0clkdiv { + &self.ssp0clkdiv + } + #[doc = "0x98 - UART clock divder"] + #[inline(always)] + pub const fn uartclkdiv(&self) -> &Uartclkdiv { + &self.uartclkdiv + } + #[doc = "0x9c - SPI1 clock divder"] + #[inline(always)] + pub const fn ssp1clkdiv(&self) -> &Ssp1clkdiv { + &self.ssp1clkdiv + } + #[doc = "0xd0 - WDT clock source select"] + #[inline(always)] + pub const fn wdtclksel(&self) -> &Wdtclksel { + &self.wdtclksel + } + #[doc = "0xd4 - WDT clock source update enable"] + #[inline(always)] + pub const fn wdtclkuen(&self) -> &Wdtclkuen { + &self.wdtclkuen + } + #[doc = "0xd8 - WDT clock divider"] + #[inline(always)] + pub const fn wdtclkdiv(&self) -> &Wdtclkdiv { + &self.wdtclkdiv + } + #[doc = "0xe0 - CLKOUT clock source select"] + #[inline(always)] + pub const fn clkoutclksel(&self) -> &Clkoutclksel { + &self.clkoutclksel + } + #[doc = "0xe4 - CLKOUT clock source update enable"] + #[inline(always)] + pub const fn clkoutuen(&self) -> &Clkoutuen { + &self.clkoutuen + } + #[doc = "0xe8 - CLKOUT clock divider"] + #[inline(always)] + pub const fn clkoutclkdiv(&self) -> &Clkoutclkdiv { + &self.clkoutclkdiv + } + #[doc = "0x100 - POR captured PIO status 0"] + #[inline(always)] + pub const fn pioporcap0(&self) -> &Pioporcap0 { + &self.pioporcap0 + } + #[doc = "0x104 - POR captured PIO status 1"] + #[inline(always)] + pub const fn pioporcap1(&self) -> &Pioporcap1 { + &self.pioporcap1 + } + #[doc = "0x150 - BOD control"] + #[inline(always)] + pub const fn bodctrl(&self) -> &Bodctrl { + &self.bodctrl + } + #[doc = "0x154 - System tick counter calibration"] + #[inline(always)] + pub const fn systckcal(&self) -> &Systckcal { + &self.systckcal + } + #[doc = "0x174 - NMI source selection"] + #[inline(always)] + pub const fn nmisrc(&self) -> &Nmisrc { + &self.nmisrc + } + #[doc = "0x200 - Start logic edge control register 0"] + #[inline(always)] + pub const fn startaprp0(&self) -> &Startaprp0 { + &self.startaprp0 + } + #[doc = "0x204 - Start logic signal enable register 0"] + #[inline(always)] + pub const fn starterp0(&self) -> &Starterp0 { + &self.starterp0 + } + #[doc = "0x208 - Start logic reset register 0"] + #[inline(always)] + pub const fn startrsrp0clr(&self) -> &Startrsrp0clr { + &self.startrsrp0clr + } + #[doc = "0x20c - Start logic status register 0"] + #[inline(always)] + pub const fn startsrp0(&self) -> &Startsrp0 { + &self.startsrp0 + } + #[doc = "0x230 - Power-down states in Deep-sleep mode"] + #[inline(always)] + pub const fn pdsleepcfg(&self) -> &Pdsleepcfg { + &self.pdsleepcfg + } + #[doc = "0x234 - Power-down states after wake-up from Deep-sleep mode"] + #[inline(always)] + pub const fn pdawakecfg(&self) -> &Pdawakecfg { + &self.pdawakecfg + } + #[doc = "0x238 - Power-down configuration register"] + #[inline(always)] + pub const fn pdruncfg(&self) -> &Pdruncfg { + &self.pdruncfg + } + #[doc = "0x3f4 - Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L."] + #[inline(always)] + pub const fn device_id(&self) -> &DeviceId { + &self.device_id + } +} +#[doc = "SYSMEMREMAP (rw) register accessor: System memory remap\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysmemremap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysmemremap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysmemremap`] +module"] +#[doc(alias = "SYSMEMREMAP")] +pub type Sysmemremap = crate::Reg; +#[doc = "System memory remap"] +pub mod sysmemremap; +#[doc = "PRESETCTRL (rw) register accessor: Peripheral reset control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`presetctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`presetctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@presetctrl`] +module"] +#[doc(alias = "PRESETCTRL")] +pub type Presetctrl = crate::Reg; +#[doc = "Peripheral reset control"] +pub mod presetctrl; +#[doc = "SYSPLLCTRL (rw) register accessor: System PLL control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syspllctrl`] +module"] +#[doc(alias = "SYSPLLCTRL")] +pub type Syspllctrl = crate::Reg; +#[doc = "System PLL control"] +pub mod syspllctrl; +#[doc = "SYSPLLSTAT (r) register accessor: System PLL status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syspllstat`] +module"] +#[doc(alias = "SYSPLLSTAT")] +pub type Syspllstat = crate::Reg; +#[doc = "System PLL status"] +pub mod syspllstat; +#[doc = "SYSOSCCTRL (rw) register accessor: System oscillator control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysoscctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysoscctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysoscctrl`] +module"] +#[doc(alias = "SYSOSCCTRL")] +pub type Sysoscctrl = crate::Reg; +#[doc = "System oscillator control"] +pub mod sysoscctrl; +#[doc = "WDTOSCCTRL (rw) register accessor: Watchdog oscillator control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtoscctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtoscctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtoscctrl`] +module"] +#[doc(alias = "WDTOSCCTRL")] +pub type Wdtoscctrl = crate::Reg; +#[doc = "Watchdog oscillator control"] +pub mod wdtoscctrl; +#[doc = "IRCCTRL (rw) register accessor: IRC control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ircctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ircctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ircctrl`] +module"] +#[doc(alias = "IRCCTRL")] +pub type Ircctrl = crate::Reg; +#[doc = "IRC control"] +pub mod ircctrl; +#[doc = "SYSRSTSTAT (r) register accessor: System reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysrststat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysrststat`] +module"] +#[doc(alias = "SYSRSTSTAT")] +pub type Sysrststat = crate::Reg; +#[doc = "System reset status register"] +pub mod sysrststat; +#[doc = "SYSPLLCLKSEL (rw) register accessor: System PLL clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllclksel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllclksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syspllclksel`] +module"] +#[doc(alias = "SYSPLLCLKSEL")] +pub type Syspllclksel = crate::Reg; +#[doc = "System PLL clock source select"] +pub mod syspllclksel; +#[doc = "SYSPLLCLKUEN (rw) register accessor: System PLL clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllclkuen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllclkuen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@syspllclkuen`] +module"] +#[doc(alias = "SYSPLLCLKUEN")] +pub type Syspllclkuen = crate::Reg; +#[doc = "System PLL clock source update enable"] +pub mod syspllclkuen; +#[doc = "MAINCLKSEL (rw) register accessor: Main clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mainclksel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mainclksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mainclksel`] +module"] +#[doc(alias = "MAINCLKSEL")] +pub type Mainclksel = crate::Reg; +#[doc = "Main clock source select"] +pub mod mainclksel; +#[doc = "MAINCLKUEN (rw) register accessor: Main clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mainclkuen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mainclkuen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mainclkuen`] +module"] +#[doc(alias = "MAINCLKUEN")] +pub type Mainclkuen = crate::Reg; +#[doc = "Main clock source update enable"] +pub mod mainclkuen; +#[doc = "SYSAHBCLKDIV (rw) register accessor: System AHB clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysahbclkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysahbclkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysahbclkdiv`] +module"] +#[doc(alias = "SYSAHBCLKDIV")] +pub type Sysahbclkdiv = crate::Reg; +#[doc = "System AHB clock divider"] +pub mod sysahbclkdiv; +#[doc = "SYSAHBCLKCTRL (rw) register accessor: System AHB clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysahbclkctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysahbclkctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysahbclkctrl`] +module"] +#[doc(alias = "SYSAHBCLKCTRL")] +pub type Sysahbclkctrl = crate::Reg; +#[doc = "System AHB clock control"] +pub mod sysahbclkctrl; +#[doc = "SSP0CLKDIV (rw) register accessor: SPI0 clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp0clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp0clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp0clkdiv`] +module"] +#[doc(alias = "SSP0CLKDIV")] +pub type Ssp0clkdiv = crate::Reg; +#[doc = "SPI0 clock divider"] +pub mod ssp0clkdiv; +#[doc = "UARTCLKDIV (rw) register accessor: UART clock divder\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uartclkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartclkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uartclkdiv`] +module"] +#[doc(alias = "UARTCLKDIV")] +pub type Uartclkdiv = crate::Reg; +#[doc = "UART clock divder"] +pub mod uartclkdiv; +#[doc = "SSP1CLKDIV (rw) register accessor: SPI1 clock divder\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp1clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp1clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssp1clkdiv`] +module"] +#[doc(alias = "SSP1CLKDIV")] +pub type Ssp1clkdiv = crate::Reg; +#[doc = "SPI1 clock divder"] +pub mod ssp1clkdiv; +#[doc = "WDTCLKSEL (rw) register accessor: WDT clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclksel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtclksel`] +module"] +#[doc(alias = "WDTCLKSEL")] +pub type Wdtclksel = crate::Reg; +#[doc = "WDT clock source select"] +pub mod wdtclksel; +#[doc = "WDTCLKUEN (rw) register accessor: WDT clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclkuen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclkuen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtclkuen`] +module"] +#[doc(alias = "WDTCLKUEN")] +pub type Wdtclkuen = crate::Reg; +#[doc = "WDT clock source update enable"] +pub mod wdtclkuen; +#[doc = "WDTCLKDIV (rw) register accessor: WDT clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtclkdiv`] +module"] +#[doc(alias = "WDTCLKDIV")] +pub type Wdtclkdiv = crate::Reg; +#[doc = "WDT clock divider"] +pub mod wdtclkdiv; +#[doc = "CLKOUTCLKSEL (rw) register accessor: CLKOUT clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutclksel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutclksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkoutclksel`] +module"] +#[doc(alias = "CLKOUTCLKSEL")] +pub type Clkoutclksel = crate::Reg; +#[doc = "CLKOUT clock source select"] +pub mod clkoutclksel; +#[doc = "CLKOUTUEN (rw) register accessor: CLKOUT clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutuen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutuen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkoutuen`] +module"] +#[doc(alias = "CLKOUTUEN")] +pub type Clkoutuen = crate::Reg; +#[doc = "CLKOUT clock source update enable"] +pub mod clkoutuen; +#[doc = "CLKOUTCLKDIV (rw) register accessor: CLKOUT clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutclkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutclkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkoutclkdiv`] +module"] +#[doc(alias = "CLKOUTCLKDIV")] +pub type Clkoutclkdiv = crate::Reg; +#[doc = "CLKOUT clock divider"] +pub mod clkoutclkdiv; +#[doc = "PIOPORCAP0 (r) register accessor: POR captured PIO status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pioporcap0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pioporcap0`] +module"] +#[doc(alias = "PIOPORCAP0")] +pub type Pioporcap0 = crate::Reg; +#[doc = "POR captured PIO status 0"] +pub mod pioporcap0; +#[doc = "PIOPORCAP1 (r) register accessor: POR captured PIO status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pioporcap1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pioporcap1`] +module"] +#[doc(alias = "PIOPORCAP1")] +pub type Pioporcap1 = crate::Reg; +#[doc = "POR captured PIO status 1"] +pub mod pioporcap1; +#[doc = "BODCTRL (rw) register accessor: BOD control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bodctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bodctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bodctrl`] +module"] +#[doc(alias = "BODCTRL")] +pub type Bodctrl = crate::Reg; +#[doc = "BOD control"] +pub mod bodctrl; +#[doc = "SYSTCKCAL (rw) register accessor: System tick counter calibration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systckcal::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systckcal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systckcal`] +module"] +#[doc(alias = "SYSTCKCAL")] +pub type Systckcal = crate::Reg; +#[doc = "System tick counter calibration"] +pub mod systckcal; +#[doc = "NMISRC (rw) register accessor: NMI source selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmisrc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmisrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmisrc`] +module"] +#[doc(alias = "NMISRC")] +pub type Nmisrc = crate::Reg; +#[doc = "NMI source selection"] +pub mod nmisrc; +#[doc = "STARTAPRP0 (rw) register accessor: Start logic edge control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`startaprp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startaprp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@startaprp0`] +module"] +#[doc(alias = "STARTAPRP0")] +pub type Startaprp0 = crate::Reg; +#[doc = "Start logic edge control register 0"] +pub mod startaprp0; +#[doc = "STARTERP0 (rw) register accessor: Start logic signal enable register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`starterp0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`starterp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@starterp0`] +module"] +#[doc(alias = "STARTERP0")] +pub type Starterp0 = crate::Reg; +#[doc = "Start logic signal enable register 0"] +pub mod starterp0; +#[doc = "STARTRSRP0CLR (w) register accessor: Start logic reset register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startrsrp0clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@startrsrp0clr`] +module"] +#[doc(alias = "STARTRSRP0CLR")] +pub type Startrsrp0clr = crate::Reg; +#[doc = "Start logic reset register 0"] +pub mod startrsrp0clr; +#[doc = "STARTSRP0 (r) register accessor: Start logic status register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`startsrp0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@startsrp0`] +module"] +#[doc(alias = "STARTSRP0")] +pub type Startsrp0 = crate::Reg; +#[doc = "Start logic status register 0"] +pub mod startsrp0; +#[doc = "PDSLEEPCFG (rw) register accessor: Power-down states in Deep-sleep mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsleepcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdsleepcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdsleepcfg`] +module"] +#[doc(alias = "PDSLEEPCFG")] +pub type Pdsleepcfg = crate::Reg; +#[doc = "Power-down states in Deep-sleep mode"] +pub mod pdsleepcfg; +#[doc = "PDAWAKECFG (rw) register accessor: Power-down states after wake-up from Deep-sleep mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdawakecfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdawakecfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdawakecfg`] +module"] +#[doc(alias = "PDAWAKECFG")] +pub type Pdawakecfg = crate::Reg; +#[doc = "Power-down states after wake-up from Deep-sleep mode"] +pub mod pdawakecfg; +#[doc = "PDRUNCFG (rw) register accessor: Power-down configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdruncfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdruncfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdruncfg`] +module"] +#[doc(alias = "PDRUNCFG")] +pub type Pdruncfg = crate::Reg; +#[doc = "Power-down configuration register"] +pub mod pdruncfg; +#[doc = "DEVICE_ID (r) register accessor: Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@device_id`] +module"] +#[doc(alias = "DEVICE_ID")] +pub type DeviceId = crate::Reg; +#[doc = "Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L."] +pub mod device_id; diff --git a/rust-embedded/lpc111x-pac/src/syscon/bodctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/bodctrl.rs new file mode 100644 index 0000000..648aa32 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/bodctrl.rs @@ -0,0 +1,281 @@ +#[doc = "Register `BODCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BODCTRL` writer"] +pub type W = crate::W; +#[doc = "BOD reset level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Bodrstlev { + #[doc = "0: Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V."] + Level0TheResetA = 0, + #[doc = "1: Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V."] + Level1TheResetA = 1, + #[doc = "2: Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V."] + Level2TheResetA = 2, + #[doc = "3: Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V."] + Level3TheResetA = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Bodrstlev) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Bodrstlev { + type Ux = u8; +} +#[doc = "Field `BODRSTLEV` reader - BOD reset level"] +pub type BodrstlevR = crate::FieldReader; +impl BodrstlevR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bodrstlev { + match self.bits { + 0 => Bodrstlev::Level0TheResetA, + 1 => Bodrstlev::Level1TheResetA, + 2 => Bodrstlev::Level2TheResetA, + 3 => Bodrstlev::Level3TheResetA, + _ => unreachable!(), + } + } + #[doc = "Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V."] + #[inline(always)] + pub fn is_level_0_the_reset_a(&self) -> bool { + *self == Bodrstlev::Level0TheResetA + } + #[doc = "Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V."] + #[inline(always)] + pub fn is_level_1_the_reset_a(&self) -> bool { + *self == Bodrstlev::Level1TheResetA + } + #[doc = "Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V."] + #[inline(always)] + pub fn is_level_2_the_reset_a(&self) -> bool { + *self == Bodrstlev::Level2TheResetA + } + #[doc = "Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V."] + #[inline(always)] + pub fn is_level_3_the_reset_a(&self) -> bool { + *self == Bodrstlev::Level3TheResetA + } +} +#[doc = "Field `BODRSTLEV` writer - BOD reset level"] +pub type BodrstlevW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Bodrstlev>; +impl<'a, REG> BodrstlevW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V."] + #[inline(always)] + pub fn level_0_the_reset_a(self) -> &'a mut crate::W { + self.variant(Bodrstlev::Level0TheResetA) + } + #[doc = "Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V."] + #[inline(always)] + pub fn level_1_the_reset_a(self) -> &'a mut crate::W { + self.variant(Bodrstlev::Level1TheResetA) + } + #[doc = "Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V."] + #[inline(always)] + pub fn level_2_the_reset_a(self) -> &'a mut crate::W { + self.variant(Bodrstlev::Level2TheResetA) + } + #[doc = "Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V."] + #[inline(always)] + pub fn level_3_the_reset_a(self) -> &'a mut crate::W { + self.variant(Bodrstlev::Level3TheResetA) + } +} +#[doc = "BOD interrupt level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Bodintval { + #[doc = "0: Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V."] + Level0TheInterru = 0, + #[doc = "1: Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V."] + Level1theInterrup = 1, + #[doc = "2: Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V."] + Level2TheInterru = 2, + #[doc = "3: Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V."] + Level3TheInterru = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Bodintval) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Bodintval { + type Ux = u8; +} +#[doc = "Field `BODINTVAL` reader - BOD interrupt level"] +pub type BodintvalR = crate::FieldReader; +impl BodintvalR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bodintval { + match self.bits { + 0 => Bodintval::Level0TheInterru, + 1 => Bodintval::Level1theInterrup, + 2 => Bodintval::Level2TheInterru, + 3 => Bodintval::Level3TheInterru, + _ => unreachable!(), + } + } + #[doc = "Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V."] + #[inline(always)] + pub fn is_level_0_the_interru(&self) -> bool { + *self == Bodintval::Level0TheInterru + } + #[doc = "Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V."] + #[inline(always)] + pub fn is_level_1the_interrup(&self) -> bool { + *self == Bodintval::Level1theInterrup + } + #[doc = "Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V."] + #[inline(always)] + pub fn is_level_2_the_interru(&self) -> bool { + *self == Bodintval::Level2TheInterru + } + #[doc = "Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V."] + #[inline(always)] + pub fn is_level_3_the_interru(&self) -> bool { + *self == Bodintval::Level3TheInterru + } +} +#[doc = "Field `BODINTVAL` writer - BOD interrupt level"] +pub type BodintvalW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Bodintval>; +impl<'a, REG> BodintvalW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V."] + #[inline(always)] + pub fn level_0_the_interru(self) -> &'a mut crate::W { + self.variant(Bodintval::Level0TheInterru) + } + #[doc = "Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V."] + #[inline(always)] + pub fn level_1the_interrup(self) -> &'a mut crate::W { + self.variant(Bodintval::Level1theInterrup) + } + #[doc = "Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V."] + #[inline(always)] + pub fn level_2_the_interru(self) -> &'a mut crate::W { + self.variant(Bodintval::Level2TheInterru) + } + #[doc = "Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V."] + #[inline(always)] + pub fn level_3_the_interru(self) -> &'a mut crate::W { + self.variant(Bodintval::Level3TheInterru) + } +} +#[doc = "BOD reset enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bodrstena { + #[doc = "0: Disable reset function."] + DisableResetFuncti = 0, + #[doc = "1: Enable reset function."] + EnableResetFunctio = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bodrstena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BODRSTENA` reader - BOD reset enable"] +pub type BodrstenaR = crate::BitReader; +impl BodrstenaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bodrstena { + match self.bits { + false => Bodrstena::DisableResetFuncti, + true => Bodrstena::EnableResetFunctio, + } + } + #[doc = "Disable reset function."] + #[inline(always)] + pub fn is_disable_reset_functi(&self) -> bool { + *self == Bodrstena::DisableResetFuncti + } + #[doc = "Enable reset function."] + #[inline(always)] + pub fn is_enable_reset_functio(&self) -> bool { + *self == Bodrstena::EnableResetFunctio + } +} +#[doc = "Field `BODRSTENA` writer - BOD reset enable"] +pub type BodrstenaW<'a, REG> = crate::BitWriter<'a, REG, Bodrstena>; +impl<'a, REG> BodrstenaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable reset function."] + #[inline(always)] + pub fn disable_reset_functi(self) -> &'a mut crate::W { + self.variant(Bodrstena::DisableResetFuncti) + } + #[doc = "Enable reset function."] + #[inline(always)] + pub fn enable_reset_functio(self) -> &'a mut crate::W { + self.variant(Bodrstena::EnableResetFunctio) + } +} +impl R { + #[doc = "Bits 0:1 - BOD reset level"] + #[inline(always)] + pub fn bodrstlev(&self) -> BodrstlevR { + BodrstlevR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - BOD interrupt level"] + #[inline(always)] + pub fn bodintval(&self) -> BodintvalR { + BodintvalR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - BOD reset enable"] + #[inline(always)] + pub fn bodrstena(&self) -> BodrstenaR { + BodrstenaR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - BOD reset level"] + #[inline(always)] + #[must_use] + pub fn bodrstlev(&mut self) -> BodrstlevW { + BodrstlevW::new(self, 0) + } + #[doc = "Bits 2:3 - BOD interrupt level"] + #[inline(always)] + #[must_use] + pub fn bodintval(&mut self) -> BodintvalW { + BodintvalW::new(self, 2) + } + #[doc = "Bit 4 - BOD reset enable"] + #[inline(always)] + #[must_use] + pub fn bodrstena(&mut self) -> BodrstenaW { + BodrstenaW::new(self, 4) + } +} +#[doc = "BOD control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bodctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bodctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BodctrlSpec; +impl crate::RegisterSpec for BodctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bodctrl::R`](R) reader structure"] +impl crate::Readable for BodctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`bodctrl::W`](W) writer structure"] +impl crate::Writable for BodctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BODCTRL to value 0"] +impl crate::Resettable for BodctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/clkoutclkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/clkoutclkdiv.rs new file mode 100644 index 0000000..304bc25 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/clkoutclkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CLKOUTCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLKOUTCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "CLKOUT clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutclkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutclkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkoutclkdivSpec; +impl crate::RegisterSpec for ClkoutclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkoutclkdiv::R`](R) reader structure"] +impl crate::Readable for ClkoutclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`clkoutclkdiv::W`](W) writer structure"] +impl crate::Writable for ClkoutclkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKOUTCLKDIV to value 0"] +impl crate::Resettable for ClkoutclkdivSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/clkoutclksel.rs b/rust-embedded/lpc111x-pac/src/syscon/clkoutclksel.rs new file mode 100644 index 0000000..41f6286 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/clkoutclksel.rs @@ -0,0 +1,121 @@ +#[doc = "Register `CLKOUTCLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `CLKOUTCLKSEL` writer"] +pub type W = crate::W; +#[doc = "CLKOUT clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sel { + #[doc = "0: IRC oscillator"] + IrcOscillator = 0, + #[doc = "1: System oscillator"] + SystemOscillator = 1, + #[doc = "2: Watchdog oscillator"] + WatchdogOscillator = 2, + #[doc = "3: Main clock"] + MainClock = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sel { + type Ux = u8; +} +#[doc = "Field `SEL` reader - CLKOUT clock source"] +pub type SelR = crate::FieldReader; +impl SelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sel { + match self.bits { + 0 => Sel::IrcOscillator, + 1 => Sel::SystemOscillator, + 2 => Sel::WatchdogOscillator, + 3 => Sel::MainClock, + _ => unreachable!(), + } + } + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn is_irc_oscillator(&self) -> bool { + *self == Sel::IrcOscillator + } + #[doc = "System oscillator"] + #[inline(always)] + pub fn is_system_oscillator(&self) -> bool { + *self == Sel::SystemOscillator + } + #[doc = "Watchdog oscillator"] + #[inline(always)] + pub fn is_watchdog_oscillator(&self) -> bool { + *self == Sel::WatchdogOscillator + } + #[doc = "Main clock"] + #[inline(always)] + pub fn is_main_clock(&self) -> bool { + *self == Sel::MainClock + } +} +#[doc = "Field `SEL` writer - CLKOUT clock source"] +pub type SelW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Sel>; +impl<'a, REG> SelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn irc_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::IrcOscillator) + } + #[doc = "System oscillator"] + #[inline(always)] + pub fn system_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::SystemOscillator) + } + #[doc = "Watchdog oscillator"] + #[inline(always)] + pub fn watchdog_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::WatchdogOscillator) + } + #[doc = "Main clock"] + #[inline(always)] + pub fn main_clock(self) -> &'a mut crate::W { + self.variant(Sel::MainClock) + } +} +impl R { + #[doc = "Bits 0:1 - CLKOUT clock source"] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CLKOUT clock source"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 0) + } +} +#[doc = "CLKOUT clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutclksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutclksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkoutclkselSpec; +impl crate::RegisterSpec for ClkoutclkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkoutclksel::R`](R) reader structure"] +impl crate::Readable for ClkoutclkselSpec {} +#[doc = "`write(|w| ..)` method takes [`clkoutclksel::W`](W) writer structure"] +impl crate::Writable for ClkoutclkselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKOUTCLKSEL to value 0"] +impl crate::Resettable for ClkoutclkselSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/clkoutuen.rs b/rust-embedded/lpc111x-pac/src/syscon/clkoutuen.rs new file mode 100644 index 0000000..173e2ae --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/clkoutuen.rs @@ -0,0 +1,89 @@ +#[doc = "Register `CLKOUTUEN` reader"] +pub type R = crate::R; +#[doc = "Register `CLKOUTUEN` writer"] +pub type W = crate::W; +#[doc = "Enable CLKOUT clock source update\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ena { + #[doc = "0: No change"] + NoChange = 0, + #[doc = "1: Update clock source"] + UpdateClockSource = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA` reader - Enable CLKOUT clock source update"] +pub type EnaR = crate::BitReader; +impl EnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ena { + match self.bits { + false => Ena::NoChange, + true => Ena::UpdateClockSource, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_no_change(&self) -> bool { + *self == Ena::NoChange + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn is_update_clock_source(&self) -> bool { + *self == Ena::UpdateClockSource + } +} +#[doc = "Field `ENA` writer - Enable CLKOUT clock source update"] +pub type EnaW<'a, REG> = crate::BitWriter<'a, REG, Ena>; +impl<'a, REG> EnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn no_change(self) -> &'a mut crate::W { + self.variant(Ena::NoChange) + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn update_clock_source(self) -> &'a mut crate::W { + self.variant(Ena::UpdateClockSource) + } +} +impl R { + #[doc = "Bit 0 - Enable CLKOUT clock source update"] + #[inline(always)] + pub fn ena(&self) -> EnaR { + EnaR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable CLKOUT clock source update"] + #[inline(always)] + #[must_use] + pub fn ena(&mut self) -> EnaW { + EnaW::new(self, 0) + } +} +#[doc = "CLKOUT clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkoutuen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkoutuen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkoutuenSpec; +impl crate::RegisterSpec for ClkoutuenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkoutuen::R`](R) reader structure"] +impl crate::Readable for ClkoutuenSpec {} +#[doc = "`write(|w| ..)` method takes [`clkoutuen::W`](W) writer structure"] +impl crate::Writable for ClkoutuenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKOUTUEN to value 0"] +impl crate::Resettable for ClkoutuenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/device_id.rs b/rust-embedded/lpc111x-pac/src/syscon/device_id.rs new file mode 100644 index 0000000..25e72e1 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/device_id.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DEVICE_ID` reader"] +pub type R = crate::R; +#[doc = "Field `DEVICEID` reader - Part ID numbers for LPC111x 0x041E 502B; 0x2516 D02B = LPC1111FHN33/101 0x2516 D02B = LPC1111FHN33/102 0x0416 502B; 0x2516 902B = LPC1111FHN33/201 0x2516 902B = LPC1111FHN33/202 0x042D 502B; 0x2524 D02B = LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 0x0425 502B; 0x2524 902B = LPC1112FHN33/201 0x2524 902B = LPC1112FHN33/202 0x2524 902B = LPC1112FHI33/202 0x0434 502B; 0x2532 902B = LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 0x0434 102B; 0x2532 102B = LPC1113FHN33/301 0x2532 102B = LPC1113FHN33/302 0x0434 102B; 0x2532 102B = LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 0x0444 502B; 0x2540 902B = LPC1114FHN33/201 0x2540 902B = LPC1114FHN33/202 0x0444 102B; 0x2540 102B = LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 0x2540 102B = LPC1114FHI33/302 0x0444 102B; 0x2540 102B = LPC1114FBD48/301 0x2540 102B = LPC1114FBD48/302 0x2540 102B = LPC11D14FBD100/302"] +pub type DeviceidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Part ID numbers for LPC111x 0x041E 502B; 0x2516 D02B = LPC1111FHN33/101 0x2516 D02B = LPC1111FHN33/102 0x0416 502B; 0x2516 902B = LPC1111FHN33/201 0x2516 902B = LPC1111FHN33/202 0x042D 502B; 0x2524 D02B = LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 0x0425 502B; 0x2524 902B = LPC1112FHN33/201 0x2524 902B = LPC1112FHN33/202 0x2524 902B = LPC1112FHI33/202 0x0434 502B; 0x2532 902B = LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 0x0434 102B; 0x2532 102B = LPC1113FHN33/301 0x2532 102B = LPC1113FHN33/302 0x0434 102B; 0x2532 102B = LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 0x0444 502B; 0x2540 902B = LPC1114FHN33/201 0x2540 902B = LPC1114FHN33/202 0x0444 102B; 0x2540 102B = LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 0x2540 102B = LPC1114FHI33/302 0x0444 102B; 0x2540 102B = LPC1114FBD48/301 0x2540 102B = LPC1114FBD48/302 0x2540 102B = LPC11D14FBD100/302"] + #[inline(always)] + pub fn deviceid(&self) -> DeviceidR { + DeviceidR::new(self.bits) + } +} +#[doc = "Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`device_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DeviceIdSpec; +impl crate::RegisterSpec for DeviceIdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`device_id::R`](R) reader structure"] +impl crate::Readable for DeviceIdSpec {} +#[doc = "`reset()` method sets DEVICE_ID to value 0"] +impl crate::Resettable for DeviceIdSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/ircctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/ircctrl.rs new file mode 100644 index 0000000..29ccb63 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/ircctrl.rs @@ -0,0 +1,40 @@ +#[doc = "Register `IRCCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `IRCCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TRIM` reader - Trim value"] +pub type TrimR = crate::FieldReader; +#[doc = "Field `TRIM` writer - Trim value"] +pub type TrimW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Trim value"] + #[inline(always)] + pub fn trim(&self) -> TrimR { + TrimR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Trim value"] + #[inline(always)] + #[must_use] + pub fn trim(&mut self) -> TrimW { + TrimW::new(self, 0) + } +} +#[doc = "IRC control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ircctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ircctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrcctrlSpec; +impl crate::RegisterSpec for IrcctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ircctrl::R`](R) reader structure"] +impl crate::Readable for IrcctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ircctrl::W`](W) writer structure"] +impl crate::Writable for IrcctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRCCTRL to value 0x80"] +impl crate::Resettable for IrcctrlSpec { + const RESET_VALUE: u32 = 0x80; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/mainclksel.rs b/rust-embedded/lpc111x-pac/src/syscon/mainclksel.rs new file mode 100644 index 0000000..91910b5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/mainclksel.rs @@ -0,0 +1,121 @@ +#[doc = "Register `MAINCLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `MAINCLKSEL` writer"] +pub type W = crate::W; +#[doc = "Clock source for main clock\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sel { + #[doc = "0: IRC oscillator"] + IrcOscillator = 0, + #[doc = "1: Input clock to system PLL"] + InputClockToSyste = 1, + #[doc = "2: WDT oscillator"] + WdtOscillator = 2, + #[doc = "3: System PLL clock out"] + SystemPllClockOut = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sel { + type Ux = u8; +} +#[doc = "Field `SEL` reader - Clock source for main clock"] +pub type SelR = crate::FieldReader; +impl SelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sel { + match self.bits { + 0 => Sel::IrcOscillator, + 1 => Sel::InputClockToSyste, + 2 => Sel::WdtOscillator, + 3 => Sel::SystemPllClockOut, + _ => unreachable!(), + } + } + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn is_irc_oscillator(&self) -> bool { + *self == Sel::IrcOscillator + } + #[doc = "Input clock to system PLL"] + #[inline(always)] + pub fn is_input_clock_to_syste(&self) -> bool { + *self == Sel::InputClockToSyste + } + #[doc = "WDT oscillator"] + #[inline(always)] + pub fn is_wdt_oscillator(&self) -> bool { + *self == Sel::WdtOscillator + } + #[doc = "System PLL clock out"] + #[inline(always)] + pub fn is_system_pll_clock_out(&self) -> bool { + *self == Sel::SystemPllClockOut + } +} +#[doc = "Field `SEL` writer - Clock source for main clock"] +pub type SelW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Sel>; +impl<'a, REG> SelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn irc_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::IrcOscillator) + } + #[doc = "Input clock to system PLL"] + #[inline(always)] + pub fn input_clock_to_syste(self) -> &'a mut crate::W { + self.variant(Sel::InputClockToSyste) + } + #[doc = "WDT oscillator"] + #[inline(always)] + pub fn wdt_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::WdtOscillator) + } + #[doc = "System PLL clock out"] + #[inline(always)] + pub fn system_pll_clock_out(self) -> &'a mut crate::W { + self.variant(Sel::SystemPllClockOut) + } +} +impl R { + #[doc = "Bits 0:1 - Clock source for main clock"] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Clock source for main clock"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 0) + } +} +#[doc = "Main clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mainclksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mainclksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MainclkselSpec; +impl crate::RegisterSpec for MainclkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mainclksel::R`](R) reader structure"] +impl crate::Readable for MainclkselSpec {} +#[doc = "`write(|w| ..)` method takes [`mainclksel::W`](W) writer structure"] +impl crate::Writable for MainclkselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAINCLKSEL to value 0"] +impl crate::Resettable for MainclkselSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/mainclkuen.rs b/rust-embedded/lpc111x-pac/src/syscon/mainclkuen.rs new file mode 100644 index 0000000..6bd0d44 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/mainclkuen.rs @@ -0,0 +1,89 @@ +#[doc = "Register `MAINCLKUEN` reader"] +pub type R = crate::R; +#[doc = "Register `MAINCLKUEN` writer"] +pub type W = crate::W; +#[doc = "Enable main clock source update\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ena { + #[doc = "0: No change"] + NoChange = 0, + #[doc = "1: Update clock source"] + UpdateClockSource = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA` reader - Enable main clock source update"] +pub type EnaR = crate::BitReader; +impl EnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ena { + match self.bits { + false => Ena::NoChange, + true => Ena::UpdateClockSource, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_no_change(&self) -> bool { + *self == Ena::NoChange + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn is_update_clock_source(&self) -> bool { + *self == Ena::UpdateClockSource + } +} +#[doc = "Field `ENA` writer - Enable main clock source update"] +pub type EnaW<'a, REG> = crate::BitWriter<'a, REG, Ena>; +impl<'a, REG> EnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn no_change(self) -> &'a mut crate::W { + self.variant(Ena::NoChange) + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn update_clock_source(self) -> &'a mut crate::W { + self.variant(Ena::UpdateClockSource) + } +} +impl R { + #[doc = "Bit 0 - Enable main clock source update"] + #[inline(always)] + pub fn ena(&self) -> EnaR { + EnaR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable main clock source update"] + #[inline(always)] + #[must_use] + pub fn ena(&mut self) -> EnaW { + EnaW::new(self, 0) + } +} +#[doc = "Main clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mainclkuen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mainclkuen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MainclkuenSpec; +impl crate::RegisterSpec for MainclkuenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mainclkuen::R`](R) reader structure"] +impl crate::Readable for MainclkuenSpec {} +#[doc = "`write(|w| ..)` method takes [`mainclkuen::W`](W) writer structure"] +impl crate::Writable for MainclkuenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAINCLKUEN to value 0"] +impl crate::Resettable for MainclkuenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/nmisrc.rs b/rust-embedded/lpc111x-pac/src/syscon/nmisrc.rs new file mode 100644 index 0000000..795b31c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/nmisrc.rs @@ -0,0 +1,55 @@ +#[doc = "Register `NMISRC` reader"] +pub type R = crate::R; +#[doc = "Register `NMISRC` writer"] +pub type W = crate::W; +#[doc = "Field `IRQNO` reader - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers."] +pub type IrqnoR = crate::FieldReader; +#[doc = "Field `IRQNO` writer - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers."] +pub type IrqnoW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `NMIEN` reader - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."] +pub type NmienR = crate::BitReader; +#[doc = "Field `NMIEN` writer - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."] +pub type NmienW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers."] + #[inline(always)] + pub fn irqno(&self) -> IrqnoR { + IrqnoR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 31 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."] + #[inline(always)] + pub fn nmien(&self) -> NmienR { + NmienR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers."] + #[inline(always)] + #[must_use] + pub fn irqno(&mut self) -> IrqnoW { + IrqnoW::new(self, 0) + } + #[doc = "Bit 31 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0."] + #[inline(always)] + #[must_use] + pub fn nmien(&mut self) -> NmienW { + NmienW::new(self, 31) + } +} +#[doc = "NMI source selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmisrc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmisrc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NmisrcSpec; +impl crate::RegisterSpec for NmisrcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`nmisrc::R`](R) reader structure"] +impl crate::Readable for NmisrcSpec {} +#[doc = "`write(|w| ..)` method takes [`nmisrc::W`](W) writer structure"] +impl crate::Writable for NmisrcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NMISRC to value 0"] +impl crate::Resettable for NmisrcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/pdawakecfg.rs b/rust-embedded/lpc111x-pac/src/syscon/pdawakecfg.rs new file mode 100644 index 0000000..e41d7e5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/pdawakecfg.rs @@ -0,0 +1,627 @@ +#[doc = "Register `PDAWAKECFG` reader"] +pub type R = crate::R; +#[doc = "Register `PDAWAKECFG` writer"] +pub type W = crate::W; +#[doc = "IRC oscillator output wake-up configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrcoutPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrcoutPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRCOUT_PD` reader - IRC oscillator output wake-up configuration"] +pub type IrcoutPdR = crate::BitReader; +impl IrcoutPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrcoutPd { + match self.bits { + false => IrcoutPd::Powered, + true => IrcoutPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == IrcoutPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == IrcoutPd::PoweredDown + } +} +#[doc = "Field `IRCOUT_PD` writer - IRC oscillator output wake-up configuration"] +pub type IrcoutPdW<'a, REG> = crate::BitWriter<'a, REG, IrcoutPd>; +impl<'a, REG> IrcoutPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(IrcoutPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(IrcoutPd::PoweredDown) + } +} +#[doc = "IRC oscillator power-down wake-up configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrcPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrcPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRC_PD` reader - IRC oscillator power-down wake-up configuration"] +pub type IrcPdR = crate::BitReader; +impl IrcPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrcPd { + match self.bits { + false => IrcPd::Powered, + true => IrcPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == IrcPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == IrcPd::PoweredDown + } +} +#[doc = "Field `IRC_PD` writer - IRC oscillator power-down wake-up configuration"] +pub type IrcPdW<'a, REG> = crate::BitWriter<'a, REG, IrcPd>; +impl<'a, REG> IrcPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(IrcPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(IrcPd::PoweredDown) + } +} +#[doc = "Flash wake-up configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FlashPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FlashPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASH_PD` reader - Flash wake-up configuration"] +pub type FlashPdR = crate::BitReader; +impl FlashPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FlashPd { + match self.bits { + false => FlashPd::Powered, + true => FlashPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == FlashPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == FlashPd::PoweredDown + } +} +#[doc = "Field `FLASH_PD` writer - Flash wake-up configuration"] +pub type FlashPdW<'a, REG> = crate::BitWriter<'a, REG, FlashPd>; +impl<'a, REG> FlashPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(FlashPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(FlashPd::PoweredDown) + } +} +#[doc = "BOD wake-up configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BodPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BodPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOD_PD` reader - BOD wake-up configuration"] +pub type BodPdR = crate::BitReader; +impl BodPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BodPd { + match self.bits { + false => BodPd::Powered, + true => BodPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == BodPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == BodPd::PoweredDown + } +} +#[doc = "Field `BOD_PD` writer - BOD wake-up configuration"] +pub type BodPdW<'a, REG> = crate::BitWriter<'a, REG, BodPd>; +impl<'a, REG> BodPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(BodPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(BodPd::PoweredDown) + } +} +#[doc = "ADC wake-up configuration\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AdcPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AdcPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC_PD` reader - ADC wake-up configuration"] +pub type AdcPdR = crate::BitReader; +impl AdcPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AdcPd { + match self.bits { + false => AdcPd::Powered, + true => AdcPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == AdcPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == AdcPd::PoweredDown + } +} +#[doc = "Field `ADC_PD` writer - ADC wake-up configuration"] +pub type AdcPdW<'a, REG> = crate::BitWriter<'a, REG, AdcPd>; +impl<'a, REG> AdcPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(AdcPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(AdcPd::PoweredDown) + } +} +#[doc = "System oscillator wake-up configuration\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysoscPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysoscPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSOSC_PD` reader - System oscillator wake-up configuration"] +pub type SysoscPdR = crate::BitReader; +impl SysoscPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysoscPd { + match self.bits { + false => SysoscPd::Powered, + true => SysoscPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == SysoscPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == SysoscPd::PoweredDown + } +} +#[doc = "Field `SYSOSC_PD` writer - System oscillator wake-up configuration"] +pub type SysoscPdW<'a, REG> = crate::BitWriter<'a, REG, SysoscPd>; +impl<'a, REG> SysoscPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(SysoscPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(SysoscPd::PoweredDown) + } +} +#[doc = "Watchdog oscillator wake-up configuration\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WdtoscPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WdtoscPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDTOSC_PD` reader - Watchdog oscillator wake-up configuration"] +pub type WdtoscPdR = crate::BitReader; +impl WdtoscPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WdtoscPd { + match self.bits { + false => WdtoscPd::Powered, + true => WdtoscPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == WdtoscPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == WdtoscPd::PoweredDown + } +} +#[doc = "Field `WDTOSC_PD` writer - Watchdog oscillator wake-up configuration"] +pub type WdtoscPdW<'a, REG> = crate::BitWriter<'a, REG, WdtoscPd>; +impl<'a, REG> WdtoscPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(WdtoscPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(WdtoscPd::PoweredDown) + } +} +#[doc = "System PLL wake-up configuration\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SyspllPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SyspllPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSPLL_PD` reader - System PLL wake-up configuration"] +pub type SyspllPdR = crate::BitReader; +impl SyspllPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SyspllPd { + match self.bits { + false => SyspllPd::Powered, + true => SyspllPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == SyspllPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == SyspllPd::PoweredDown + } +} +#[doc = "Field `SYSPLL_PD` writer - System PLL wake-up configuration"] +pub type SyspllPdW<'a, REG> = crate::BitWriter<'a, REG, SyspllPd>; +impl<'a, REG> SyspllPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(SyspllPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(SyspllPd::PoweredDown) + } +} +#[doc = "Field `NOTUSED0` reader - Reserved. Always write this bit as 1."] +pub type Notused0R = crate::BitReader; +#[doc = "Field `NOTUSED0` writer - Reserved. Always write this bit as 1."] +pub type Notused0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED1` reader - Reserved. Always write this bit as 0."] +pub type Notused1R = crate::BitReader; +#[doc = "Field `NOTUSED1` writer - Reserved. Always write this bit as 0."] +pub type Notused1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED2` reader - Reserved. Always write this bit as 1."] +pub type Notused2R = crate::BitReader; +#[doc = "Field `NOTUSED2` writer - Reserved. Always write this bit as 1."] +pub type Notused2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED3` reader - Reserved. Always write this bit as 1."] +pub type Notused3R = crate::BitReader; +#[doc = "Field `NOTUSED3` writer - Reserved. Always write this bit as 1."] +pub type Notused3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED4` reader - Reserved. Always write this bit as 0."] +pub type Notused4R = crate::BitReader; +#[doc = "Field `NOTUSED4` writer - Reserved. Always write this bit as 0."] +pub type Notused4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED5` reader - Reserved. Always write these bits as 111."] +pub type Notused5R = crate::FieldReader; +#[doc = "Field `NOTUSED5` writer - Reserved. Always write these bits as 111."] +pub type Notused5W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - IRC oscillator output wake-up configuration"] + #[inline(always)] + pub fn ircout_pd(&self) -> IrcoutPdR { + IrcoutPdR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - IRC oscillator power-down wake-up configuration"] + #[inline(always)] + pub fn irc_pd(&self) -> IrcPdR { + IrcPdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Flash wake-up configuration"] + #[inline(always)] + pub fn flash_pd(&self) -> FlashPdR { + FlashPdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD wake-up configuration"] + #[inline(always)] + pub fn bod_pd(&self) -> BodPdR { + BodPdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - ADC wake-up configuration"] + #[inline(always)] + pub fn adc_pd(&self) -> AdcPdR { + AdcPdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - System oscillator wake-up configuration"] + #[inline(always)] + pub fn sysosc_pd(&self) -> SysoscPdR { + SysoscPdR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Watchdog oscillator wake-up configuration"] + #[inline(always)] + pub fn wdtosc_pd(&self) -> WdtoscPdR { + WdtoscPdR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - System PLL wake-up configuration"] + #[inline(always)] + pub fn syspll_pd(&self) -> SyspllPdR { + SyspllPdR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused0(&self) -> Notused0R { + Notused0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved. Always write this bit as 0."] + #[inline(always)] + pub fn notused1(&self) -> Notused1R { + Notused1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused2(&self) -> Notused2R { + Notused2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused3(&self) -> Notused3R { + Notused3R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved. Always write this bit as 0."] + #[inline(always)] + pub fn notused4(&self) -> Notused4R { + Notused4R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - Reserved. Always write these bits as 111."] + #[inline(always)] + pub fn notused5(&self) -> Notused5R { + Notused5R::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - IRC oscillator output wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn ircout_pd(&mut self) -> IrcoutPdW { + IrcoutPdW::new(self, 0) + } + #[doc = "Bit 1 - IRC oscillator power-down wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn irc_pd(&mut self) -> IrcPdW { + IrcPdW::new(self, 1) + } + #[doc = "Bit 2 - Flash wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn flash_pd(&mut self) -> FlashPdW { + FlashPdW::new(self, 2) + } + #[doc = "Bit 3 - BOD wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn bod_pd(&mut self) -> BodPdW { + BodPdW::new(self, 3) + } + #[doc = "Bit 4 - ADC wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn adc_pd(&mut self) -> AdcPdW { + AdcPdW::new(self, 4) + } + #[doc = "Bit 5 - System oscillator wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn sysosc_pd(&mut self) -> SysoscPdW { + SysoscPdW::new(self, 5) + } + #[doc = "Bit 6 - Watchdog oscillator wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn wdtosc_pd(&mut self) -> WdtoscPdW { + WdtoscPdW::new(self, 6) + } + #[doc = "Bit 7 - System PLL wake-up configuration"] + #[inline(always)] + #[must_use] + pub fn syspll_pd(&mut self) -> SyspllPdW { + SyspllPdW::new(self, 7) + } + #[doc = "Bit 8 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused0(&mut self) -> Notused0W { + Notused0W::new(self, 8) + } + #[doc = "Bit 9 - Reserved. Always write this bit as 0."] + #[inline(always)] + #[must_use] + pub fn notused1(&mut self) -> Notused1W { + Notused1W::new(self, 9) + } + #[doc = "Bit 10 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused2(&mut self) -> Notused2W { + Notused2W::new(self, 10) + } + #[doc = "Bit 11 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused3(&mut self) -> Notused3W { + Notused3W::new(self, 11) + } + #[doc = "Bit 12 - Reserved. Always write this bit as 0."] + #[inline(always)] + #[must_use] + pub fn notused4(&mut self) -> Notused4W { + Notused4W::new(self, 12) + } + #[doc = "Bits 13:15 - Reserved. Always write these bits as 111."] + #[inline(always)] + #[must_use] + pub fn notused5(&mut self) -> Notused5W { + Notused5W::new(self, 13) + } +} +#[doc = "Power-down states after wake-up from Deep-sleep mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdawakecfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdawakecfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdawakecfgSpec; +impl crate::RegisterSpec for PdawakecfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdawakecfg::R`](R) reader structure"] +impl crate::Readable for PdawakecfgSpec {} +#[doc = "`write(|w| ..)` method takes [`pdawakecfg::W`](W) writer structure"] +impl crate::Writable for PdawakecfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PDAWAKECFG to value 0xedf0"] +impl crate::Resettable for PdawakecfgSpec { + const RESET_VALUE: u32 = 0xedf0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/pdruncfg.rs b/rust-embedded/lpc111x-pac/src/syscon/pdruncfg.rs new file mode 100644 index 0000000..73da093 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/pdruncfg.rs @@ -0,0 +1,627 @@ +#[doc = "Register `PDRUNCFG` reader"] +pub type R = crate::R; +#[doc = "Register `PDRUNCFG` writer"] +pub type W = crate::W; +#[doc = "IRC oscillator output power-down\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrcoutPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrcoutPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRCOUT_PD` reader - IRC oscillator output power-down"] +pub type IrcoutPdR = crate::BitReader; +impl IrcoutPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrcoutPd { + match self.bits { + false => IrcoutPd::Powered, + true => IrcoutPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == IrcoutPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == IrcoutPd::PoweredDown + } +} +#[doc = "Field `IRCOUT_PD` writer - IRC oscillator output power-down"] +pub type IrcoutPdW<'a, REG> = crate::BitWriter<'a, REG, IrcoutPd>; +impl<'a, REG> IrcoutPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(IrcoutPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(IrcoutPd::PoweredDown) + } +} +#[doc = "IRC oscillator power-down\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IrcPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IrcPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IRC_PD` reader - IRC oscillator power-down"] +pub type IrcPdR = crate::BitReader; +impl IrcPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IrcPd { + match self.bits { + false => IrcPd::Powered, + true => IrcPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == IrcPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == IrcPd::PoweredDown + } +} +#[doc = "Field `IRC_PD` writer - IRC oscillator power-down"] +pub type IrcPdW<'a, REG> = crate::BitWriter<'a, REG, IrcPd>; +impl<'a, REG> IrcPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(IrcPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(IrcPd::PoweredDown) + } +} +#[doc = "Flash power-down\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FlashPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FlashPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASH_PD` reader - Flash power-down"] +pub type FlashPdR = crate::BitReader; +impl FlashPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FlashPd { + match self.bits { + false => FlashPd::Powered, + true => FlashPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == FlashPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == FlashPd::PoweredDown + } +} +#[doc = "Field `FLASH_PD` writer - Flash power-down"] +pub type FlashPdW<'a, REG> = crate::BitWriter<'a, REG, FlashPd>; +impl<'a, REG> FlashPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(FlashPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(FlashPd::PoweredDown) + } +} +#[doc = "BOD power-down\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BodPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BodPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOD_PD` reader - BOD power-down"] +pub type BodPdR = crate::BitReader; +impl BodPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BodPd { + match self.bits { + false => BodPd::Powered, + true => BodPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == BodPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == BodPd::PoweredDown + } +} +#[doc = "Field `BOD_PD` writer - BOD power-down"] +pub type BodPdW<'a, REG> = crate::BitWriter<'a, REG, BodPd>; +impl<'a, REG> BodPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(BodPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(BodPd::PoweredDown) + } +} +#[doc = "ADC power-down\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum AdcPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: AdcPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC_PD` reader - ADC power-down"] +pub type AdcPdR = crate::BitReader; +impl AdcPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AdcPd { + match self.bits { + false => AdcPd::Powered, + true => AdcPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == AdcPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == AdcPd::PoweredDown + } +} +#[doc = "Field `ADC_PD` writer - ADC power-down"] +pub type AdcPdW<'a, REG> = crate::BitWriter<'a, REG, AdcPd>; +impl<'a, REG> AdcPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(AdcPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(AdcPd::PoweredDown) + } +} +#[doc = "System oscillator power-down\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SysoscPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SysoscPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSOSC_PD` reader - System oscillator power-down"] +pub type SysoscPdR = crate::BitReader; +impl SysoscPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SysoscPd { + match self.bits { + false => SysoscPd::Powered, + true => SysoscPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == SysoscPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == SysoscPd::PoweredDown + } +} +#[doc = "Field `SYSOSC_PD` writer - System oscillator power-down"] +pub type SysoscPdW<'a, REG> = crate::BitWriter<'a, REG, SysoscPd>; +impl<'a, REG> SysoscPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(SysoscPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(SysoscPd::PoweredDown) + } +} +#[doc = "Watchdog oscillator power-down\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WdtoscPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WdtoscPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDTOSC_PD` reader - Watchdog oscillator power-down"] +pub type WdtoscPdR = crate::BitReader; +impl WdtoscPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WdtoscPd { + match self.bits { + false => WdtoscPd::Powered, + true => WdtoscPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == WdtoscPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == WdtoscPd::PoweredDown + } +} +#[doc = "Field `WDTOSC_PD` writer - Watchdog oscillator power-down"] +pub type WdtoscPdW<'a, REG> = crate::BitWriter<'a, REG, WdtoscPd>; +impl<'a, REG> WdtoscPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(WdtoscPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(WdtoscPd::PoweredDown) + } +} +#[doc = "System PLL power-down\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SyspllPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SyspllPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSPLL_PD` reader - System PLL power-down"] +pub type SyspllPdR = crate::BitReader; +impl SyspllPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SyspllPd { + match self.bits { + false => SyspllPd::Powered, + true => SyspllPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == SyspllPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == SyspllPd::PoweredDown + } +} +#[doc = "Field `SYSPLL_PD` writer - System PLL power-down"] +pub type SyspllPdW<'a, REG> = crate::BitWriter<'a, REG, SyspllPd>; +impl<'a, REG> SyspllPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(SyspllPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(SyspllPd::PoweredDown) + } +} +#[doc = "Field `NOTUSED0` reader - Reserved. Always write this bit as 1."] +pub type Notused0R = crate::BitReader; +#[doc = "Field `NOTUSED0` writer - Reserved. Always write this bit as 1."] +pub type Notused0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED1` reader - Reserved. Always write this bit as 0."] +pub type Notused1R = crate::BitReader; +#[doc = "Field `NOTUSED1` writer - Reserved. Always write this bit as 0."] +pub type Notused1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED2` reader - Reserved. Always write this bit as 1."] +pub type Notused2R = crate::BitReader; +#[doc = "Field `NOTUSED2` writer - Reserved. Always write this bit as 1."] +pub type Notused2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED3` reader - Reserved. Always write this bit as 1."] +pub type Notused3R = crate::BitReader; +#[doc = "Field `NOTUSED3` writer - Reserved. Always write this bit as 1."] +pub type Notused3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED4` reader - Reserved. Always write this bit as 0."] +pub type Notused4R = crate::BitReader; +#[doc = "Field `NOTUSED4` writer - Reserved. Always write this bit as 0."] +pub type Notused4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED5` reader - Reserved. Always write these bits as 111."] +pub type Notused5R = crate::FieldReader; +#[doc = "Field `NOTUSED5` writer - Reserved. Always write these bits as 111."] +pub type Notused5W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bit 0 - IRC oscillator output power-down"] + #[inline(always)] + pub fn ircout_pd(&self) -> IrcoutPdR { + IrcoutPdR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - IRC oscillator power-down"] + #[inline(always)] + pub fn irc_pd(&self) -> IrcPdR { + IrcPdR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Flash power-down"] + #[inline(always)] + pub fn flash_pd(&self) -> FlashPdR { + FlashPdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD power-down"] + #[inline(always)] + pub fn bod_pd(&self) -> BodPdR { + BodPdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - ADC power-down"] + #[inline(always)] + pub fn adc_pd(&self) -> AdcPdR { + AdcPdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - System oscillator power-down"] + #[inline(always)] + pub fn sysosc_pd(&self) -> SysoscPdR { + SysoscPdR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Watchdog oscillator power-down"] + #[inline(always)] + pub fn wdtosc_pd(&self) -> WdtoscPdR { + WdtoscPdR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - System PLL power-down"] + #[inline(always)] + pub fn syspll_pd(&self) -> SyspllPdR { + SyspllPdR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused0(&self) -> Notused0R { + Notused0R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved. Always write this bit as 0."] + #[inline(always)] + pub fn notused1(&self) -> Notused1R { + Notused1R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused2(&self) -> Notused2R { + Notused2R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused3(&self) -> Notused3R { + Notused3R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reserved. Always write this bit as 0."] + #[inline(always)] + pub fn notused4(&self) -> Notused4R { + Notused4R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - Reserved. Always write these bits as 111."] + #[inline(always)] + pub fn notused5(&self) -> Notused5R { + Notused5R::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - IRC oscillator output power-down"] + #[inline(always)] + #[must_use] + pub fn ircout_pd(&mut self) -> IrcoutPdW { + IrcoutPdW::new(self, 0) + } + #[doc = "Bit 1 - IRC oscillator power-down"] + #[inline(always)] + #[must_use] + pub fn irc_pd(&mut self) -> IrcPdW { + IrcPdW::new(self, 1) + } + #[doc = "Bit 2 - Flash power-down"] + #[inline(always)] + #[must_use] + pub fn flash_pd(&mut self) -> FlashPdW { + FlashPdW::new(self, 2) + } + #[doc = "Bit 3 - BOD power-down"] + #[inline(always)] + #[must_use] + pub fn bod_pd(&mut self) -> BodPdW { + BodPdW::new(self, 3) + } + #[doc = "Bit 4 - ADC power-down"] + #[inline(always)] + #[must_use] + pub fn adc_pd(&mut self) -> AdcPdW { + AdcPdW::new(self, 4) + } + #[doc = "Bit 5 - System oscillator power-down"] + #[inline(always)] + #[must_use] + pub fn sysosc_pd(&mut self) -> SysoscPdW { + SysoscPdW::new(self, 5) + } + #[doc = "Bit 6 - Watchdog oscillator power-down"] + #[inline(always)] + #[must_use] + pub fn wdtosc_pd(&mut self) -> WdtoscPdW { + WdtoscPdW::new(self, 6) + } + #[doc = "Bit 7 - System PLL power-down"] + #[inline(always)] + #[must_use] + pub fn syspll_pd(&mut self) -> SyspllPdW { + SyspllPdW::new(self, 7) + } + #[doc = "Bit 8 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused0(&mut self) -> Notused0W { + Notused0W::new(self, 8) + } + #[doc = "Bit 9 - Reserved. Always write this bit as 0."] + #[inline(always)] + #[must_use] + pub fn notused1(&mut self) -> Notused1W { + Notused1W::new(self, 9) + } + #[doc = "Bit 10 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused2(&mut self) -> Notused2W { + Notused2W::new(self, 10) + } + #[doc = "Bit 11 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused3(&mut self) -> Notused3W { + Notused3W::new(self, 11) + } + #[doc = "Bit 12 - Reserved. Always write this bit as 0."] + #[inline(always)] + #[must_use] + pub fn notused4(&mut self) -> Notused4W { + Notused4W::new(self, 12) + } + #[doc = "Bits 13:15 - Reserved. Always write these bits as 111."] + #[inline(always)] + #[must_use] + pub fn notused5(&mut self) -> Notused5W { + Notused5W::new(self, 13) + } +} +#[doc = "Power-down configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdruncfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdruncfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdruncfgSpec; +impl crate::RegisterSpec for PdruncfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdruncfg::R`](R) reader structure"] +impl crate::Readable for PdruncfgSpec {} +#[doc = "`write(|w| ..)` method takes [`pdruncfg::W`](W) writer structure"] +impl crate::Writable for PdruncfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PDRUNCFG to value 0xedf0"] +impl crate::Resettable for PdruncfgSpec { + const RESET_VALUE: u32 = 0xedf0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/pdsleepcfg.rs b/rust-embedded/lpc111x-pac/src/syscon/pdsleepcfg.rs new file mode 100644 index 0000000..da7c577 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/pdsleepcfg.rs @@ -0,0 +1,228 @@ +#[doc = "Register `PDSLEEPCFG` reader"] +pub type R = crate::R; +#[doc = "Register `PDSLEEPCFG` writer"] +pub type W = crate::W; +#[doc = "Field `NOTUSED0` reader - Reserved. Always write these bits as 111."] +pub type Notused0R = crate::FieldReader; +#[doc = "Field `NOTUSED0` writer - Reserved. Always write these bits as 111."] +pub type Notused0W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "BOD power-down control in Deep-sleep mode, see Table 40.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum BodPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: BodPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOD_PD` reader - BOD power-down control in Deep-sleep mode, see Table 40."] +pub type BodPdR = crate::BitReader; +impl BodPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> BodPd { + match self.bits { + false => BodPd::Powered, + true => BodPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == BodPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == BodPd::PoweredDown + } +} +#[doc = "Field `BOD_PD` writer - BOD power-down control in Deep-sleep mode, see Table 40."] +pub type BodPdW<'a, REG> = crate::BitWriter<'a, REG, BodPd>; +impl<'a, REG> BodPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(BodPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(BodPd::PoweredDown) + } +} +#[doc = "Field `NOTUSED1` reader - Reserved. Always write these bits as 11."] +pub type Notused1R = crate::FieldReader; +#[doc = "Field `NOTUSED1` writer - Reserved. Always write these bits as 11."] +pub type Notused1W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Watchdog oscillator power control in Deep-sleep mode, see Table 40.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WdtoscPd { + #[doc = "0: Powered"] + Powered = 0, + #[doc = "1: Powered down"] + PoweredDown = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WdtoscPd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDTOSC_PD` reader - Watchdog oscillator power control in Deep-sleep mode, see Table 40."] +pub type WdtoscPdR = crate::BitReader; +impl WdtoscPdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> WdtoscPd { + match self.bits { + false => WdtoscPd::Powered, + true => WdtoscPd::PoweredDown, + } + } + #[doc = "Powered"] + #[inline(always)] + pub fn is_powered(&self) -> bool { + *self == WdtoscPd::Powered + } + #[doc = "Powered down"] + #[inline(always)] + pub fn is_powered_down(&self) -> bool { + *self == WdtoscPd::PoweredDown + } +} +#[doc = "Field `WDTOSC_PD` writer - Watchdog oscillator power control in Deep-sleep mode, see Table 40."] +pub type WdtoscPdW<'a, REG> = crate::BitWriter<'a, REG, WdtoscPd>; +impl<'a, REG> WdtoscPdW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Powered"] + #[inline(always)] + pub fn powered(self) -> &'a mut crate::W { + self.variant(WdtoscPd::Powered) + } + #[doc = "Powered down"] + #[inline(always)] + pub fn powered_down(self) -> &'a mut crate::W { + self.variant(WdtoscPd::PoweredDown) + } +} +#[doc = "Field `NOTUSED2` reader - Reserved. Always write this bit as 1."] +pub type Notused2R = crate::BitReader; +#[doc = "Field `NOTUSED2` writer - Reserved. Always write this bit as 1."] +pub type Notused2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOTUSED3` reader - Reserved. Always write these bits as 000."] +pub type Notused3R = crate::FieldReader; +#[doc = "Field `NOTUSED3` writer - Reserved. Always write these bits as 000."] +pub type Notused3W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `NOTUSED4` reader - Reserved. Always write these bits as 11."] +pub type Notused4R = crate::FieldReader; +#[doc = "Field `NOTUSED4` writer - Reserved. Always write these bits as 11."] +pub type Notused4W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:2 - Reserved. Always write these bits as 111."] + #[inline(always)] + pub fn notused0(&self) -> Notused0R { + Notused0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - BOD power-down control in Deep-sleep mode, see Table 40."] + #[inline(always)] + pub fn bod_pd(&self) -> BodPdR { + BodPdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Reserved. Always write these bits as 11."] + #[inline(always)] + pub fn notused1(&self) -> Notused1R { + Notused1R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Watchdog oscillator power control in Deep-sleep mode, see Table 40."] + #[inline(always)] + pub fn wdtosc_pd(&self) -> WdtoscPdR { + WdtoscPdR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Reserved. Always write this bit as 1."] + #[inline(always)] + pub fn notused2(&self) -> Notused2R { + Notused2R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Reserved. Always write these bits as 000."] + #[inline(always)] + pub fn notused3(&self) -> Notused3R { + Notused3R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 11:12 - Reserved. Always write these bits as 11."] + #[inline(always)] + pub fn notused4(&self) -> Notused4R { + Notused4R::new(((self.bits >> 11) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Reserved. Always write these bits as 111."] + #[inline(always)] + #[must_use] + pub fn notused0(&mut self) -> Notused0W { + Notused0W::new(self, 0) + } + #[doc = "Bit 3 - BOD power-down control in Deep-sleep mode, see Table 40."] + #[inline(always)] + #[must_use] + pub fn bod_pd(&mut self) -> BodPdW { + BodPdW::new(self, 3) + } + #[doc = "Bits 4:5 - Reserved. Always write these bits as 11."] + #[inline(always)] + #[must_use] + pub fn notused1(&mut self) -> Notused1W { + Notused1W::new(self, 4) + } + #[doc = "Bit 6 - Watchdog oscillator power control in Deep-sleep mode, see Table 40."] + #[inline(always)] + #[must_use] + pub fn wdtosc_pd(&mut self) -> WdtoscPdW { + WdtoscPdW::new(self, 6) + } + #[doc = "Bit 7 - Reserved. Always write this bit as 1."] + #[inline(always)] + #[must_use] + pub fn notused2(&mut self) -> Notused2W { + Notused2W::new(self, 7) + } + #[doc = "Bits 8:10 - Reserved. Always write these bits as 000."] + #[inline(always)] + #[must_use] + pub fn notused3(&mut self) -> Notused3W { + Notused3W::new(self, 8) + } + #[doc = "Bits 11:12 - Reserved. Always write these bits as 11."] + #[inline(always)] + #[must_use] + pub fn notused4(&mut self) -> Notused4W { + Notused4W::new(self, 11) + } +} +#[doc = "Power-down states in Deep-sleep mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsleepcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdsleepcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PdsleepcfgSpec; +impl crate::RegisterSpec for PdsleepcfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pdsleepcfg::R`](R) reader structure"] +impl crate::Readable for PdsleepcfgSpec {} +#[doc = "`write(|w| ..)` method takes [`pdsleepcfg::W`](W) writer structure"] +impl crate::Writable for PdsleepcfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PDSLEEPCFG to value 0"] +impl crate::Resettable for PdsleepcfgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/pioporcap0.rs b/rust-embedded/lpc111x-pac/src/syscon/pioporcap0.rs new file mode 100644 index 0000000..9e7695c --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/pioporcap0.rs @@ -0,0 +1,36 @@ +#[doc = "Register `PIOPORCAP0` reader"] +pub type R = crate::R; +#[doc = "Field `CAPPIO0_n` reader - Raw reset status input PIO0_n: PIO0_11 to PIO0_0"] +pub type Cappio0NR = crate::FieldReader; +#[doc = "Field `CAPPIO1_n` reader - Raw reset status input PIO1_n: PIO1_11 to PIO1_0"] +pub type Cappio1NR = crate::FieldReader; +#[doc = "Field `CAPPIO2_n` reader - Raw reset status input PIO2_n: PIO2_7 to PIO2_0"] +pub type Cappio2NR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Raw reset status input PIO0_n: PIO0_11 to PIO0_0"] + #[inline(always)] + pub fn cappio0_n(&self) -> Cappio0NR { + Cappio0NR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - Raw reset status input PIO1_n: PIO1_11 to PIO1_0"] + #[inline(always)] + pub fn cappio1_n(&self) -> Cappio1NR { + Cappio1NR::new(((self.bits >> 12) & 0x0fff) as u16) + } + #[doc = "Bits 24:31 - Raw reset status input PIO2_n: PIO2_7 to PIO2_0"] + #[inline(always)] + pub fn cappio2_n(&self) -> Cappio2NR { + Cappio2NR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "POR captured PIO status 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pioporcap0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pioporcap0Spec; +impl crate::RegisterSpec for Pioporcap0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pioporcap0::R`](R) reader structure"] +impl crate::Readable for Pioporcap0Spec {} +#[doc = "`reset()` method sets PIOPORCAP0 to value 0"] +impl crate::Resettable for Pioporcap0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/pioporcap1.rs b/rust-embedded/lpc111x-pac/src/syscon/pioporcap1.rs new file mode 100644 index 0000000..b30a58d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/pioporcap1.rs @@ -0,0 +1,85 @@ +#[doc = "Register `PIOPORCAP1` reader"] +pub type R = crate::R; +#[doc = "Field `CAPPIO2_8` reader - Raw reset status input PIO2_8"] +pub type Cappio2_8R = crate::BitReader; +#[doc = "Field `CAPPIO2_9` reader - Raw reset status input PIO2_9"] +pub type Cappio2_9R = crate::BitReader; +#[doc = "Field `CAPPIO2_10` reader - Raw reset status input PIO2_10"] +pub type Cappio2_10R = crate::BitReader; +#[doc = "Field `CAPPIO2_11` reader - Raw reset status input PIO2_11"] +pub type Cappio2_11R = crate::BitReader; +#[doc = "Field `CAPPIO3_0` reader - Raw reset status input PIO3_0"] +pub type Cappio3_0R = crate::BitReader; +#[doc = "Field `CAPPIO3_1` reader - Raw reset status input PIO3_1"] +pub type Cappio3_1R = crate::BitReader; +#[doc = "Field `CAPPIO3_2` reader - Raw reset status input PIO3_2"] +pub type Cappio3_2R = crate::BitReader; +#[doc = "Field `CAPPIO3_3` reader - Raw reset status input PIO3_3"] +pub type Cappio3_3R = crate::BitReader; +#[doc = "Field `CAPPIO3_4` reader - Raw reset status input PIO3_4"] +pub type Cappio3_4R = crate::BitReader; +#[doc = "Field `CAPPIO3_5` reader - Raw reset status input PIO3_5"] +pub type Cappio3_5R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Raw reset status input PIO2_8"] + #[inline(always)] + pub fn cappio2_8(&self) -> Cappio2_8R { + Cappio2_8R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Raw reset status input PIO2_9"] + #[inline(always)] + pub fn cappio2_9(&self) -> Cappio2_9R { + Cappio2_9R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Raw reset status input PIO2_10"] + #[inline(always)] + pub fn cappio2_10(&self) -> Cappio2_10R { + Cappio2_10R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raw reset status input PIO2_11"] + #[inline(always)] + pub fn cappio2_11(&self) -> Cappio2_11R { + Cappio2_11R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raw reset status input PIO3_0"] + #[inline(always)] + pub fn cappio3_0(&self) -> Cappio3_0R { + Cappio3_0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Raw reset status input PIO3_1"] + #[inline(always)] + pub fn cappio3_1(&self) -> Cappio3_1R { + Cappio3_1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Raw reset status input PIO3_2"] + #[inline(always)] + pub fn cappio3_2(&self) -> Cappio3_2R { + Cappio3_2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Raw reset status input PIO3_3"] + #[inline(always)] + pub fn cappio3_3(&self) -> Cappio3_3R { + Cappio3_3R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Raw reset status input PIO3_4"] + #[inline(always)] + pub fn cappio3_4(&self) -> Cappio3_4R { + Cappio3_4R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Raw reset status input PIO3_5"] + #[inline(always)] + pub fn cappio3_5(&self) -> Cappio3_5R { + Cappio3_5R::new(((self.bits >> 9) & 1) != 0) + } +} +#[doc = "POR captured PIO status 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pioporcap1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Pioporcap1Spec; +impl crate::RegisterSpec for Pioporcap1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pioporcap1::R`](R) reader structure"] +impl crate::Readable for Pioporcap1Spec {} +#[doc = "`reset()` method sets PIOPORCAP1 to value 0"] +impl crate::Resettable for Pioporcap1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/presetctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/presetctrl.rs new file mode 100644 index 0000000..c796786 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/presetctrl.rs @@ -0,0 +1,281 @@ +#[doc = "Register `PRESETCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PRESETCTRL` writer"] +pub type W = crate::W; +#[doc = "SPI0 reset control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ssp0RstN { + #[doc = "0: Resets the SPI0 peripheral."] + Spio0reset = 0, + #[doc = "1: SPI0 reset de-asserted."] + Spio0noreset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ssp0RstN) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSP0_RST_N` reader - SPI0 reset control"] +pub type Ssp0RstNR = crate::BitReader; +impl Ssp0RstNR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ssp0RstN { + match self.bits { + false => Ssp0RstN::Spio0reset, + true => Ssp0RstN::Spio0noreset, + } + } + #[doc = "Resets the SPI0 peripheral."] + #[inline(always)] + pub fn is_spio0reset(&self) -> bool { + *self == Ssp0RstN::Spio0reset + } + #[doc = "SPI0 reset de-asserted."] + #[inline(always)] + pub fn is_spio0noreset(&self) -> bool { + *self == Ssp0RstN::Spio0noreset + } +} +#[doc = "Field `SSP0_RST_N` writer - SPI0 reset control"] +pub type Ssp0RstNW<'a, REG> = crate::BitWriter<'a, REG, Ssp0RstN>; +impl<'a, REG> Ssp0RstNW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Resets the SPI0 peripheral."] + #[inline(always)] + pub fn spio0reset(self) -> &'a mut crate::W { + self.variant(Ssp0RstN::Spio0reset) + } + #[doc = "SPI0 reset de-asserted."] + #[inline(always)] + pub fn spio0noreset(self) -> &'a mut crate::W { + self.variant(Ssp0RstN::Spio0noreset) + } +} +#[doc = "I2C reset control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2cRstN { + #[doc = "0: Resets the I2C peripheral."] + I2creset = 0, + #[doc = "1: I2C reset de-asserted."] + I2cnoreset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2cRstN) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I2C_RST_N` reader - I2C reset control"] +pub type I2cRstNR = crate::BitReader; +impl I2cRstNR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I2cRstN { + match self.bits { + false => I2cRstN::I2creset, + true => I2cRstN::I2cnoreset, + } + } + #[doc = "Resets the I2C peripheral."] + #[inline(always)] + pub fn is_i2creset(&self) -> bool { + *self == I2cRstN::I2creset + } + #[doc = "I2C reset de-asserted."] + #[inline(always)] + pub fn is_i2cnoreset(&self) -> bool { + *self == I2cRstN::I2cnoreset + } +} +#[doc = "Field `I2C_RST_N` writer - I2C reset control"] +pub type I2cRstNW<'a, REG> = crate::BitWriter<'a, REG, I2cRstN>; +impl<'a, REG> I2cRstNW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Resets the I2C peripheral."] + #[inline(always)] + pub fn i2creset(self) -> &'a mut crate::W { + self.variant(I2cRstN::I2creset) + } + #[doc = "I2C reset de-asserted."] + #[inline(always)] + pub fn i2cnoreset(self) -> &'a mut crate::W { + self.variant(I2cRstN::I2cnoreset) + } +} +#[doc = "SPI1 reset control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ssp1RstN { + #[doc = "0: Resets the SPI1 peripheral."] + Spi1reset = 0, + #[doc = "1: SPI1 reset de-asserted."] + Spi2noreset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ssp1RstN) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSP1_RST_N` reader - SPI1 reset control"] +pub type Ssp1RstNR = crate::BitReader; +impl Ssp1RstNR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ssp1RstN { + match self.bits { + false => Ssp1RstN::Spi1reset, + true => Ssp1RstN::Spi2noreset, + } + } + #[doc = "Resets the SPI1 peripheral."] + #[inline(always)] + pub fn is_spi1reset(&self) -> bool { + *self == Ssp1RstN::Spi1reset + } + #[doc = "SPI1 reset de-asserted."] + #[inline(always)] + pub fn is_spi2noreset(&self) -> bool { + *self == Ssp1RstN::Spi2noreset + } +} +#[doc = "Field `SSP1_RST_N` writer - SPI1 reset control"] +pub type Ssp1RstNW<'a, REG> = crate::BitWriter<'a, REG, Ssp1RstN>; +impl<'a, REG> Ssp1RstNW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Resets the SPI1 peripheral."] + #[inline(always)] + pub fn spi1reset(self) -> &'a mut crate::W { + self.variant(Ssp1RstN::Spi1reset) + } + #[doc = "SPI1 reset de-asserted."] + #[inline(always)] + pub fn spi2noreset(self) -> &'a mut crate::W { + self.variant(Ssp1RstN::Spi2noreset) + } +} +#[doc = "C_CAN reset control. See Section 3.1 for part specific details.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CanRstN { + #[doc = "0: Resets the C_CAN peripheral."] + Canreset = 0, + #[doc = "1: C_CAN reset de-asserted."] + Cannoreset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CanRstN) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAN_RST_N` reader - C_CAN reset control. See Section 3.1 for part specific details."] +pub type CanRstNR = crate::BitReader; +impl CanRstNR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CanRstN { + match self.bits { + false => CanRstN::Canreset, + true => CanRstN::Cannoreset, + } + } + #[doc = "Resets the C_CAN peripheral."] + #[inline(always)] + pub fn is_canreset(&self) -> bool { + *self == CanRstN::Canreset + } + #[doc = "C_CAN reset de-asserted."] + #[inline(always)] + pub fn is_cannoreset(&self) -> bool { + *self == CanRstN::Cannoreset + } +} +#[doc = "Field `CAN_RST_N` writer - C_CAN reset control. See Section 3.1 for part specific details."] +pub type CanRstNW<'a, REG> = crate::BitWriter<'a, REG, CanRstN>; +impl<'a, REG> CanRstNW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Resets the C_CAN peripheral."] + #[inline(always)] + pub fn canreset(self) -> &'a mut crate::W { + self.variant(CanRstN::Canreset) + } + #[doc = "C_CAN reset de-asserted."] + #[inline(always)] + pub fn cannoreset(self) -> &'a mut crate::W { + self.variant(CanRstN::Cannoreset) + } +} +impl R { + #[doc = "Bit 0 - SPI0 reset control"] + #[inline(always)] + pub fn ssp0_rst_n(&self) -> Ssp0RstNR { + Ssp0RstNR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C reset control"] + #[inline(always)] + pub fn i2c_rst_n(&self) -> I2cRstNR { + I2cRstNR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SPI1 reset control"] + #[inline(always)] + pub fn ssp1_rst_n(&self) -> Ssp1RstNR { + Ssp1RstNR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - C_CAN reset control. See Section 3.1 for part specific details."] + #[inline(always)] + pub fn can_rst_n(&self) -> CanRstNR { + CanRstNR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SPI0 reset control"] + #[inline(always)] + #[must_use] + pub fn ssp0_rst_n(&mut self) -> Ssp0RstNW { + Ssp0RstNW::new(self, 0) + } + #[doc = "Bit 1 - I2C reset control"] + #[inline(always)] + #[must_use] + pub fn i2c_rst_n(&mut self) -> I2cRstNW { + I2cRstNW::new(self, 1) + } + #[doc = "Bit 2 - SPI1 reset control"] + #[inline(always)] + #[must_use] + pub fn ssp1_rst_n(&mut self) -> Ssp1RstNW { + Ssp1RstNW::new(self, 2) + } + #[doc = "Bit 3 - C_CAN reset control. See Section 3.1 for part specific details."] + #[inline(always)] + #[must_use] + pub fn can_rst_n(&mut self) -> CanRstNW { + CanRstNW::new(self, 3) + } +} +#[doc = "Peripheral reset control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`presetctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`presetctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PresetctrlSpec; +impl crate::RegisterSpec for PresetctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`presetctrl::R`](R) reader structure"] +impl crate::Readable for PresetctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`presetctrl::W`](W) writer structure"] +impl crate::Writable for PresetctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRESETCTRL to value 0"] +impl crate::Resettable for PresetctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/ssp0clkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/ssp0clkdiv.rs new file mode 100644 index 0000000..32a9730 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/ssp0clkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SSP0CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SSP0CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "SPI0 clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp0clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp0clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ssp0clkdivSpec; +impl crate::RegisterSpec for Ssp0clkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssp0clkdiv::R`](R) reader structure"] +impl crate::Readable for Ssp0clkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`ssp0clkdiv::W`](W) writer structure"] +impl crate::Writable for Ssp0clkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSP0CLKDIV to value 0"] +impl crate::Resettable for Ssp0clkdivSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/ssp1clkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/ssp1clkdiv.rs new file mode 100644 index 0000000..64a7eaf --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/ssp1clkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SSP1CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SSP1CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "SPI1 clock divder\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssp1clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssp1clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ssp1clkdivSpec; +impl crate::RegisterSpec for Ssp1clkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssp1clkdiv::R`](R) reader structure"] +impl crate::Readable for Ssp1clkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`ssp1clkdiv::W`](W) writer structure"] +impl crate::Writable for Ssp1clkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSP1CLKDIV to value 0"] +impl crate::Resettable for Ssp1clkdivSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/startaprp0.rs b/rust-embedded/lpc111x-pac/src/syscon/startaprp0.rs new file mode 100644 index 0000000..8a2c29a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/startaprp0.rs @@ -0,0 +1,220 @@ +#[doc = "Register `STARTAPRP0` reader"] +pub type R = crate::R; +#[doc = "Register `STARTAPRP0` writer"] +pub type W = crate::W; +#[doc = "Field `APRPIO0_0` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_0R = crate::BitReader; +#[doc = "Field `APRPIO0_0` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_1` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_1R = crate::BitReader; +#[doc = "Field `APRPIO0_1` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_2` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_2R = crate::BitReader; +#[doc = "Field `APRPIO0_2` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_3` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_3R = crate::BitReader; +#[doc = "Field `APRPIO0_3` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_4` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_4R = crate::BitReader; +#[doc = "Field `APRPIO0_4` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_5` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_5R = crate::BitReader; +#[doc = "Field `APRPIO0_5` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_6` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_6R = crate::BitReader; +#[doc = "Field `APRPIO0_6` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_7` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_7R = crate::BitReader; +#[doc = "Field `APRPIO0_7` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_8` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_8R = crate::BitReader; +#[doc = "Field `APRPIO0_8` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_9` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_9R = crate::BitReader; +#[doc = "Field `APRPIO0_9` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_10` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_10R = crate::BitReader; +#[doc = "Field `APRPIO0_10` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO0_11` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_11R = crate::BitReader; +#[doc = "Field `APRPIO0_11` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio0_11W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APRPIO1_0` reader - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio1_0R = crate::BitReader; +#[doc = "Field `APRPIO1_0` writer - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"] +pub type Aprpio1_0W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_0(&self) -> Aprpio0_0R { + Aprpio0_0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_1(&self) -> Aprpio0_1R { + Aprpio0_1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_2(&self) -> Aprpio0_2R { + Aprpio0_2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_3(&self) -> Aprpio0_3R { + Aprpio0_3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_4(&self) -> Aprpio0_4R { + Aprpio0_4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_5(&self) -> Aprpio0_5R { + Aprpio0_5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_6(&self) -> Aprpio0_6R { + Aprpio0_6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_7(&self) -> Aprpio0_7R { + Aprpio0_7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_8(&self) -> Aprpio0_8R { + Aprpio0_8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_9(&self) -> Aprpio0_9R { + Aprpio0_9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_10(&self) -> Aprpio0_10R { + Aprpio0_10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio0_11(&self) -> Aprpio0_11R { + Aprpio0_11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + pub fn aprpio1_0(&self) -> Aprpio1_0R { + Aprpio1_0R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_0(&mut self) -> Aprpio0_0W { + Aprpio0_0W::new(self, 0) + } + #[doc = "Bit 1 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_1(&mut self) -> Aprpio0_1W { + Aprpio0_1W::new(self, 1) + } + #[doc = "Bit 2 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_2(&mut self) -> Aprpio0_2W { + Aprpio0_2W::new(self, 2) + } + #[doc = "Bit 3 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_3(&mut self) -> Aprpio0_3W { + Aprpio0_3W::new(self, 3) + } + #[doc = "Bit 4 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_4(&mut self) -> Aprpio0_4W { + Aprpio0_4W::new(self, 4) + } + #[doc = "Bit 5 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_5(&mut self) -> Aprpio0_5W { + Aprpio0_5W::new(self, 5) + } + #[doc = "Bit 6 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_6(&mut self) -> Aprpio0_6W { + Aprpio0_6W::new(self, 6) + } + #[doc = "Bit 7 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_7(&mut self) -> Aprpio0_7W { + Aprpio0_7W::new(self, 7) + } + #[doc = "Bit 8 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_8(&mut self) -> Aprpio0_8W { + Aprpio0_8W::new(self, 8) + } + #[doc = "Bit 9 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_9(&mut self) -> Aprpio0_9W { + Aprpio0_9W::new(self, 9) + } + #[doc = "Bit 10 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_10(&mut self) -> Aprpio0_10W { + Aprpio0_10W::new(self, 10) + } + #[doc = "Bit 11 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio0_11(&mut self) -> Aprpio0_11W { + Aprpio0_11W::new(self, 11) + } + #[doc = "Bit 12 - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"] + #[inline(always)] + #[must_use] + pub fn aprpio1_0(&mut self) -> Aprpio1_0W { + Aprpio1_0W::new(self, 12) + } +} +#[doc = "Start logic edge control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`startaprp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startaprp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Startaprp0Spec; +impl crate::RegisterSpec for Startaprp0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`startaprp0::R`](R) reader structure"] +impl crate::Readable for Startaprp0Spec {} +#[doc = "`write(|w| ..)` method takes [`startaprp0::W`](W) writer structure"] +impl crate::Writable for Startaprp0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STARTAPRP0 to value 0"] +impl crate::Resettable for Startaprp0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/starterp0.rs b/rust-embedded/lpc111x-pac/src/syscon/starterp0.rs new file mode 100644 index 0000000..1223f35 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/starterp0.rs @@ -0,0 +1,220 @@ +#[doc = "Register `STARTERP0` reader"] +pub type R = crate::R; +#[doc = "Register `STARTERP0` writer"] +pub type W = crate::W; +#[doc = "Field `ERPIO0_0` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_0R = crate::BitReader; +#[doc = "Field `ERPIO0_0` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_1` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_1R = crate::BitReader; +#[doc = "Field `ERPIO0_1` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_2` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_2R = crate::BitReader; +#[doc = "Field `ERPIO0_2` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_3` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_3R = crate::BitReader; +#[doc = "Field `ERPIO0_3` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_4` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_4R = crate::BitReader; +#[doc = "Field `ERPIO0_4` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_5` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_5R = crate::BitReader; +#[doc = "Field `ERPIO0_5` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_6` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_6R = crate::BitReader; +#[doc = "Field `ERPIO0_6` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_7` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_7R = crate::BitReader; +#[doc = "Field `ERPIO0_7` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_8` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_8R = crate::BitReader; +#[doc = "Field `ERPIO0_8` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_9` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_9R = crate::BitReader; +#[doc = "Field `ERPIO0_9` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_10` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_10R = crate::BitReader; +#[doc = "Field `ERPIO0_10` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO0_11` reader - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_11R = crate::BitReader; +#[doc = "Field `ERPIO0_11` writer - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] +pub type Erpio0_11W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERPIO1_0` reader - Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled"] +pub type Erpio1_0R = crate::BitReader; +#[doc = "Field `ERPIO1_0` writer - Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled"] +pub type Erpio1_0W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_0(&self) -> Erpio0_0R { + Erpio0_0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_1(&self) -> Erpio0_1R { + Erpio0_1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_2(&self) -> Erpio0_2R { + Erpio0_2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_3(&self) -> Erpio0_3R { + Erpio0_3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_4(&self) -> Erpio0_4R { + Erpio0_4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_5(&self) -> Erpio0_5R { + Erpio0_5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_6(&self) -> Erpio0_6R { + Erpio0_6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_7(&self) -> Erpio0_7R { + Erpio0_7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_8(&self) -> Erpio0_8R { + Erpio0_8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_9(&self) -> Erpio0_9R { + Erpio0_9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_10(&self) -> Erpio0_10R { + Erpio0_10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio0_11(&self) -> Erpio0_11R { + Erpio0_11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + pub fn erpio1_0(&self) -> Erpio1_0R { + Erpio1_0R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_0(&mut self) -> Erpio0_0W { + Erpio0_0W::new(self, 0) + } + #[doc = "Bit 1 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_1(&mut self) -> Erpio0_1W { + Erpio0_1W::new(self, 1) + } + #[doc = "Bit 2 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_2(&mut self) -> Erpio0_2W { + Erpio0_2W::new(self, 2) + } + #[doc = "Bit 3 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_3(&mut self) -> Erpio0_3W { + Erpio0_3W::new(self, 3) + } + #[doc = "Bit 4 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_4(&mut self) -> Erpio0_4W { + Erpio0_4W::new(self, 4) + } + #[doc = "Bit 5 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_5(&mut self) -> Erpio0_5W { + Erpio0_5W::new(self, 5) + } + #[doc = "Bit 6 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_6(&mut self) -> Erpio0_6W { + Erpio0_6W::new(self, 6) + } + #[doc = "Bit 7 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_7(&mut self) -> Erpio0_7W { + Erpio0_7W::new(self, 7) + } + #[doc = "Bit 8 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_8(&mut self) -> Erpio0_8W { + Erpio0_8W::new(self, 8) + } + #[doc = "Bit 9 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_9(&mut self) -> Erpio0_9W { + Erpio0_9W::new(self, 9) + } + #[doc = "Bit 10 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_10(&mut self) -> Erpio0_10W { + Erpio0_10W::new(self, 10) + } + #[doc = "Bit 11 - Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio0_11(&mut self) -> Erpio0_11W { + Erpio0_11W::new(self, 11) + } + #[doc = "Bit 12 - Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled"] + #[inline(always)] + #[must_use] + pub fn erpio1_0(&mut self) -> Erpio1_0W { + Erpio1_0W::new(self, 12) + } +} +#[doc = "Start logic signal enable register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`starterp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`starterp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Starterp0Spec; +impl crate::RegisterSpec for Starterp0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`starterp0::R`](R) reader structure"] +impl crate::Readable for Starterp0Spec {} +#[doc = "`write(|w| ..)` method takes [`starterp0::W`](W) writer structure"] +impl crate::Writable for Starterp0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STARTERP0 to value 0"] +impl crate::Resettable for Starterp0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/startrsrp0clr.rs b/rust-embedded/lpc111x-pac/src/syscon/startrsrp0clr.rs new file mode 100644 index 0000000..9fa0667 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/startrsrp0clr.rs @@ -0,0 +1,123 @@ +#[doc = "Register `STARTRSRP0CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RSRPIO0_0` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_1` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_2` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_3` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_4` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_4W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_5` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_5W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_6` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_6W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_7` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_7W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_8` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_9` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_9W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_10` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_10W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO0_11` writer - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio0_11W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSRPIO1_0` writer - Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] +pub type Rsrpio1_0W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_0(&mut self) -> Rsrpio0_0W { + Rsrpio0_0W::new(self, 0) + } + #[doc = "Bit 1 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_1(&mut self) -> Rsrpio0_1W { + Rsrpio0_1W::new(self, 1) + } + #[doc = "Bit 2 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_2(&mut self) -> Rsrpio0_2W { + Rsrpio0_2W::new(self, 2) + } + #[doc = "Bit 3 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_3(&mut self) -> Rsrpio0_3W { + Rsrpio0_3W::new(self, 3) + } + #[doc = "Bit 4 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_4(&mut self) -> Rsrpio0_4W { + Rsrpio0_4W::new(self, 4) + } + #[doc = "Bit 5 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_5(&mut self) -> Rsrpio0_5W { + Rsrpio0_5W::new(self, 5) + } + #[doc = "Bit 6 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_6(&mut self) -> Rsrpio0_6W { + Rsrpio0_6W::new(self, 6) + } + #[doc = "Bit 7 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_7(&mut self) -> Rsrpio0_7W { + Rsrpio0_7W::new(self, 7) + } + #[doc = "Bit 8 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_8(&mut self) -> Rsrpio0_8W { + Rsrpio0_8W::new(self, 8) + } + #[doc = "Bit 9 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_9(&mut self) -> Rsrpio0_9W { + Rsrpio0_9W::new(self, 9) + } + #[doc = "Bit 10 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_10(&mut self) -> Rsrpio0_10W { + Rsrpio0_10W::new(self, 10) + } + #[doc = "Bit 11 - Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio0_11(&mut self) -> Rsrpio0_11W { + Rsrpio0_11W::new(self, 11) + } + #[doc = "Bit 12 - Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal."] + #[inline(always)] + #[must_use] + pub fn rsrpio1_0(&mut self) -> Rsrpio1_0W { + Rsrpio1_0W::new(self, 12) + } +} +#[doc = "Start logic reset register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startrsrp0clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Startrsrp0clrSpec; +impl crate::RegisterSpec for Startrsrp0clrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`startrsrp0clr::W`](W) writer structure"] +impl crate::Writable for Startrsrp0clrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STARTRSRP0CLR to value 0"] +impl crate::Resettable for Startrsrp0clrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/startsrp0.rs b/rust-embedded/lpc111x-pac/src/syscon/startsrp0.rs new file mode 100644 index 0000000..4f6f2bc --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/startsrp0.rs @@ -0,0 +1,106 @@ +#[doc = "Register `STARTSRP0` reader"] +pub type R = crate::R; +#[doc = "Field `SRPIO0_0` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_0R = crate::BitReader; +#[doc = "Field `SRPIO0_1` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_1R = crate::BitReader; +#[doc = "Field `SRPIO0_2` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_2R = crate::BitReader; +#[doc = "Field `SRPIO0_3` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_3R = crate::BitReader; +#[doc = "Field `SRPIO0_4` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_4R = crate::BitReader; +#[doc = "Field `SRPIO0_5` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_5R = crate::BitReader; +#[doc = "Field `SRPIO0_6` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_6R = crate::BitReader; +#[doc = "Field `SRPIO0_7` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_7R = crate::BitReader; +#[doc = "Field `SRPIO0_8` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_8R = crate::BitReader; +#[doc = "Field `SRPIO0_9` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_9R = crate::BitReader; +#[doc = "Field `SRPIO0_10` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_10R = crate::BitReader; +#[doc = "Field `SRPIO0_11` reader - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio0_11R = crate::BitReader; +#[doc = "Field `SRPIO1_0` reader - Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending."] +pub type Srpio1_0R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_0(&self) -> Srpio0_0R { + Srpio0_0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_1(&self) -> Srpio0_1R { + Srpio0_1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_2(&self) -> Srpio0_2R { + Srpio0_2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_3(&self) -> Srpio0_3R { + Srpio0_3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_4(&self) -> Srpio0_4R { + Srpio0_4R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_5(&self) -> Srpio0_5R { + Srpio0_5R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_6(&self) -> Srpio0_6R { + Srpio0_6R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_7(&self) -> Srpio0_7R { + Srpio0_7R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_8(&self) -> Srpio0_8R { + Srpio0_8R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_9(&self) -> Srpio0_9R { + Srpio0_9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_10(&self) -> Srpio0_10R { + Srpio0_10R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio0_11(&self) -> Srpio0_11R { + Srpio0_11R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending."] + #[inline(always)] + pub fn srpio1_0(&self) -> Srpio1_0R { + Srpio1_0R::new(((self.bits >> 12) & 1) != 0) + } +} +#[doc = "Start logic status register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`startsrp0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Startsrp0Spec; +impl crate::RegisterSpec for Startsrp0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`startsrp0::R`](R) reader structure"] +impl crate::Readable for Startsrp0Spec {} +#[doc = "`reset()` method sets STARTSRP0 to value 0"] +impl crate::Resettable for Startsrp0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/sysahbclkctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/sysahbclkctrl.rs new file mode 100644 index 0000000..797bdcd --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/sysahbclkctrl.rs @@ -0,0 +1,1165 @@ +#[doc = "Register `SYSAHBCLKCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYSAHBCLKCTRL` writer"] +pub type W = crate::W; +#[doc = "Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sys { + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sys) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYS` reader - Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only."] +pub type SysR = crate::BitReader; +impl SysR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sys { + match self.bits { + true => Sys::Enable, + _ => unreachable!(), + } + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Sys::Enable + } +} +#[doc = "Field `SYS` writer - Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only."] +pub type SysW<'a, REG> = crate::BitWriter<'a, REG, Sys>; +impl<'a, REG> SysW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Sys::Enable) + } +} +#[doc = "Enables clock for ROM.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rom { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rom) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ROM` reader - Enables clock for ROM."] +pub type RomR = crate::BitReader; +impl RomR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rom { + match self.bits { + false => Rom::Disable, + true => Rom::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Rom::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Rom::Enable + } +} +#[doc = "Field `ROM` writer - Enables clock for ROM."] +pub type RomW<'a, REG> = crate::BitWriter<'a, REG, Rom>; +impl<'a, REG> RomW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Rom::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Rom::Enable) + } +} +#[doc = "Enables clock for RAM.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ram { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ram) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RAM` reader - Enables clock for RAM."] +pub type RamR = crate::BitReader; +impl RamR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ram { + match self.bits { + false => Ram::Disable, + true => Ram::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ram::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ram::Enable + } +} +#[doc = "Field `RAM` writer - Enables clock for RAM."] +pub type RamW<'a, REG> = crate::BitWriter<'a, REG, Ram>; +impl<'a, REG> RamW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ram::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ram::Enable) + } +} +#[doc = "Enables clock for flash register interface.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flashreg { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flashreg) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHREG` reader - Enables clock for flash register interface."] +pub type FlashregR = crate::BitReader; +impl FlashregR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flashreg { + match self.bits { + false => Flashreg::Disabled, + true => Flashreg::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flashreg::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flashreg::Enabled + } +} +#[doc = "Field `FLASHREG` writer - Enables clock for flash register interface."] +pub type FlashregW<'a, REG> = crate::BitWriter<'a, REG, Flashreg>; +impl<'a, REG> FlashregW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flashreg::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flashreg::Enabled) + } +} +#[doc = "Enables clock for flash array access.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Flasharray { + #[doc = "0: Disabled"] + Disabled = 0, + #[doc = "1: Enabled"] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Flasharray) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FLASHARRAY` reader - Enables clock for flash array access."] +pub type FlasharrayR = crate::BitReader; +impl FlasharrayR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Flasharray { + match self.bits { + false => Flasharray::Disabled, + true => Flasharray::Enabled, + } + } + #[doc = "Disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Flasharray::Disabled + } + #[doc = "Enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Flasharray::Enabled + } +} +#[doc = "Field `FLASHARRAY` writer - Enables clock for flash array access."] +pub type FlasharrayW<'a, REG> = crate::BitWriter<'a, REG, Flasharray>; +impl<'a, REG> FlasharrayW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Flasharray::Disabled) + } + #[doc = "Enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Flasharray::Enabled) + } +} +#[doc = "Enables clock for I2C.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum I2c { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: I2c) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `I2C` reader - Enables clock for I2C."] +pub type I2cR = crate::BitReader; +impl I2cR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> I2c { + match self.bits { + false => I2c::Disable, + true => I2c::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == I2c::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == I2c::Enable + } +} +#[doc = "Field `I2C` writer - Enables clock for I2C."] +pub type I2cW<'a, REG> = crate::BitWriter<'a, REG, I2c>; +impl<'a, REG> I2cW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(I2c::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(I2c::Enable) + } +} +#[doc = "Enables clock for GPIO.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Gpio { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Gpio) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GPIO` reader - Enables clock for GPIO."] +pub type GpioR = crate::BitReader; +impl GpioR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Gpio { + match self.bits { + false => Gpio::Disable, + true => Gpio::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Gpio::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Gpio::Enable + } +} +#[doc = "Field `GPIO` writer - Enables clock for GPIO."] +pub type GpioW<'a, REG> = crate::BitWriter<'a, REG, Gpio>; +impl<'a, REG> GpioW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Gpio::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Gpio::Enable) + } +} +#[doc = "Enables clock for 16-bit counter/timer 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ct16b0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ct16b0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CT16B0` reader - Enables clock for 16-bit counter/timer 0."] +pub type Ct16b0R = crate::BitReader; +impl Ct16b0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ct16b0 { + match self.bits { + false => Ct16b0::Disable, + true => Ct16b0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ct16b0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ct16b0::Enable + } +} +#[doc = "Field `CT16B0` writer - Enables clock for 16-bit counter/timer 0."] +pub type Ct16b0W<'a, REG> = crate::BitWriter<'a, REG, Ct16b0>; +impl<'a, REG> Ct16b0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ct16b0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ct16b0::Enable) + } +} +#[doc = "Enables clock for 16-bit counter/timer 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ct16b1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ct16b1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CT16B1` reader - Enables clock for 16-bit counter/timer 1."] +pub type Ct16b1R = crate::BitReader; +impl Ct16b1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ct16b1 { + match self.bits { + false => Ct16b1::Disable, + true => Ct16b1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ct16b1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ct16b1::Enable + } +} +#[doc = "Field `CT16B1` writer - Enables clock for 16-bit counter/timer 1."] +pub type Ct16b1W<'a, REG> = crate::BitWriter<'a, REG, Ct16b1>; +impl<'a, REG> Ct16b1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ct16b1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ct16b1::Enable) + } +} +#[doc = "Enables clock for 32-bit counter/timer 0.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ct32b0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ct32b0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CT32B0` reader - Enables clock for 32-bit counter/timer 0."] +pub type Ct32b0R = crate::BitReader; +impl Ct32b0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ct32b0 { + match self.bits { + false => Ct32b0::Disable, + true => Ct32b0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ct32b0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ct32b0::Enable + } +} +#[doc = "Field `CT32B0` writer - Enables clock for 32-bit counter/timer 0."] +pub type Ct32b0W<'a, REG> = crate::BitWriter<'a, REG, Ct32b0>; +impl<'a, REG> Ct32b0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ct32b0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ct32b0::Enable) + } +} +#[doc = "Enables clock for 32-bit counter/timer 1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ct32b1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ct32b1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CT32B1` reader - Enables clock for 32-bit counter/timer 1."] +pub type Ct32b1R = crate::BitReader; +impl Ct32b1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ct32b1 { + match self.bits { + false => Ct32b1::Disable, + true => Ct32b1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ct32b1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ct32b1::Enable + } +} +#[doc = "Field `CT32B1` writer - Enables clock for 32-bit counter/timer 1."] +pub type Ct32b1W<'a, REG> = crate::BitWriter<'a, REG, Ct32b1>; +impl<'a, REG> Ct32b1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ct32b1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ct32b1::Enable) + } +} +#[doc = "Enables clock for SPI0.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ssp0 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ssp0) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSP0` reader - Enables clock for SPI0."] +pub type Ssp0R = crate::BitReader; +impl Ssp0R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ssp0 { + match self.bits { + false => Ssp0::Disable, + true => Ssp0::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ssp0::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ssp0::Enable + } +} +#[doc = "Field `SSP0` writer - Enables clock for SPI0."] +pub type Ssp0W<'a, REG> = crate::BitWriter<'a, REG, Ssp0>; +impl<'a, REG> Ssp0W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ssp0::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ssp0::Enable) + } +} +#[doc = "Enables clock for UART. See Section 3.1 for part specific details.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Uart { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Uart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `UART` reader - Enables clock for UART. See Section 3.1 for part specific details."] +pub type UartR = crate::BitReader; +impl UartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Uart { + match self.bits { + false => Uart::Disable, + true => Uart::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Uart::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Uart::Enable + } +} +#[doc = "Field `UART` writer - Enables clock for UART. See Section 3.1 for part specific details."] +pub type UartW<'a, REG> = crate::BitWriter<'a, REG, Uart>; +impl<'a, REG> UartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Uart::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Uart::Enable) + } +} +#[doc = "Enables clock for ADC.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Adc { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Adc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ADC` reader - Enables clock for ADC."] +pub type AdcR = crate::BitReader; +impl AdcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Adc { + match self.bits { + false => Adc::Disable, + true => Adc::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Adc::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Adc::Enable + } +} +#[doc = "Field `ADC` writer - Enables clock for ADC."] +pub type AdcW<'a, REG> = crate::BitWriter<'a, REG, Adc>; +impl<'a, REG> AdcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Adc::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Adc::Enable) + } +} +#[doc = "Enables clock for WDT.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdt { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDT` reader - Enables clock for WDT."] +pub type WdtR = crate::BitReader; +impl WdtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdt { + match self.bits { + false => Wdt::Disable, + true => Wdt::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Wdt::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Wdt::Enable + } +} +#[doc = "Field `WDT` writer - Enables clock for WDT."] +pub type WdtW<'a, REG> = crate::BitWriter<'a, REG, Wdt>; +impl<'a, REG> WdtW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Wdt::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Wdt::Enable) + } +} +#[doc = "Enables clock for I/O configuration block.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Iocon { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Iocon) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IOCON` reader - Enables clock for I/O configuration block."] +pub type IoconR = crate::BitReader; +impl IoconR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Iocon { + match self.bits { + false => Iocon::Disable, + true => Iocon::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Iocon::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Iocon::Enable + } +} +#[doc = "Field `IOCON` writer - Enables clock for I/O configuration block."] +pub type IoconW<'a, REG> = crate::BitWriter<'a, REG, Iocon>; +impl<'a, REG> IoconW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Iocon::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Iocon::Enable) + } +} +#[doc = "Enables clock for C_CAN. See Section 3.1 for part specific details.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Can { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Can) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CAN` reader - Enables clock for C_CAN. See Section 3.1 for part specific details."] +pub type CanR = crate::BitReader; +impl CanR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Can { + match self.bits { + false => Can::Disable, + true => Can::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Can::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Can::Enable + } +} +#[doc = "Field `CAN` writer - Enables clock for C_CAN. See Section 3.1 for part specific details."] +pub type CanW<'a, REG> = crate::BitWriter<'a, REG, Can>; +impl<'a, REG> CanW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Can::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Can::Enable) + } +} +#[doc = "Enables clock for SPI1.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ssp1 { + #[doc = "0: Disable"] + Disable = 0, + #[doc = "1: Enable"] + Enable = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ssp1) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SSP1` reader - Enables clock for SPI1."] +pub type Ssp1R = crate::BitReader; +impl Ssp1R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ssp1 { + match self.bits { + false => Ssp1::Disable, + true => Ssp1::Enable, + } + } + #[doc = "Disable"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == Ssp1::Disable + } + #[doc = "Enable"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == Ssp1::Enable + } +} +#[doc = "Field `SSP1` writer - Enables clock for SPI1."] +pub type Ssp1W<'a, REG> = crate::BitWriter<'a, REG, Ssp1>; +impl<'a, REG> Ssp1W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(Ssp1::Disable) + } + #[doc = "Enable"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(Ssp1::Enable) + } +} +impl R { + #[doc = "Bit 0 - Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only."] + #[inline(always)] + pub fn sys(&self) -> SysR { + SysR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables clock for ROM."] + #[inline(always)] + pub fn rom(&self) -> RomR { + RomR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables clock for RAM."] + #[inline(always)] + pub fn ram(&self) -> RamR { + RamR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables clock for flash register interface."] + #[inline(always)] + pub fn flashreg(&self) -> FlashregR { + FlashregR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables clock for flash array access."] + #[inline(always)] + pub fn flasharray(&self) -> FlasharrayR { + FlasharrayR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables clock for I2C."] + #[inline(always)] + pub fn i2c(&self) -> I2cR { + I2cR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables clock for GPIO."] + #[inline(always)] + pub fn gpio(&self) -> GpioR { + GpioR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enables clock for 16-bit counter/timer 0."] + #[inline(always)] + pub fn ct16b0(&self) -> Ct16b0R { + Ct16b0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enables clock for 16-bit counter/timer 1."] + #[inline(always)] + pub fn ct16b1(&self) -> Ct16b1R { + Ct16b1R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enables clock for 32-bit counter/timer 0."] + #[inline(always)] + pub fn ct32b0(&self) -> Ct32b0R { + Ct32b0R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enables clock for 32-bit counter/timer 1."] + #[inline(always)] + pub fn ct32b1(&self) -> Ct32b1R { + Ct32b1R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enables clock for SPI0."] + #[inline(always)] + pub fn ssp0(&self) -> Ssp0R { + Ssp0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enables clock for UART. See Section 3.1 for part specific details."] + #[inline(always)] + pub fn uart(&self) -> UartR { + UartR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enables clock for ADC."] + #[inline(always)] + pub fn adc(&self) -> AdcR { + AdcR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Enables clock for WDT."] + #[inline(always)] + pub fn wdt(&self) -> WdtR { + WdtR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enables clock for I/O configuration block."] + #[inline(always)] + pub fn iocon(&self) -> IoconR { + IoconR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enables clock for C_CAN. See Section 3.1 for part specific details."] + #[inline(always)] + pub fn can(&self) -> CanR { + CanR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enables clock for SPI1."] + #[inline(always)] + pub fn ssp1(&self) -> Ssp1R { + Ssp1R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only."] + #[inline(always)] + #[must_use] + pub fn sys(&mut self) -> SysW { + SysW::new(self, 0) + } + #[doc = "Bit 1 - Enables clock for ROM."] + #[inline(always)] + #[must_use] + pub fn rom(&mut self) -> RomW { + RomW::new(self, 1) + } + #[doc = "Bit 2 - Enables clock for RAM."] + #[inline(always)] + #[must_use] + pub fn ram(&mut self) -> RamW { + RamW::new(self, 2) + } + #[doc = "Bit 3 - Enables clock for flash register interface."] + #[inline(always)] + #[must_use] + pub fn flashreg(&mut self) -> FlashregW { + FlashregW::new(self, 3) + } + #[doc = "Bit 4 - Enables clock for flash array access."] + #[inline(always)] + #[must_use] + pub fn flasharray(&mut self) -> FlasharrayW { + FlasharrayW::new(self, 4) + } + #[doc = "Bit 5 - Enables clock for I2C."] + #[inline(always)] + #[must_use] + pub fn i2c(&mut self) -> I2cW { + I2cW::new(self, 5) + } + #[doc = "Bit 6 - Enables clock for GPIO."] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GpioW { + GpioW::new(self, 6) + } + #[doc = "Bit 7 - Enables clock for 16-bit counter/timer 0."] + #[inline(always)] + #[must_use] + pub fn ct16b0(&mut self) -> Ct16b0W { + Ct16b0W::new(self, 7) + } + #[doc = "Bit 8 - Enables clock for 16-bit counter/timer 1."] + #[inline(always)] + #[must_use] + pub fn ct16b1(&mut self) -> Ct16b1W { + Ct16b1W::new(self, 8) + } + #[doc = "Bit 9 - Enables clock for 32-bit counter/timer 0."] + #[inline(always)] + #[must_use] + pub fn ct32b0(&mut self) -> Ct32b0W { + Ct32b0W::new(self, 9) + } + #[doc = "Bit 10 - Enables clock for 32-bit counter/timer 1."] + #[inline(always)] + #[must_use] + pub fn ct32b1(&mut self) -> Ct32b1W { + Ct32b1W::new(self, 10) + } + #[doc = "Bit 11 - Enables clock for SPI0."] + #[inline(always)] + #[must_use] + pub fn ssp0(&mut self) -> Ssp0W { + Ssp0W::new(self, 11) + } + #[doc = "Bit 12 - Enables clock for UART. See Section 3.1 for part specific details."] + #[inline(always)] + #[must_use] + pub fn uart(&mut self) -> UartW { + UartW::new(self, 12) + } + #[doc = "Bit 13 - Enables clock for ADC."] + #[inline(always)] + #[must_use] + pub fn adc(&mut self) -> AdcW { + AdcW::new(self, 13) + } + #[doc = "Bit 15 - Enables clock for WDT."] + #[inline(always)] + #[must_use] + pub fn wdt(&mut self) -> WdtW { + WdtW::new(self, 15) + } + #[doc = "Bit 16 - Enables clock for I/O configuration block."] + #[inline(always)] + #[must_use] + pub fn iocon(&mut self) -> IoconW { + IoconW::new(self, 16) + } + #[doc = "Bit 17 - Enables clock for C_CAN. See Section 3.1 for part specific details."] + #[inline(always)] + #[must_use] + pub fn can(&mut self) -> CanW { + CanW::new(self, 17) + } + #[doc = "Bit 18 - Enables clock for SPI1."] + #[inline(always)] + #[must_use] + pub fn ssp1(&mut self) -> Ssp1W { + Ssp1W::new(self, 18) + } +} +#[doc = "System AHB clock control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysahbclkctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysahbclkctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysahbclkctrlSpec; +impl crate::RegisterSpec for SysahbclkctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysahbclkctrl::R`](R) reader structure"] +impl crate::Readable for SysahbclkctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sysahbclkctrl::W`](W) writer structure"] +impl crate::Writable for SysahbclkctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSAHBCLKCTRL to value 0x085f"] +impl crate::Resettable for SysahbclkctrlSpec { + const RESET_VALUE: u32 = 0x085f; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/sysahbclkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/sysahbclkdiv.rs new file mode 100644 index 0000000..1581d77 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/sysahbclkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SYSAHBCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SYSAHBCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "System AHB clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysahbclkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysahbclkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysahbclkdivSpec; +impl crate::RegisterSpec for SysahbclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysahbclkdiv::R`](R) reader structure"] +impl crate::Readable for SysahbclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`sysahbclkdiv::W`](W) writer structure"] +impl crate::Writable for SysahbclkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSAHBCLKDIV to value 0x01"] +impl crate::Resettable for SysahbclkdivSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/sysmemremap.rs b/rust-embedded/lpc111x-pac/src/syscon/sysmemremap.rs new file mode 100644 index 0000000..61fd095 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/sysmemremap.rs @@ -0,0 +1,108 @@ +#[doc = "Register `SYSMEMREMAP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSMEMREMAP` writer"] +pub type W = crate::W; +#[doc = "System memory remap\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Map { + #[doc = "0: Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM."] + BootLoaderModeIn = 0, + #[doc = "1: User RAM Mode. Interrupt vectors are re-mapped to Static RAM."] + UserRamModeInter = 1, + #[doc = "2: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash."] + UserFlashModeInt = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Map) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Map { + type Ux = u8; +} +#[doc = "Field `MAP` reader - System memory remap"] +pub type MapR = crate::FieldReader; +impl MapR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Map::BootLoaderModeIn), + 1 => Some(Map::UserRamModeInter), + 2 => Some(Map::UserFlashModeInt), + _ => None, + } + } + #[doc = "Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM."] + #[inline(always)] + pub fn is_boot_loader_mode_in(&self) -> bool { + *self == Map::BootLoaderModeIn + } + #[doc = "User RAM Mode. Interrupt vectors are re-mapped to Static RAM."] + #[inline(always)] + pub fn is_user_ram_mode_inter(&self) -> bool { + *self == Map::UserRamModeInter + } + #[doc = "User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash."] + #[inline(always)] + pub fn is_user_flash_mode_int(&self) -> bool { + *self == Map::UserFlashModeInt + } +} +#[doc = "Field `MAP` writer - System memory remap"] +pub type MapW<'a, REG> = crate::FieldWriter<'a, REG, 2, Map>; +impl<'a, REG> MapW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM."] + #[inline(always)] + pub fn boot_loader_mode_in(self) -> &'a mut crate::W { + self.variant(Map::BootLoaderModeIn) + } + #[doc = "User RAM Mode. Interrupt vectors are re-mapped to Static RAM."] + #[inline(always)] + pub fn user_ram_mode_inter(self) -> &'a mut crate::W { + self.variant(Map::UserRamModeInter) + } + #[doc = "User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash."] + #[inline(always)] + pub fn user_flash_mode_int(self) -> &'a mut crate::W { + self.variant(Map::UserFlashModeInt) + } +} +impl R { + #[doc = "Bits 0:1 - System memory remap"] + #[inline(always)] + pub fn map(&self) -> MapR { + MapR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - System memory remap"] + #[inline(always)] + #[must_use] + pub fn map(&mut self) -> MapW { + MapW::new(self, 0) + } +} +#[doc = "System memory remap\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysmemremap::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysmemremap::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysmemremapSpec; +impl crate::RegisterSpec for SysmemremapSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysmemremap::R`](R) reader structure"] +impl crate::Readable for SysmemremapSpec {} +#[doc = "`write(|w| ..)` method takes [`sysmemremap::W`](W) writer structure"] +impl crate::Writable for SysmemremapSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSMEMREMAP to value 0x02"] +impl crate::Resettable for SysmemremapSpec { + const RESET_VALUE: u32 = 0x02; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/sysoscctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/sysoscctrl.rs new file mode 100644 index 0000000..9bdc8ce --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/sysoscctrl.rs @@ -0,0 +1,153 @@ +#[doc = "Register `SYSOSCCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYSOSCCTRL` writer"] +pub type W = crate::W; +#[doc = "Bypass system oscillator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bypass { + #[doc = "0: Oscillator is not bypassed."] + Nobypass = 0, + #[doc = "1: Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins."] + BypassEnabledPll_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bypass) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BYPASS` reader - Bypass system oscillator"] +pub type BypassR = crate::BitReader; +impl BypassR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bypass { + match self.bits { + false => Bypass::Nobypass, + true => Bypass::BypassEnabledPll_, + } + } + #[doc = "Oscillator is not bypassed."] + #[inline(always)] + pub fn is_nobypass(&self) -> bool { + *self == Bypass::Nobypass + } + #[doc = "Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins."] + #[inline(always)] + pub fn is_bypass_enabled_pll_(&self) -> bool { + *self == Bypass::BypassEnabledPll_ + } +} +#[doc = "Field `BYPASS` writer - Bypass system oscillator"] +pub type BypassW<'a, REG> = crate::BitWriter<'a, REG, Bypass>; +impl<'a, REG> BypassW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Oscillator is not bypassed."] + #[inline(always)] + pub fn nobypass(self) -> &'a mut crate::W { + self.variant(Bypass::Nobypass) + } + #[doc = "Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins."] + #[inline(always)] + pub fn bypass_enabled_pll_(self) -> &'a mut crate::W { + self.variant(Bypass::BypassEnabledPll_) + } +} +#[doc = "Determines frequency range for Low-power oscillator.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Freqrange { + #[doc = "0: 1 - 20 MHz frequency range."] + Low = 0, + #[doc = "1: 15 - 25 MHz frequency range"] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Freqrange) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FREQRANGE` reader - Determines frequency range for Low-power oscillator."] +pub type FreqrangeR = crate::BitReader; +impl FreqrangeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Freqrange { + match self.bits { + false => Freqrange::Low, + true => Freqrange::High, + } + } + #[doc = "1 - 20 MHz frequency range."] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Freqrange::Low + } + #[doc = "15 - 25 MHz frequency range"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Freqrange::High + } +} +#[doc = "Field `FREQRANGE` writer - Determines frequency range for Low-power oscillator."] +pub type FreqrangeW<'a, REG> = crate::BitWriter<'a, REG, Freqrange>; +impl<'a, REG> FreqrangeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1 - 20 MHz frequency range."] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Freqrange::Low) + } + #[doc = "15 - 25 MHz frequency range"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Freqrange::High) + } +} +impl R { + #[doc = "Bit 0 - Bypass system oscillator"] + #[inline(always)] + pub fn bypass(&self) -> BypassR { + BypassR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines frequency range for Low-power oscillator."] + #[inline(always)] + pub fn freqrange(&self) -> FreqrangeR { + FreqrangeR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bypass system oscillator"] + #[inline(always)] + #[must_use] + pub fn bypass(&mut self) -> BypassW { + BypassW::new(self, 0) + } + #[doc = "Bit 1 - Determines frequency range for Low-power oscillator."] + #[inline(always)] + #[must_use] + pub fn freqrange(&mut self) -> FreqrangeW { + FreqrangeW::new(self, 1) + } +} +#[doc = "System oscillator control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysoscctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysoscctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysoscctrlSpec; +impl crate::RegisterSpec for SysoscctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysoscctrl::R`](R) reader structure"] +impl crate::Readable for SysoscctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`sysoscctrl::W`](W) writer structure"] +impl crate::Writable for SysoscctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSOSCCTRL to value 0"] +impl crate::Resettable for SysoscctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/syspllclksel.rs b/rust-embedded/lpc111x-pac/src/syscon/syspllclksel.rs new file mode 100644 index 0000000..23960c6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/syspllclksel.rs @@ -0,0 +1,95 @@ +#[doc = "Register `SYSPLLCLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `SYSPLLCLKSEL` writer"] +pub type W = crate::W; +#[doc = "System PLL clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sel { + #[doc = "0: IRC oscillator"] + IrcOscillator = 0, + #[doc = "1: System oscillator"] + SystemOscillator = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sel { + type Ux = u8; +} +#[doc = "Field `SEL` reader - System PLL clock source"] +pub type SelR = crate::FieldReader; +impl SelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sel { + match self.bits { + 0 => Sel::IrcOscillator, + 1 => Sel::SystemOscillator, + _ => unreachable!(), + } + } + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn is_irc_oscillator(&self) -> bool { + *self == Sel::IrcOscillator + } + #[doc = "System oscillator"] + #[inline(always)] + pub fn is_system_oscillator(&self) -> bool { + *self == Sel::SystemOscillator + } +} +#[doc = "Field `SEL` writer - System PLL clock source"] +pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sel>; +impl<'a, REG> SelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn irc_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::IrcOscillator) + } + #[doc = "System oscillator"] + #[inline(always)] + pub fn system_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::SystemOscillator) + } +} +impl R { + #[doc = "Bits 0:1 - System PLL clock source"] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - System PLL clock source"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 0) + } +} +#[doc = "System PLL clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllclksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllclksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyspllclkselSpec; +impl crate::RegisterSpec for SyspllclkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`syspllclksel::R`](R) reader structure"] +impl crate::Readable for SyspllclkselSpec {} +#[doc = "`write(|w| ..)` method takes [`syspllclksel::W`](W) writer structure"] +impl crate::Writable for SyspllclkselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSPLLCLKSEL to value 0"] +impl crate::Resettable for SyspllclkselSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/syspllclkuen.rs b/rust-embedded/lpc111x-pac/src/syscon/syspllclkuen.rs new file mode 100644 index 0000000..f3c0bef --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/syspllclkuen.rs @@ -0,0 +1,89 @@ +#[doc = "Register `SYSPLLCLKUEN` reader"] +pub type R = crate::R; +#[doc = "Register `SYSPLLCLKUEN` writer"] +pub type W = crate::W; +#[doc = "Enable system PLL clock source update\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ena { + #[doc = "0: No change"] + NoChange = 0, + #[doc = "1: Update clock source"] + UpdateClockSource = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA` reader - Enable system PLL clock source update"] +pub type EnaR = crate::BitReader; +impl EnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ena { + match self.bits { + false => Ena::NoChange, + true => Ena::UpdateClockSource, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_no_change(&self) -> bool { + *self == Ena::NoChange + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn is_update_clock_source(&self) -> bool { + *self == Ena::UpdateClockSource + } +} +#[doc = "Field `ENA` writer - Enable system PLL clock source update"] +pub type EnaW<'a, REG> = crate::BitWriter<'a, REG, Ena>; +impl<'a, REG> EnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn no_change(self) -> &'a mut crate::W { + self.variant(Ena::NoChange) + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn update_clock_source(self) -> &'a mut crate::W { + self.variant(Ena::UpdateClockSource) + } +} +impl R { + #[doc = "Bit 0 - Enable system PLL clock source update"] + #[inline(always)] + pub fn ena(&self) -> EnaR { + EnaR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable system PLL clock source update"] + #[inline(always)] + #[must_use] + pub fn ena(&mut self) -> EnaW { + EnaW::new(self, 0) + } +} +#[doc = "System PLL clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllclkuen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllclkuen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyspllclkuenSpec; +impl crate::RegisterSpec for SyspllclkuenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`syspllclkuen::R`](R) reader structure"] +impl crate::Readable for SyspllclkuenSpec {} +#[doc = "`write(|w| ..)` method takes [`syspllclkuen::W`](W) writer structure"] +impl crate::Writable for SyspllclkuenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSPLLCLKUEN to value 0"] +impl crate::Resettable for SyspllclkuenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/syspllctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/syspllctrl.rs new file mode 100644 index 0000000..28d9198 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/syspllctrl.rs @@ -0,0 +1,136 @@ +#[doc = "Register `SYSPLLCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SYSPLLCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `MSEL` reader - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."] +pub type MselR = crate::FieldReader; +#[doc = "Field `MSEL` writer - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."] +pub type MselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Post divider ratio P. The division ratio is 2 x P.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Psel { + #[doc = "0: P = 1"] + PEq1 = 0, + #[doc = "1: P = 2"] + PEq2 = 1, + #[doc = "2: P = 4"] + PEq4 = 2, + #[doc = "3: P = 8"] + PEq8 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Psel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Psel { + type Ux = u8; +} +#[doc = "Field `PSEL` reader - Post divider ratio P. The division ratio is 2 x P."] +pub type PselR = crate::FieldReader; +impl PselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Psel { + match self.bits { + 0 => Psel::PEq1, + 1 => Psel::PEq2, + 2 => Psel::PEq4, + 3 => Psel::PEq8, + _ => unreachable!(), + } + } + #[doc = "P = 1"] + #[inline(always)] + pub fn is_p_eq_1(&self) -> bool { + *self == Psel::PEq1 + } + #[doc = "P = 2"] + #[inline(always)] + pub fn is_p_eq_2(&self) -> bool { + *self == Psel::PEq2 + } + #[doc = "P = 4"] + #[inline(always)] + pub fn is_p_eq_4(&self) -> bool { + *self == Psel::PEq4 + } + #[doc = "P = 8"] + #[inline(always)] + pub fn is_p_eq_8(&self) -> bool { + *self == Psel::PEq8 + } +} +#[doc = "Field `PSEL` writer - Post divider ratio P. The division ratio is 2 x P."] +pub type PselW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Psel>; +impl<'a, REG> PselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "P = 1"] + #[inline(always)] + pub fn p_eq_1(self) -> &'a mut crate::W { + self.variant(Psel::PEq1) + } + #[doc = "P = 2"] + #[inline(always)] + pub fn p_eq_2(self) -> &'a mut crate::W { + self.variant(Psel::PEq2) + } + #[doc = "P = 4"] + #[inline(always)] + pub fn p_eq_4(self) -> &'a mut crate::W { + self.variant(Psel::PEq4) + } + #[doc = "P = 8"] + #[inline(always)] + pub fn p_eq_8(self) -> &'a mut crate::W { + self.variant(Psel::PEq8) + } +} +impl R { + #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."] + #[inline(always)] + pub fn msel(&self) -> MselR { + MselR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."] + #[inline(always)] + pub fn psel(&self) -> PselR { + PselR::new(((self.bits >> 5) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32."] + #[inline(always)] + #[must_use] + pub fn msel(&mut self) -> MselW { + MselW::new(self, 0) + } + #[doc = "Bits 5:6 - Post divider ratio P. The division ratio is 2 x P."] + #[inline(always)] + #[must_use] + pub fn psel(&mut self) -> PselW { + PselW::new(self, 5) + } +} +#[doc = "System PLL control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`syspllctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyspllctrlSpec; +impl crate::RegisterSpec for SyspllctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`syspllctrl::R`](R) reader structure"] +impl crate::Readable for SyspllctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`syspllctrl::W`](W) writer structure"] +impl crate::Writable for SyspllctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSPLLCTRL to value 0"] +impl crate::Resettable for SyspllctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/syspllstat.rs b/rust-embedded/lpc111x-pac/src/syscon/syspllstat.rs new file mode 100644 index 0000000..228af31 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/syspllstat.rs @@ -0,0 +1,56 @@ +#[doc = "Register `SYSPLLSTAT` reader"] +pub type R = crate::R; +#[doc = "PLL lock status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Lock { + #[doc = "0: PLL not locked"] + PllNotLocked = 0, + #[doc = "1: PLL locked"] + PllLocked = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Lock) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `LOCK` reader - PLL lock status"] +pub type LockR = crate::BitReader; +impl LockR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Lock { + match self.bits { + false => Lock::PllNotLocked, + true => Lock::PllLocked, + } + } + #[doc = "PLL not locked"] + #[inline(always)] + pub fn is_pll_not_locked(&self) -> bool { + *self == Lock::PllNotLocked + } + #[doc = "PLL locked"] + #[inline(always)] + pub fn is_pll_locked(&self) -> bool { + *self == Lock::PllLocked + } +} +impl R { + #[doc = "Bit 0 - PLL lock status"] + #[inline(always)] + pub fn lock(&self) -> LockR { + LockR::new((self.bits & 1) != 0) + } +} +#[doc = "System PLL status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syspllstat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyspllstatSpec; +impl crate::RegisterSpec for SyspllstatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`syspllstat::R`](R) reader structure"] +impl crate::Readable for SyspllstatSpec {} +#[doc = "`reset()` method sets SYSPLLSTAT to value 0"] +impl crate::Resettable for SyspllstatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/sysrststat.rs b/rust-embedded/lpc111x-pac/src/syscon/sysrststat.rs new file mode 100644 index 0000000..bde878a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/sysrststat.rs @@ -0,0 +1,220 @@ +#[doc = "Register `SYSRSTSTAT` reader"] +pub type R = crate::R; +#[doc = "POR reset status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Por { + #[doc = "0: No POR detected."] + NoPorDetected_ = 0, + #[doc = "1: POR detected. Writing a one clears this reset."] + PorDetectedWritin = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Por) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `POR` reader - POR reset status"] +pub type PorR = crate::BitReader; +impl PorR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Por { + match self.bits { + false => Por::NoPorDetected_, + true => Por::PorDetectedWritin, + } + } + #[doc = "No POR detected."] + #[inline(always)] + pub fn is_no_por_detected_(&self) -> bool { + *self == Por::NoPorDetected_ + } + #[doc = "POR detected. Writing a one clears this reset."] + #[inline(always)] + pub fn is_por_detected_writin(&self) -> bool { + *self == Por::PorDetectedWritin + } +} +#[doc = "Status of the external RESET pin.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Extrst { + #[doc = "0: No RESET event detected."] + NoResetEventDetec = 0, + #[doc = "1: RESET detected. Writing a one clears this reset."] + ResetDetectedWrit = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Extrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `EXTRST` reader - Status of the external RESET pin."] +pub type ExtrstR = crate::BitReader; +impl ExtrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Extrst { + match self.bits { + false => Extrst::NoResetEventDetec, + true => Extrst::ResetDetectedWrit, + } + } + #[doc = "No RESET event detected."] + #[inline(always)] + pub fn is_no_reset_event_detec(&self) -> bool { + *self == Extrst::NoResetEventDetec + } + #[doc = "RESET detected. Writing a one clears this reset."] + #[inline(always)] + pub fn is_reset_detected_writ(&self) -> bool { + *self == Extrst::ResetDetectedWrit + } +} +#[doc = "Status of the Watchdog reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdt { + #[doc = "0: No WDT reset detected."] + NoWdtResetDetecte = 0, + #[doc = "1: WDT reset detected. Writing a one clears this reset."] + WdtResetDetected_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDT` reader - Status of the Watchdog reset"] +pub type WdtR = crate::BitReader; +impl WdtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdt { + match self.bits { + false => Wdt::NoWdtResetDetecte, + true => Wdt::WdtResetDetected_, + } + } + #[doc = "No WDT reset detected."] + #[inline(always)] + pub fn is_no_wdt_reset_detecte(&self) -> bool { + *self == Wdt::NoWdtResetDetecte + } + #[doc = "WDT reset detected. Writing a one clears this reset."] + #[inline(always)] + pub fn is_wdt_reset_detected_(&self) -> bool { + *self == Wdt::WdtResetDetected_ + } +} +#[doc = "Status of the Brown-out detect reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bod { + #[doc = "0: No BOD reset detected."] + NoBodResetDetecte = 0, + #[doc = "1: BOD reset detected. Writing a one clears this reset."] + BodResetDetected_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bod) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BOD` reader - Status of the Brown-out detect reset"] +pub type BodR = crate::BitReader; +impl BodR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bod { + match self.bits { + false => Bod::NoBodResetDetecte, + true => Bod::BodResetDetected_, + } + } + #[doc = "No BOD reset detected."] + #[inline(always)] + pub fn is_no_bod_reset_detecte(&self) -> bool { + *self == Bod::NoBodResetDetecte + } + #[doc = "BOD reset detected. Writing a one clears this reset."] + #[inline(always)] + pub fn is_bod_reset_detected_(&self) -> bool { + *self == Bod::BodResetDetected_ + } +} +#[doc = "Status of the software system reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sysrst { + #[doc = "0: No System reset detected."] + NoSystemResetDete = 0, + #[doc = "1: System reset detected. Writing a one clears this reset."] + SystemResetDetecte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sysrst) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SYSRST` reader - Status of the software system reset"] +pub type SysrstR = crate::BitReader; +impl SysrstR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sysrst { + match self.bits { + false => Sysrst::NoSystemResetDete, + true => Sysrst::SystemResetDetecte, + } + } + #[doc = "No System reset detected."] + #[inline(always)] + pub fn is_no_system_reset_dete(&self) -> bool { + *self == Sysrst::NoSystemResetDete + } + #[doc = "System reset detected. Writing a one clears this reset."] + #[inline(always)] + pub fn is_system_reset_detecte(&self) -> bool { + *self == Sysrst::SystemResetDetecte + } +} +impl R { + #[doc = "Bit 0 - POR reset status"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Status of the external RESET pin."] + #[inline(always)] + pub fn extrst(&self) -> ExtrstR { + ExtrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Status of the Watchdog reset"] + #[inline(always)] + pub fn wdt(&self) -> WdtR { + WdtR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Status of the Brown-out detect reset"] + #[inline(always)] + pub fn bod(&self) -> BodR { + BodR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Status of the software system reset"] + #[inline(always)] + pub fn sysrst(&self) -> SysrstR { + SysrstR::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "System reset status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysrststat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SysrststatSpec; +impl crate::RegisterSpec for SysrststatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysrststat::R`](R) reader structure"] +impl crate::Readable for SysrststatSpec {} +#[doc = "`reset()` method sets SYSRSTSTAT to value 0"] +impl crate::Resettable for SysrststatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/systckcal.rs b/rust-embedded/lpc111x-pac/src/syscon/systckcal.rs new file mode 100644 index 0000000..d9c9ed2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/systckcal.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SYSTCKCAL` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTCKCAL` writer"] +pub type W = crate::W; +#[doc = "Field `CAL` reader - System tick timer calibration value"] +pub type CalR = crate::FieldReader; +#[doc = "Field `CAL` writer - System tick timer calibration value"] +pub type CalW<'a, REG> = crate::FieldWriter<'a, REG, 26, u32>; +impl R { + #[doc = "Bits 0:25 - System tick timer calibration value"] + #[inline(always)] + pub fn cal(&self) -> CalR { + CalR::new(self.bits & 0x03ff_ffff) + } +} +impl W { + #[doc = "Bits 0:25 - System tick timer calibration value"] + #[inline(always)] + #[must_use] + pub fn cal(&mut self) -> CalW { + CalW::new(self, 0) + } +} +#[doc = "System tick counter calibration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systckcal::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systckcal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystckcalSpec; +impl crate::RegisterSpec for SystckcalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systckcal::R`](R) reader structure"] +impl crate::Readable for SystckcalSpec {} +#[doc = "`write(|w| ..)` method takes [`systckcal::W`](W) writer structure"] +impl crate::Writable for SystckcalSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSTCKCAL to value 0x04"] +impl crate::Resettable for SystckcalSpec { + const RESET_VALUE: u32 = 0x04; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/uartclkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/uartclkdiv.rs new file mode 100644 index 0000000..7c48ac2 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/uartclkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `UARTCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `UARTCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "UART clock divder\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uartclkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uartclkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UartclkdivSpec; +impl crate::RegisterSpec for UartclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartclkdiv::R`](R) reader structure"] +impl crate::Readable for UartclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`uartclkdiv::W`](W) writer structure"] +impl crate::Writable for UartclkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTCLKDIV to value 0"] +impl crate::Resettable for UartclkdivSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/wdtclkdiv.rs b/rust-embedded/lpc111x-pac/src/syscon/wdtclkdiv.rs new file mode 100644 index 0000000..7d009e6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/wdtclkdiv.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDTCLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `DIV` reader - WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivR = crate::FieldReader; +#[doc = "Field `DIV` writer - WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255."] +pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + pub fn div(&self) -> DivR { + DivR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255."] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DivW { + DivW::new(self, 0) + } +} +#[doc = "WDT clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtclkdivSpec; +impl crate::RegisterSpec for WdtclkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtclkdiv::R`](R) reader structure"] +impl crate::Readable for WdtclkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`wdtclkdiv::W`](W) writer structure"] +impl crate::Writable for WdtclkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDTCLKDIV to value 0"] +impl crate::Resettable for WdtclkdivSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/wdtclksel.rs b/rust-embedded/lpc111x-pac/src/syscon/wdtclksel.rs new file mode 100644 index 0000000..901c721 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/wdtclksel.rs @@ -0,0 +1,108 @@ +#[doc = "Register `WDTCLKSEL` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCLKSEL` writer"] +pub type W = crate::W; +#[doc = "WDT clock source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Sel { + #[doc = "0: IRC oscillator"] + IrcOscillator = 0, + #[doc = "1: Main clock"] + MainClock = 1, + #[doc = "2: Watchdog oscillator"] + WatchdogOscillator = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Sel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Sel { + type Ux = u8; +} +#[doc = "Field `SEL` reader - WDT clock source"] +pub type SelR = crate::FieldReader; +impl SelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sel { + match self.bits { + 0 => Sel::IrcOscillator, + 1 => Sel::MainClock, + 2 => Sel::WatchdogOscillator, + _ => unreachable!(), + } + } + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn is_irc_oscillator(&self) -> bool { + *self == Sel::IrcOscillator + } + #[doc = "Main clock"] + #[inline(always)] + pub fn is_main_clock(&self) -> bool { + *self == Sel::MainClock + } + #[doc = "Watchdog oscillator"] + #[inline(always)] + pub fn is_watchdog_oscillator(&self) -> bool { + *self == Sel::WatchdogOscillator + } +} +#[doc = "Field `SEL` writer - WDT clock source"] +pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 2, Sel>; +impl<'a, REG> SelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "IRC oscillator"] + #[inline(always)] + pub fn irc_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::IrcOscillator) + } + #[doc = "Main clock"] + #[inline(always)] + pub fn main_clock(self) -> &'a mut crate::W { + self.variant(Sel::MainClock) + } + #[doc = "Watchdog oscillator"] + #[inline(always)] + pub fn watchdog_oscillator(self) -> &'a mut crate::W { + self.variant(Sel::WatchdogOscillator) + } +} +impl R { + #[doc = "Bits 0:1 - WDT clock source"] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - WDT clock source"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 0) + } +} +#[doc = "WDT clock source select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclksel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtclkselSpec; +impl crate::RegisterSpec for WdtclkselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtclksel::R`](R) reader structure"] +impl crate::Readable for WdtclkselSpec {} +#[doc = "`write(|w| ..)` method takes [`wdtclksel::W`](W) writer structure"] +impl crate::Writable for WdtclkselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDTCLKSEL to value 0"] +impl crate::Resettable for WdtclkselSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/wdtclkuen.rs b/rust-embedded/lpc111x-pac/src/syscon/wdtclkuen.rs new file mode 100644 index 0000000..07a1bf6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/wdtclkuen.rs @@ -0,0 +1,89 @@ +#[doc = "Register `WDTCLKUEN` reader"] +pub type R = crate::R; +#[doc = "Register `WDTCLKUEN` writer"] +pub type W = crate::W; +#[doc = "Enable WDT clock source update\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ena { + #[doc = "0: No change"] + NoChange = 0, + #[doc = "1: Update clock source"] + UpdateClockSource = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ena) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENA` reader - Enable WDT clock source update"] +pub type EnaR = crate::BitReader; +impl EnaR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ena { + match self.bits { + false => Ena::NoChange, + true => Ena::UpdateClockSource, + } + } + #[doc = "No change"] + #[inline(always)] + pub fn is_no_change(&self) -> bool { + *self == Ena::NoChange + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn is_update_clock_source(&self) -> bool { + *self == Ena::UpdateClockSource + } +} +#[doc = "Field `ENA` writer - Enable WDT clock source update"] +pub type EnaW<'a, REG> = crate::BitWriter<'a, REG, Ena>; +impl<'a, REG> EnaW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No change"] + #[inline(always)] + pub fn no_change(self) -> &'a mut crate::W { + self.variant(Ena::NoChange) + } + #[doc = "Update clock source"] + #[inline(always)] + pub fn update_clock_source(self) -> &'a mut crate::W { + self.variant(Ena::UpdateClockSource) + } +} +impl R { + #[doc = "Bit 0 - Enable WDT clock source update"] + #[inline(always)] + pub fn ena(&self) -> EnaR { + EnaR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable WDT clock source update"] + #[inline(always)] + #[must_use] + pub fn ena(&mut self) -> EnaW { + EnaW::new(self, 0) + } +} +#[doc = "WDT clock source update enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtclkuen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtclkuen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtclkuenSpec; +impl crate::RegisterSpec for WdtclkuenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtclkuen::R`](R) reader structure"] +impl crate::Readable for WdtclkuenSpec {} +#[doc = "`write(|w| ..)` method takes [`wdtclkuen::W`](W) writer structure"] +impl crate::Writable for WdtclkuenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDTCLKUEN to value 0"] +impl crate::Resettable for WdtclkuenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/syscon/wdtoscctrl.rs b/rust-embedded/lpc111x-pac/src/syscon/wdtoscctrl.rs new file mode 100644 index 0000000..6482368 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/syscon/wdtoscctrl.rs @@ -0,0 +1,279 @@ +#[doc = "Register `WDTOSCCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `WDTOSCCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `DIVSEL` reader - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"] +pub type DivselR = crate::FieldReader; +#[doc = "Field `DIVSEL` writer - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"] +pub type DivselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Select watchdog oscillator analog output frequency (Fclkana).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Freqsel { + #[doc = "1: 0.6 MHz"] + _0_6Mhz = 1, + #[doc = "2: 1.05 MHz"] + _1_05Mhz = 2, + #[doc = "3: 1.4 MHz"] + _1_4Mhz = 3, + #[doc = "4: 1.75 MHz"] + _1_75Mhz = 4, + #[doc = "5: 2.1 MHz"] + _2_1Mhz = 5, + #[doc = "6: 2.4 MHz"] + _2_4Mhz = 6, + #[doc = "7: 2.7 MHz"] + _2_7Mhz = 7, + #[doc = "8: 3.0 MHz"] + _3_0Mhz = 8, + #[doc = "9: 3.25 MHz"] + _3_25Mhz = 9, + #[doc = "10: 3.5 MHz"] + _3_5Mhz = 10, + #[doc = "11: 3.75 MHz"] + _3_75Mhz = 11, + #[doc = "12: 4.0 MHz"] + _4_0Mhz = 12, + #[doc = "13: 4.2 MHz"] + _4_2Mhz = 13, + #[doc = "14: 4.4 MHz"] + _4_4Mhz = 14, + #[doc = "15: 4.6 MHz"] + _4_6Mhz = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Freqsel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Freqsel { + type Ux = u8; +} +#[doc = "Field `FREQSEL` reader - Select watchdog oscillator analog output frequency (Fclkana)."] +pub type FreqselR = crate::FieldReader; +impl FreqselR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(Freqsel::_0_6Mhz), + 2 => Some(Freqsel::_1_05Mhz), + 3 => Some(Freqsel::_1_4Mhz), + 4 => Some(Freqsel::_1_75Mhz), + 5 => Some(Freqsel::_2_1Mhz), + 6 => Some(Freqsel::_2_4Mhz), + 7 => Some(Freqsel::_2_7Mhz), + 8 => Some(Freqsel::_3_0Mhz), + 9 => Some(Freqsel::_3_25Mhz), + 10 => Some(Freqsel::_3_5Mhz), + 11 => Some(Freqsel::_3_75Mhz), + 12 => Some(Freqsel::_4_0Mhz), + 13 => Some(Freqsel::_4_2Mhz), + 14 => Some(Freqsel::_4_4Mhz), + 15 => Some(Freqsel::_4_6Mhz), + _ => None, + } + } + #[doc = "0.6 MHz"] + #[inline(always)] + pub fn is_0_6_mhz(&self) -> bool { + *self == Freqsel::_0_6Mhz + } + #[doc = "1.05 MHz"] + #[inline(always)] + pub fn is_1_05_mhz(&self) -> bool { + *self == Freqsel::_1_05Mhz + } + #[doc = "1.4 MHz"] + #[inline(always)] + pub fn is_1_4_mhz(&self) -> bool { + *self == Freqsel::_1_4Mhz + } + #[doc = "1.75 MHz"] + #[inline(always)] + pub fn is_1_75_mhz(&self) -> bool { + *self == Freqsel::_1_75Mhz + } + #[doc = "2.1 MHz"] + #[inline(always)] + pub fn is_2_1_mhz(&self) -> bool { + *self == Freqsel::_2_1Mhz + } + #[doc = "2.4 MHz"] + #[inline(always)] + pub fn is_2_4_mhz(&self) -> bool { + *self == Freqsel::_2_4Mhz + } + #[doc = "2.7 MHz"] + #[inline(always)] + pub fn is_2_7_mhz(&self) -> bool { + *self == Freqsel::_2_7Mhz + } + #[doc = "3.0 MHz"] + #[inline(always)] + pub fn is_3_0_mhz(&self) -> bool { + *self == Freqsel::_3_0Mhz + } + #[doc = "3.25 MHz"] + #[inline(always)] + pub fn is_3_25_mhz(&self) -> bool { + *self == Freqsel::_3_25Mhz + } + #[doc = "3.5 MHz"] + #[inline(always)] + pub fn is_3_5_mhz(&self) -> bool { + *self == Freqsel::_3_5Mhz + } + #[doc = "3.75 MHz"] + #[inline(always)] + pub fn is_3_75_mhz(&self) -> bool { + *self == Freqsel::_3_75Mhz + } + #[doc = "4.0 MHz"] + #[inline(always)] + pub fn is_4_0_mhz(&self) -> bool { + *self == Freqsel::_4_0Mhz + } + #[doc = "4.2 MHz"] + #[inline(always)] + pub fn is_4_2_mhz(&self) -> bool { + *self == Freqsel::_4_2Mhz + } + #[doc = "4.4 MHz"] + #[inline(always)] + pub fn is_4_4_mhz(&self) -> bool { + *self == Freqsel::_4_4Mhz + } + #[doc = "4.6 MHz"] + #[inline(always)] + pub fn is_4_6_mhz(&self) -> bool { + *self == Freqsel::_4_6Mhz + } +} +#[doc = "Field `FREQSEL` writer - Select watchdog oscillator analog output frequency (Fclkana)."] +pub type FreqselW<'a, REG> = crate::FieldWriter<'a, REG, 4, Freqsel>; +impl<'a, REG> FreqselW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "0.6 MHz"] + #[inline(always)] + pub fn _0_6_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_0_6Mhz) + } + #[doc = "1.05 MHz"] + #[inline(always)] + pub fn _1_05_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_1_05Mhz) + } + #[doc = "1.4 MHz"] + #[inline(always)] + pub fn _1_4_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_1_4Mhz) + } + #[doc = "1.75 MHz"] + #[inline(always)] + pub fn _1_75_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_1_75Mhz) + } + #[doc = "2.1 MHz"] + #[inline(always)] + pub fn _2_1_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_2_1Mhz) + } + #[doc = "2.4 MHz"] + #[inline(always)] + pub fn _2_4_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_2_4Mhz) + } + #[doc = "2.7 MHz"] + #[inline(always)] + pub fn _2_7_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_2_7Mhz) + } + #[doc = "3.0 MHz"] + #[inline(always)] + pub fn _3_0_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_3_0Mhz) + } + #[doc = "3.25 MHz"] + #[inline(always)] + pub fn _3_25_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_3_25Mhz) + } + #[doc = "3.5 MHz"] + #[inline(always)] + pub fn _3_5_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_3_5Mhz) + } + #[doc = "3.75 MHz"] + #[inline(always)] + pub fn _3_75_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_3_75Mhz) + } + #[doc = "4.0 MHz"] + #[inline(always)] + pub fn _4_0_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_4_0Mhz) + } + #[doc = "4.2 MHz"] + #[inline(always)] + pub fn _4_2_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_4_2Mhz) + } + #[doc = "4.4 MHz"] + #[inline(always)] + pub fn _4_4_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_4_4Mhz) + } + #[doc = "4.6 MHz"] + #[inline(always)] + pub fn _4_6_mhz(self) -> &'a mut crate::W { + self.variant(Freqsel::_4_6Mhz) + } +} +impl R { + #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"] + #[inline(always)] + pub fn divsel(&self) -> DivselR { + DivselR::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:8 - Select watchdog oscillator analog output frequency (Fclkana)."] + #[inline(always)] + pub fn freqsel(&self) -> FreqselR { + FreqselR::new(((self.bits >> 5) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64"] + #[inline(always)] + #[must_use] + pub fn divsel(&mut self) -> DivselW { + DivselW::new(self, 0) + } + #[doc = "Bits 5:8 - Select watchdog oscillator analog output frequency (Fclkana)."] + #[inline(always)] + #[must_use] + pub fn freqsel(&mut self) -> FreqselW { + FreqselW::new(self, 5) + } +} +#[doc = "Watchdog oscillator control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtoscctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtoscctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtoscctrlSpec; +impl crate::RegisterSpec for WdtoscctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtoscctrl::R`](R) reader structure"] +impl crate::Readable for WdtoscctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`wdtoscctrl::W`](W) writer structure"] +impl crate::Writable for WdtoscctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDTOSCCTRL to value 0"] +impl crate::Resettable for WdtoscctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart.rs b/rust-embedded/lpc111x-pac/src/uart.rs new file mode 100644 index 0000000..8a22787 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart.rs @@ -0,0 +1,221 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved_0_dll: [u8; 0x04], + _reserved_1_dlm: [u8; 0x04], + _reserved_2_fcr: [u8; 0x04], + lcr: Lcr, + mcr: Mcr, + lsr: Lsr, + msr: Msr, + scr: Scr, + acr: Acr, + _reserved9: [u8; 0x04], + fdr: Fdr, + _reserved10: [u8; 0x04], + ter: Ter, + _reserved11: [u8; 0x18], + rs485ctrl: Rs485ctrl, + rs485adrmatch: Rs485adrmatch, + rs485dly: Rs485dly, +} +impl RegisterBlock { + #[doc = "0x00 - Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"] + #[inline(always)] + pub const fn dll(&self) -> &Dll { + unsafe { &*(self as *const Self).cast::().add(0).cast() } + } + #[doc = "0x00 - Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)"] + #[inline(always)] + pub const fn thr(&self) -> &Thr { + unsafe { &*(self as *const Self).cast::().add(0).cast() } + } + #[doc = "0x00 - Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)"] + #[inline(always)] + pub const fn rbr(&self) -> &Rbr { + unsafe { &*(self as *const Self).cast::().add(0).cast() } + } + #[doc = "0x04 - Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)"] + #[inline(always)] + pub const fn ier(&self) -> &Ier { + unsafe { &*(self as *const Self).cast::().add(4).cast() } + } + #[doc = "0x04 - Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"] + #[inline(always)] + pub const fn dlm(&self) -> &Dlm { + unsafe { &*(self as *const Self).cast::().add(4).cast() } + } + #[doc = "0x08 - FIFO Control Register. Controls UART FIFO usage and modes."] + #[inline(always)] + pub const fn fcr(&self) -> &Fcr { + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending."] + #[inline(always)] + pub const fn iir(&self) -> &Iir { + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Line Control Register. Contains controls for frame formatting and break generation."] + #[inline(always)] + pub const fn lcr(&self) -> &Lcr { + &self.lcr + } + #[doc = "0x10 - Modem control register"] + #[inline(always)] + pub const fn mcr(&self) -> &Mcr { + &self.mcr + } + #[doc = "0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors."] + #[inline(always)] + pub const fn lsr(&self) -> &Lsr { + &self.lsr + } + #[doc = "0x18 - Modem status register"] + #[inline(always)] + pub const fn msr(&self) -> &Msr { + &self.msr + } + #[doc = "0x1c - Scratch Pad Register. Eight-bit temporary storage for software."] + #[inline(always)] + pub const fn scr(&self) -> &Scr { + &self.scr + } + #[doc = "0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature."] + #[inline(always)] + pub const fn acr(&self) -> &Acr { + &self.acr + } + #[doc = "0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider."] + #[inline(always)] + pub const fn fdr(&self) -> &Fdr { + &self.fdr + } + #[doc = "0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control."] + #[inline(always)] + pub const fn ter(&self) -> &Ter { + &self.ter + } + #[doc = "0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."] + #[inline(always)] + pub const fn rs485ctrl(&self) -> &Rs485ctrl { + &self.rs485ctrl + } + #[doc = "0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."] + #[inline(always)] + pub const fn rs485adrmatch(&self) -> &Rs485adrmatch { + &self.rs485adrmatch + } + #[doc = "0x54 - RS-485/EIA-485 direction control delay."] + #[inline(always)] + pub const fn rs485dly(&self) -> &Rs485dly { + &self.rs485dly + } +} +#[doc = "RBR (r) register accessor: Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`]. WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`] +module"] +#[doc(alias = "RBR")] +pub type Rbr = crate::Reg; +#[doc = "Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)"] +pub mod rbr; +#[doc = "THR (w) register accessor: Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`] +module"] +#[doc(alias = "THR")] +pub type Thr = crate::Reg; +#[doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)"] +pub mod thr; +#[doc = "DLL (rw) register accessor: Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`] +module"] +#[doc(alias = "DLL")] +pub type Dll = crate::Reg; +#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"] +pub mod dll; +#[doc = "DLM (rw) register accessor: Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlm`] +module"] +#[doc(alias = "DLM")] +pub type Dlm = crate::Reg; +#[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)"] +pub mod dlm; +#[doc = "IER (rw) register accessor: Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`] +module"] +#[doc(alias = "IER")] +pub type Ier = crate::Reg; +#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)"] +pub mod ier; +#[doc = "IIR (r) register accessor: Interrupt ID Register. Identifies which interrupt(s) are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`] +module"] +#[doc(alias = "IIR")] +pub type Iir = crate::Reg; +#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."] +pub mod iir; +#[doc = "FCR (w) register accessor: FIFO Control Register. Controls UART FIFO usage and modes.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`] +module"] +#[doc(alias = "FCR")] +pub type Fcr = crate::Reg; +#[doc = "FIFO Control Register. Controls UART FIFO usage and modes."] +pub mod fcr; +#[doc = "LCR (rw) register accessor: Line Control Register. Contains controls for frame formatting and break generation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`] +module"] +#[doc(alias = "LCR")] +pub type Lcr = crate::Reg; +#[doc = "Line Control Register. Contains controls for frame formatting and break generation."] +pub mod lcr; +#[doc = "MCR (rw) register accessor: Modem control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`] +module"] +#[doc(alias = "MCR")] +pub type Mcr = crate::Reg; +#[doc = "Modem control register"] +pub mod mcr; +#[doc = "LSR (r) register accessor: Line Status Register. Contains flags for transmit and receive status, including line errors.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`] +module"] +#[doc(alias = "LSR")] +pub type Lsr = crate::Reg; +#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."] +pub mod lsr; +#[doc = "MSR (r) register accessor: Modem status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`]. WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`] +module"] +#[doc(alias = "MSR")] +pub type Msr = crate::Reg; +#[doc = "Modem status register"] +pub mod msr; +#[doc = "SCR (rw) register accessor: Scratch Pad Register. Eight-bit temporary storage for software.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scr`] +module"] +#[doc(alias = "SCR")] +pub type Scr = crate::Reg; +#[doc = "Scratch Pad Register. Eight-bit temporary storage for software."] +pub mod scr; +#[doc = "ACR (rw) register accessor: Auto-baud Control Register. Contains controls for the auto-baud feature.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acr`] +module"] +#[doc(alias = "ACR")] +pub type Acr = crate::Reg; +#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."] +pub mod acr; +#[doc = "FDR (rw) register accessor: Fractional Divider Register. Generates a clock input for the baud rate divider.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fdr`] +module"] +#[doc(alias = "FDR")] +pub type Fdr = crate::Reg; +#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."] +pub mod fdr; +#[doc = "TER (rw) register accessor: Transmit Enable Register. Turns off UART transmitter for use with software flow control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ter::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ter`] +module"] +#[doc(alias = "TER")] +pub type Ter = crate::Reg; +#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."] +pub mod ter; +#[doc = "RS485CTRL (rw) register accessor: RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485ctrl`] +module"] +#[doc(alias = "RS485CTRL")] +pub type Rs485ctrl = crate::Reg; +#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."] +pub mod rs485ctrl; +#[doc = "RS485ADRMATCH (rw) register accessor: RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485adrmatch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485adrmatch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485adrmatch`] +module"] +#[doc(alias = "RS485ADRMATCH")] +pub type Rs485adrmatch = crate::Reg; +#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."] +pub mod rs485adrmatch; +#[doc = "RS485DLY (rw) register accessor: RS-485/EIA-485 direction control delay.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485dly::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485dly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485dly`] +module"] +#[doc(alias = "RS485DLY")] +pub type Rs485dly = crate::Reg; +#[doc = "RS-485/EIA-485 direction control delay."] +pub mod rs485dly; diff --git a/rust-embedded/lpc111x-pac/src/uart/acr.rs b/rust-embedded/lpc111x-pac/src/uart/acr.rs new file mode 100644 index 0000000..d5b1903 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/acr.rs @@ -0,0 +1,345 @@ +#[doc = "Register `ACR` reader"] +pub type R = crate::R; +#[doc = "Register `ACR` writer"] +pub type W = crate::W; +#[doc = "Start bit. This bit is automatically cleared after auto-baud completion.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Start { + #[doc = "0: Auto-baud stop (auto-baud is not running)."] + Stop = 0, + #[doc = "1: Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."] + Start = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Start) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `START` reader - Start bit. This bit is automatically cleared after auto-baud completion."] +pub type StartR = crate::BitReader; +impl StartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Start { + match self.bits { + false => Start::Stop, + true => Start::Start, + } + } + #[doc = "Auto-baud stop (auto-baud is not running)."] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == Start::Stop + } + #[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == Start::Start + } +} +#[doc = "Field `START` writer - Start bit. This bit is automatically cleared after auto-baud completion."] +pub type StartW<'a, REG> = crate::BitWriter<'a, REG, Start>; +impl<'a, REG> StartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto-baud stop (auto-baud is not running)."] + #[inline(always)] + pub fn stop(self) -> &'a mut crate::W { + self.variant(Start::Stop) + } + #[doc = "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion."] + #[inline(always)] + pub fn start(self) -> &'a mut crate::W { + self.variant(Start::Start) + } +} +#[doc = "Auto-baud mode select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Mode { + #[doc = "0: Mode 0."] + Mode0_ = 0, + #[doc = "1: Mode 1."] + Mode1_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Mode) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Auto-baud mode select"] +pub type ModeR = crate::BitReader; +impl ModeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Mode { + match self.bits { + false => Mode::Mode0_, + true => Mode::Mode1_, + } + } + #[doc = "Mode 0."] + #[inline(always)] + pub fn is_mode_0_(&self) -> bool { + *self == Mode::Mode0_ + } + #[doc = "Mode 1."] + #[inline(always)] + pub fn is_mode_1_(&self) -> bool { + *self == Mode::Mode1_ + } +} +#[doc = "Field `MODE` writer - Auto-baud mode select"] +pub type ModeW<'a, REG> = crate::BitWriter<'a, REG, Mode>; +impl<'a, REG> ModeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Mode 0."] + #[inline(always)] + pub fn mode_0_(self) -> &'a mut crate::W { + self.variant(Mode::Mode0_) + } + #[doc = "Mode 1."] + #[inline(always)] + pub fn mode_1_(self) -> &'a mut crate::W { + self.variant(Mode::Mode1_) + } +} +#[doc = "Restart enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Autorestart { + #[doc = "0: No restart"] + NoRestart = 0, + #[doc = "1: Restart in case of time-out (counter restarts at next UART Rx falling edge)"] + RestartInCaseOfT = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Autorestart) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AUTORESTART` reader - Restart enable"] +pub type AutorestartR = crate::BitReader; +impl AutorestartR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Autorestart { + match self.bits { + false => Autorestart::NoRestart, + true => Autorestart::RestartInCaseOfT, + } + } + #[doc = "No restart"] + #[inline(always)] + pub fn is_no_restart(&self) -> bool { + *self == Autorestart::NoRestart + } + #[doc = "Restart in case of time-out (counter restarts at next UART Rx falling edge)"] + #[inline(always)] + pub fn is_restart_in_case_of_t(&self) -> bool { + *self == Autorestart::RestartInCaseOfT + } +} +#[doc = "Field `AUTORESTART` writer - Restart enable"] +pub type AutorestartW<'a, REG> = crate::BitWriter<'a, REG, Autorestart>; +impl<'a, REG> AutorestartW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No restart"] + #[inline(always)] + pub fn no_restart(self) -> &'a mut crate::W { + self.variant(Autorestart::NoRestart) + } + #[doc = "Restart in case of time-out (counter restarts at next UART Rx falling edge)"] + #[inline(always)] + pub fn restart_in_case_of_t(self) -> &'a mut crate::W { + self.variant(Autorestart::RestartInCaseOfT) + } +} +#[doc = "End of auto-baud interrupt clear (write only accessible)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abeointclr { + #[doc = "0: Writing a 0 has no impact."] + Noimpact = 0, + #[doc = "1: Writing a 1 will clear the corresponding interrupt in the IIR."] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abeointclr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABEOINTCLR` reader - End of auto-baud interrupt clear (write only accessible)"] +pub type AbeointclrR = crate::BitReader; +impl AbeointclrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abeointclr { + match self.bits { + false => Abeointclr::Noimpact, + true => Abeointclr::Clear, + } + } + #[doc = "Writing a 0 has no impact."] + #[inline(always)] + pub fn is_noimpact(&self) -> bool { + *self == Abeointclr::Noimpact + } + #[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Abeointclr::Clear + } +} +#[doc = "Field `ABEOINTCLR` writer - End of auto-baud interrupt clear (write only accessible)"] +pub type AbeointclrW<'a, REG> = crate::BitWriter<'a, REG, Abeointclr>; +impl<'a, REG> AbeointclrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Writing a 0 has no impact."] + #[inline(always)] + pub fn noimpact(self) -> &'a mut crate::W { + self.variant(Abeointclr::Noimpact) + } + #[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Abeointclr::Clear) + } +} +#[doc = "Auto-baud time-out interrupt clear (write only accessible)\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abtointclr { + #[doc = "0: Writing a 0 has no impact."] + Noimpact = 0, + #[doc = "1: Writing a 1 will clear the corresponding interrupt in the IIR."] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abtointclr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABTOINTCLR` reader - Auto-baud time-out interrupt clear (write only accessible)"] +pub type AbtointclrR = crate::BitReader; +impl AbtointclrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abtointclr { + match self.bits { + false => Abtointclr::Noimpact, + true => Abtointclr::Clear, + } + } + #[doc = "Writing a 0 has no impact."] + #[inline(always)] + pub fn is_noimpact(&self) -> bool { + *self == Abtointclr::Noimpact + } + #[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == Abtointclr::Clear + } +} +#[doc = "Field `ABTOINTCLR` writer - Auto-baud time-out interrupt clear (write only accessible)"] +pub type AbtointclrW<'a, REG> = crate::BitWriter<'a, REG, Abtointclr>; +impl<'a, REG> AbtointclrW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Writing a 0 has no impact."] + #[inline(always)] + pub fn noimpact(self) -> &'a mut crate::W { + self.variant(Abtointclr::Noimpact) + } + #[doc = "Writing a 1 will clear the corresponding interrupt in the IIR."] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Abtointclr::Clear) + } +} +impl R { + #[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."] + #[inline(always)] + pub fn start(&self) -> StartR { + StartR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Auto-baud mode select"] + #[inline(always)] + pub fn mode(&self) -> ModeR { + ModeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Restart enable"] + #[inline(always)] + pub fn autorestart(&self) -> AutorestartR { + AutorestartR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - End of auto-baud interrupt clear (write only accessible)"] + #[inline(always)] + pub fn abeointclr(&self) -> AbeointclrR { + AbeointclrR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Auto-baud time-out interrupt clear (write only accessible)"] + #[inline(always)] + pub fn abtointclr(&self) -> AbtointclrR { + AbtointclrR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Start bit. This bit is automatically cleared after auto-baud completion."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> StartW { + StartW::new(self, 0) + } + #[doc = "Bit 1 - Auto-baud mode select"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> ModeW { + ModeW::new(self, 1) + } + #[doc = "Bit 2 - Restart enable"] + #[inline(always)] + #[must_use] + pub fn autorestart(&mut self) -> AutorestartW { + AutorestartW::new(self, 2) + } + #[doc = "Bit 8 - End of auto-baud interrupt clear (write only accessible)"] + #[inline(always)] + #[must_use] + pub fn abeointclr(&mut self) -> AbeointclrW { + AbeointclrW::new(self, 8) + } + #[doc = "Bit 9 - Auto-baud time-out interrupt clear (write only accessible)"] + #[inline(always)] + #[must_use] + pub fn abtointclr(&mut self) -> AbtointclrW { + AbtointclrW::new(self, 9) + } +} +#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AcrSpec; +impl crate::RegisterSpec for AcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`acr::R`](R) reader structure"] +impl crate::Readable for AcrSpec {} +#[doc = "`write(|w| ..)` method takes [`acr::W`](W) writer structure"] +impl crate::Writable for AcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ACR to value 0"] +impl crate::Resettable for AcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/dll.rs b/rust-embedded/lpc111x-pac/src/uart/dll.rs new file mode 100644 index 0000000..64ac7c1 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/dll.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DLL` reader"] +pub type R = crate::R; +#[doc = "Register `DLL` writer"] +pub type W = crate::W; +#[doc = "Field `DLLSB` reader - The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART."] +pub type DllsbR = crate::FieldReader; +#[doc = "Field `DLLSB` writer - The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART."] +pub type DllsbW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART."] + #[inline(always)] + pub fn dllsb(&self) -> DllsbR { + DllsbR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART."] + #[inline(always)] + #[must_use] + pub fn dllsb(&mut self) -> DllsbW { + DllsbW::new(self, 0) + } +} +#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DllSpec; +impl crate::RegisterSpec for DllSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dll::R`](R) reader structure"] +impl crate::Readable for DllSpec {} +#[doc = "`write(|w| ..)` method takes [`dll::W`](W) writer structure"] +impl crate::Writable for DllSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DLL to value 0x01"] +impl crate::Resettable for DllSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/dlm.rs b/rust-embedded/lpc111x-pac/src/uart/dlm.rs new file mode 100644 index 0000000..537293f --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/dlm.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DLM` reader"] +pub type R = crate::R; +#[doc = "Register `DLM` writer"] +pub type W = crate::W; +#[doc = "Field `DLMSB` reader - The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART."] +pub type DlmsbR = crate::FieldReader; +#[doc = "Field `DLMSB` writer - The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART."] +pub type DlmsbW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART."] + #[inline(always)] + pub fn dlmsb(&self) -> DlmsbR { + DlmsbR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART."] + #[inline(always)] + #[must_use] + pub fn dlmsb(&mut self) -> DlmsbW { + DlmsbW::new(self, 0) + } +} +#[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DlmSpec; +impl crate::RegisterSpec for DlmSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dlm::R`](R) reader structure"] +impl crate::Readable for DlmSpec {} +#[doc = "`write(|w| ..)` method takes [`dlm::W`](W) writer structure"] +impl crate::Writable for DlmSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DLM to value 0"] +impl crate::Resettable for DlmSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/fcr.rs b/rust-embedded/lpc111x-pac/src/uart/fcr.rs new file mode 100644 index 0000000..19d02e5 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/fcr.rs @@ -0,0 +1,192 @@ +#[doc = "Register `FCR` writer"] +pub type W = crate::W; +#[doc = "FIFO Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fifoen { + #[doc = "0: UART FIFOs are disabled. Must not be used in the application."] + Disabled = 0, + #[doc = "1: Active high enable for both UART Rx and TX FIFOs and FCR\\[7:1\\] +access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fifoen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIFOEN` writer - FIFO Enable"] +pub type FifoenW<'a, REG> = crate::BitWriter<'a, REG, Fifoen>; +impl<'a, REG> FifoenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "UART FIFOs are disabled. Must not be used in the application."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Fifoen::Disabled) + } + #[doc = "Active high enable for both UART Rx and TX FIFOs and FCR\\[7:1\\] +access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Fifoen::Enabled) + } +} +#[doc = "RX FIFO Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxfifores { + #[doc = "0: No impact on either of UART FIFOs."] + NoImpactOnEither_ = 0, + #[doc = "1: Writing a logic 1 to FCR\\[1\\] +will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing."] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxfifores) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXFIFORES` writer - RX FIFO Reset"] +pub type RxfiforesW<'a, REG> = crate::BitWriter<'a, REG, Rxfifores>; +impl<'a, REG> RxfiforesW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No impact on either of UART FIFOs."] + #[inline(always)] + pub fn no_impact_on_either_(self) -> &'a mut crate::W { + self.variant(Rxfifores::NoImpactOnEither_) + } + #[doc = "Writing a logic 1 to FCR\\[1\\] +will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing."] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Rxfifores::Clear) + } +} +#[doc = "TX FIFO Reset\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Txfifores { + #[doc = "0: No impact on either of UART FIFOs."] + NoImpactOnEither_ = 0, + #[doc = "1: Writing a logic 1 to FCR\\[2\\] +will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing."] + Clear = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Txfifores) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TXFIFORES` writer - TX FIFO Reset"] +pub type TxfiforesW<'a, REG> = crate::BitWriter<'a, REG, Txfifores>; +impl<'a, REG> TxfiforesW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No impact on either of UART FIFOs."] + #[inline(always)] + pub fn no_impact_on_either_(self) -> &'a mut crate::W { + self.variant(Txfifores::NoImpactOnEither_) + } + #[doc = "Writing a logic 1 to FCR\\[2\\] +will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing."] + #[inline(always)] + pub fn clear(self) -> &'a mut crate::W { + self.variant(Txfifores::Clear) + } +} +#[doc = "RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Rxtl { + #[doc = "0: Trigger level 0 (1 character or 0x01)."] + TriggerLevel0_1C = 0, + #[doc = "1: Trigger level 1 (4 characters or 0x04)."] + TriggerLevel1_4C = 1, + #[doc = "2: Trigger level 2 (8 characters or 0x08)."] + TriggerLevel2_8C = 2, + #[doc = "3: Trigger level 3 (14 characters or 0x0E)."] + TriggerLevel3_14_ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Rxtl) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Rxtl { + type Ux = u8; +} +#[doc = "Field `RXTL` writer - RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated."] +pub type RxtlW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Rxtl>; +impl<'a, REG> RxtlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Trigger level 0 (1 character or 0x01)."] + #[inline(always)] + pub fn trigger_level_0_1_c(self) -> &'a mut crate::W { + self.variant(Rxtl::TriggerLevel0_1C) + } + #[doc = "Trigger level 1 (4 characters or 0x04)."] + #[inline(always)] + pub fn trigger_level_1_4_c(self) -> &'a mut crate::W { + self.variant(Rxtl::TriggerLevel1_4C) + } + #[doc = "Trigger level 2 (8 characters or 0x08)."] + #[inline(always)] + pub fn trigger_level_2_8_c(self) -> &'a mut crate::W { + self.variant(Rxtl::TriggerLevel2_8C) + } + #[doc = "Trigger level 3 (14 characters or 0x0E)."] + #[inline(always)] + pub fn trigger_level_3_14_(self) -> &'a mut crate::W { + self.variant(Rxtl::TriggerLevel3_14_) + } +} +impl W { + #[doc = "Bit 0 - FIFO Enable"] + #[inline(always)] + #[must_use] + pub fn fifoen(&mut self) -> FifoenW { + FifoenW::new(self, 0) + } + #[doc = "Bit 1 - RX FIFO Reset"] + #[inline(always)] + #[must_use] + pub fn rxfifores(&mut self) -> RxfiforesW { + RxfiforesW::new(self, 1) + } + #[doc = "Bit 2 - TX FIFO Reset"] + #[inline(always)] + #[must_use] + pub fn txfifores(&mut self) -> TxfiforesW { + TxfiforesW::new(self, 2) + } + #[doc = "Bits 6:7 - RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated."] + #[inline(always)] + #[must_use] + pub fn rxtl(&mut self) -> RxtlW { + RxtlW::new(self, 6) + } +} +#[doc = "FIFO Control Register. Controls UART FIFO usage and modes.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FcrSpec; +impl crate::RegisterSpec for FcrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] +impl crate::Writable for FcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FCR to value 0"] +impl crate::Resettable for FcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/fdr.rs b/rust-embedded/lpc111x-pac/src/uart/fdr.rs new file mode 100644 index 0000000..bfcb420 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/fdr.rs @@ -0,0 +1,55 @@ +#[doc = "Register `FDR` reader"] +pub type R = crate::R; +#[doc = "Register `FDR` writer"] +pub type W = crate::W; +#[doc = "Field `DIVADDVAL` reader - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate."] +pub type DivaddvalR = crate::FieldReader; +#[doc = "Field `DIVADDVAL` writer - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate."] +pub type DivaddvalW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `MULVAL` reader - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not."] +pub type MulvalR = crate::FieldReader; +#[doc = "Field `MULVAL` writer - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not."] +pub type MulvalW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate."] + #[inline(always)] + pub fn divaddval(&self) -> DivaddvalR { + DivaddvalR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not."] + #[inline(always)] + pub fn mulval(&self) -> MulvalR { + MulvalR::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate."] + #[inline(always)] + #[must_use] + pub fn divaddval(&mut self) -> DivaddvalW { + DivaddvalW::new(self, 0) + } + #[doc = "Bits 4:7 - Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not."] + #[inline(always)] + #[must_use] + pub fn mulval(&mut self) -> MulvalW { + MulvalW::new(self, 4) + } +} +#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FdrSpec; +impl crate::RegisterSpec for FdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdr::R`](R) reader structure"] +impl crate::Readable for FdrSpec {} +#[doc = "`write(|w| ..)` method takes [`fdr::W`](W) writer structure"] +impl crate::Writable for FdrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FDR to value 0x10"] +impl crate::Resettable for FdrSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/ier.rs b/rust-embedded/lpc111x-pac/src/uart/ier.rs new file mode 100644 index 0000000..a13dbe0 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/ier.rs @@ -0,0 +1,345 @@ +#[doc = "Register `IER` reader"] +pub type R = crate::R; +#[doc = "Register `IER` writer"] +pub type W = crate::W; +#[doc = "RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rbrie { + #[doc = "0: Disable the RDA interrupt."] + DisableTheRdaInte = 0, + #[doc = "1: Enable the RDA interrupt."] + EnableTheRdaInter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rbrie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RBRIE` reader - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt."] +pub type RbrieR = crate::BitReader; +impl RbrieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rbrie { + match self.bits { + false => Rbrie::DisableTheRdaInte, + true => Rbrie::EnableTheRdaInter, + } + } + #[doc = "Disable the RDA interrupt."] + #[inline(always)] + pub fn is_disable_the_rda_inte(&self) -> bool { + *self == Rbrie::DisableTheRdaInte + } + #[doc = "Enable the RDA interrupt."] + #[inline(always)] + pub fn is_enable_the_rda_inter(&self) -> bool { + *self == Rbrie::EnableTheRdaInter + } +} +#[doc = "Field `RBRIE` writer - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt."] +pub type RbrieW<'a, REG> = crate::BitWriter<'a, REG, Rbrie>; +impl<'a, REG> RbrieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable the RDA interrupt."] + #[inline(always)] + pub fn disable_the_rda_inte(self) -> &'a mut crate::W { + self.variant(Rbrie::DisableTheRdaInte) + } + #[doc = "Enable the RDA interrupt."] + #[inline(always)] + pub fn enable_the_rda_inter(self) -> &'a mut crate::W { + self.variant(Rbrie::EnableTheRdaInter) + } +} +#[doc = "THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR\\[5\\].\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Threie { + #[doc = "0: Disable the THRE interrupt."] + DisableTheThreInt = 0, + #[doc = "1: Enable the THRE interrupt."] + EnableTheThreInte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Threie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `THREIE` reader - THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR\\[5\\]."] +pub type ThreieR = crate::BitReader; +impl ThreieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Threie { + match self.bits { + false => Threie::DisableTheThreInt, + true => Threie::EnableTheThreInte, + } + } + #[doc = "Disable the THRE interrupt."] + #[inline(always)] + pub fn is_disable_the_thre_int(&self) -> bool { + *self == Threie::DisableTheThreInt + } + #[doc = "Enable the THRE interrupt."] + #[inline(always)] + pub fn is_enable_the_thre_inte(&self) -> bool { + *self == Threie::EnableTheThreInte + } +} +#[doc = "Field `THREIE` writer - THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR\\[5\\]."] +pub type ThreieW<'a, REG> = crate::BitWriter<'a, REG, Threie>; +impl<'a, REG> ThreieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable the THRE interrupt."] + #[inline(always)] + pub fn disable_the_thre_int(self) -> &'a mut crate::W { + self.variant(Threie::DisableTheThreInt) + } + #[doc = "Enable the THRE interrupt."] + #[inline(always)] + pub fn enable_the_thre_inte(self) -> &'a mut crate::W { + self.variant(Threie::EnableTheThreInte) + } +} +#[doc = "RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\].\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxlie { + #[doc = "0: Disable the RX line status interrupts."] + DisableTheRxLine_ = 0, + #[doc = "1: Enable the RX line status interrupts."] + EnableTheRxLineS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxlie) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXLIE` reader - RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."] +pub type RxlieR = crate::BitReader; +impl RxlieR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxlie { + match self.bits { + false => Rxlie::DisableTheRxLine_, + true => Rxlie::EnableTheRxLineS, + } + } + #[doc = "Disable the RX line status interrupts."] + #[inline(always)] + pub fn is_disable_the_rx_line_(&self) -> bool { + *self == Rxlie::DisableTheRxLine_ + } + #[doc = "Enable the RX line status interrupts."] + #[inline(always)] + pub fn is_enable_the_rx_line_s(&self) -> bool { + *self == Rxlie::EnableTheRxLineS + } +} +#[doc = "Field `RXLIE` writer - RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."] +pub type RxlieW<'a, REG> = crate::BitWriter<'a, REG, Rxlie>; +impl<'a, REG> RxlieW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable the RX line status interrupts."] + #[inline(always)] + pub fn disable_the_rx_line_(self) -> &'a mut crate::W { + self.variant(Rxlie::DisableTheRxLine_) + } + #[doc = "Enable the RX line status interrupts."] + #[inline(always)] + pub fn enable_the_rx_line_s(self) -> &'a mut crate::W { + self.variant(Rxlie::EnableTheRxLineS) + } +} +#[doc = "Enables the end of auto-baud interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abeointen { + #[doc = "0: Disable end of auto-baud Interrupt."] + DisableEndOfAuto_ = 0, + #[doc = "1: Enable end of auto-baud Interrupt."] + EnableEndOfAutoB = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abeointen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABEOINTEN` reader - Enables the end of auto-baud interrupt."] +pub type AbeointenR = crate::BitReader; +impl AbeointenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abeointen { + match self.bits { + false => Abeointen::DisableEndOfAuto_, + true => Abeointen::EnableEndOfAutoB, + } + } + #[doc = "Disable end of auto-baud Interrupt."] + #[inline(always)] + pub fn is_disable_end_of_auto_(&self) -> bool { + *self == Abeointen::DisableEndOfAuto_ + } + #[doc = "Enable end of auto-baud Interrupt."] + #[inline(always)] + pub fn is_enable_end_of_auto_b(&self) -> bool { + *self == Abeointen::EnableEndOfAutoB + } +} +#[doc = "Field `ABEOINTEN` writer - Enables the end of auto-baud interrupt."] +pub type AbeointenW<'a, REG> = crate::BitWriter<'a, REG, Abeointen>; +impl<'a, REG> AbeointenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable end of auto-baud Interrupt."] + #[inline(always)] + pub fn disable_end_of_auto_(self) -> &'a mut crate::W { + self.variant(Abeointen::DisableEndOfAuto_) + } + #[doc = "Enable end of auto-baud Interrupt."] + #[inline(always)] + pub fn enable_end_of_auto_b(self) -> &'a mut crate::W { + self.variant(Abeointen::EnableEndOfAutoB) + } +} +#[doc = "Enables the auto-baud time-out interrupt.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Abtointen { + #[doc = "0: Disable auto-baud time-out Interrupt."] + DisableAutoBaudTi = 0, + #[doc = "1: Enable auto-baud time-out Interrupt."] + EnableAutoBaudTim = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Abtointen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABTOINTEN` reader - Enables the auto-baud time-out interrupt."] +pub type AbtointenR = crate::BitReader; +impl AbtointenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Abtointen { + match self.bits { + false => Abtointen::DisableAutoBaudTi, + true => Abtointen::EnableAutoBaudTim, + } + } + #[doc = "Disable auto-baud time-out Interrupt."] + #[inline(always)] + pub fn is_disable_auto_baud_ti(&self) -> bool { + *self == Abtointen::DisableAutoBaudTi + } + #[doc = "Enable auto-baud time-out Interrupt."] + #[inline(always)] + pub fn is_enable_auto_baud_tim(&self) -> bool { + *self == Abtointen::EnableAutoBaudTim + } +} +#[doc = "Field `ABTOINTEN` writer - Enables the auto-baud time-out interrupt."] +pub type AbtointenW<'a, REG> = crate::BitWriter<'a, REG, Abtointen>; +impl<'a, REG> AbtointenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable auto-baud time-out Interrupt."] + #[inline(always)] + pub fn disable_auto_baud_ti(self) -> &'a mut crate::W { + self.variant(Abtointen::DisableAutoBaudTi) + } + #[doc = "Enable auto-baud time-out Interrupt."] + #[inline(always)] + pub fn enable_auto_baud_tim(self) -> &'a mut crate::W { + self.variant(Abtointen::EnableAutoBaudTim) + } +} +impl R { + #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt."] + #[inline(always)] + pub fn rbrie(&self) -> RbrieR { + RbrieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR\\[5\\]."] + #[inline(always)] + pub fn threie(&self) -> ThreieR { + ThreieR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."] + #[inline(always)] + pub fn rxlie(&self) -> RxlieR { + RxlieR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Enables the end of auto-baud interrupt."] + #[inline(always)] + pub fn abeointen(&self) -> AbeointenR { + AbeointenR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enables the auto-baud time-out interrupt."] + #[inline(always)] + pub fn abtointen(&self) -> AbtointenR { + AbtointenR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt."] + #[inline(always)] + #[must_use] + pub fn rbrie(&mut self) -> RbrieW { + RbrieW::new(self, 0) + } + #[doc = "Bit 1 - THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR\\[5\\]."] + #[inline(always)] + #[must_use] + pub fn threie(&mut self) -> ThreieW { + ThreieW::new(self, 1) + } + #[doc = "Bit 2 - RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR\\[4:1\\]."] + #[inline(always)] + #[must_use] + pub fn rxlie(&mut self) -> RxlieW { + RxlieW::new(self, 2) + } + #[doc = "Bit 8 - Enables the end of auto-baud interrupt."] + #[inline(always)] + #[must_use] + pub fn abeointen(&mut self) -> AbeointenW { + AbeointenW::new(self, 8) + } + #[doc = "Bit 9 - Enables the auto-baud time-out interrupt."] + #[inline(always)] + #[must_use] + pub fn abtointen(&mut self) -> AbtointenW { + AbtointenW::new(self, 9) + } +} +#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IerSpec; +impl crate::RegisterSpec for IerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ier::R`](R) reader structure"] +impl crate::Readable for IerSpec {} +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] +impl crate::Writable for IerSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IER to value 0"] +impl crate::Resettable for IerSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/iir.rs b/rust-embedded/lpc111x-pac/src/uart/iir.rs new file mode 100644 index 0000000..0038dbc --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/iir.rs @@ -0,0 +1,156 @@ +#[doc = "Register `IIR` reader"] +pub type R = crate::R; +#[doc = "Interrupt status. Note that IIR\\[0\\] +is active low. The pending interrupt can be determined by evaluating IIR\\[3:1\\].\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Intstatus { + #[doc = "0: At least one interrupt is pending."] + Pending = 0, + #[doc = "1: No interrupt is pending."] + NoInterruptIsPend = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Intstatus) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `INTSTATUS` reader - Interrupt status. Note that IIR\\[0\\] +is active low. The pending interrupt can be determined by evaluating IIR\\[3:1\\]."] +pub type IntstatusR = crate::BitReader; +impl IntstatusR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Intstatus { + match self.bits { + false => Intstatus::Pending, + true => Intstatus::NoInterruptIsPend, + } + } + #[doc = "At least one interrupt is pending."] + #[inline(always)] + pub fn is_pending(&self) -> bool { + *self == Intstatus::Pending + } + #[doc = "No interrupt is pending."] + #[inline(always)] + pub fn is_no_interrupt_is_pend(&self) -> bool { + *self == Intstatus::NoInterruptIsPend + } +} +#[doc = "Interrupt identification. IER\\[3:1\\] +identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER\\[3:1\\] +not listed below are reserved (100,101,111).\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Intid { + #[doc = "3: 1 - Receive Line Status (RLS)."] + _1ReceiveLineS = 3, + #[doc = "2: 2a - Receive Data Available (RDA)."] + _2a_ReceiveDataAv = 2, + #[doc = "6: 2b - Character Time-out Indicator (CTI)."] + _2b_CharacterTime_ = 6, + #[doc = "1: 3 - THRE Interrupt."] + _3ThreInterrupt = 1, + #[doc = "0: 4 - Modem interrupt."] + _4ModemInterrup = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Intid) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Intid { + type Ux = u8; +} +#[doc = "Field `INTID` reader - Interrupt identification. IER\\[3:1\\] +identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER\\[3:1\\] +not listed below are reserved (100,101,111)."] +pub type IntidR = crate::FieldReader; +impl IntidR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 3 => Some(Intid::_1ReceiveLineS), + 2 => Some(Intid::_2a_ReceiveDataAv), + 6 => Some(Intid::_2b_CharacterTime_), + 1 => Some(Intid::_3ThreInterrupt), + 0 => Some(Intid::_4ModemInterrup), + _ => None, + } + } + #[doc = "1 - Receive Line Status (RLS)."] + #[inline(always)] + pub fn is_1_receive_line_s(&self) -> bool { + *self == Intid::_1ReceiveLineS + } + #[doc = "2a - Receive Data Available (RDA)."] + #[inline(always)] + pub fn is_2a__receive_data_av(&self) -> bool { + *self == Intid::_2a_ReceiveDataAv + } + #[doc = "2b - Character Time-out Indicator (CTI)."] + #[inline(always)] + pub fn is_2b__character_time_(&self) -> bool { + *self == Intid::_2b_CharacterTime_ + } + #[doc = "3 - THRE Interrupt."] + #[inline(always)] + pub fn is_3_thre_interrupt(&self) -> bool { + *self == Intid::_3ThreInterrupt + } + #[doc = "4 - Modem interrupt."] + #[inline(always)] + pub fn is_4_modem_interrup(&self) -> bool { + *self == Intid::_4ModemInterrup + } +} +#[doc = "Field `FIFOENABLE` reader - These bits are equivalent to FCR\\[0\\]."] +pub type FifoenableR = crate::FieldReader; +#[doc = "Field `ABEOINT` reader - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."] +pub type AbeointR = crate::BitReader; +#[doc = "Field `ABTOINT` reader - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."] +pub type AbtointR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Interrupt status. Note that IIR\\[0\\] +is active low. The pending interrupt can be determined by evaluating IIR\\[3:1\\]."] + #[inline(always)] + pub fn intstatus(&self) -> IntstatusR { + IntstatusR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Interrupt identification. IER\\[3:1\\] +identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER\\[3:1\\] +not listed below are reserved (100,101,111)."] + #[inline(always)] + pub fn intid(&self) -> IntidR { + IntidR::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bits 6:7 - These bits are equivalent to FCR\\[0\\]."] + #[inline(always)] + pub fn fifoenable(&self) -> FifoenableR { + FifoenableR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled."] + #[inline(always)] + pub fn abeoint(&self) -> AbeointR { + AbeointR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled."] + #[inline(always)] + pub fn abtoint(&self) -> AbtointR { + AbtointR::new(((self.bits >> 9) & 1) != 0) + } +} +#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IirSpec; +impl crate::RegisterSpec for IirSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`iir::R`](R) reader structure"] +impl crate::Readable for IirSpec {} +#[doc = "`reset()` method sets IIR to value 0x01"] +impl crate::Resettable for IirSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/lcr.rs b/rust-embedded/lpc111x-pac/src/uart/lcr.rs new file mode 100644 index 0000000..41f82ff --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/lcr.rs @@ -0,0 +1,476 @@ +#[doc = "Register `LCR` reader"] +pub type R = crate::R; +#[doc = "Register `LCR` writer"] +pub type W = crate::W; +#[doc = "Word Length Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Wls { + #[doc = "0: 5-bit character length."] + _5BitCharacterLeng = 0, + #[doc = "1: 6-bit character length."] + _6BitCharacterLeng = 1, + #[doc = "2: 7-bit character length."] + _7BitCharacterLeng = 2, + #[doc = "3: 8-bit character length."] + _8BitCharacterLeng = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Wls) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Wls { + type Ux = u8; +} +#[doc = "Field `WLS` reader - Word Length Select"] +pub type WlsR = crate::FieldReader; +impl WlsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wls { + match self.bits { + 0 => Wls::_5BitCharacterLeng, + 1 => Wls::_6BitCharacterLeng, + 2 => Wls::_7BitCharacterLeng, + 3 => Wls::_8BitCharacterLeng, + _ => unreachable!(), + } + } + #[doc = "5-bit character length."] + #[inline(always)] + pub fn is_5_bit_character_leng(&self) -> bool { + *self == Wls::_5BitCharacterLeng + } + #[doc = "6-bit character length."] + #[inline(always)] + pub fn is_6_bit_character_leng(&self) -> bool { + *self == Wls::_6BitCharacterLeng + } + #[doc = "7-bit character length."] + #[inline(always)] + pub fn is_7_bit_character_leng(&self) -> bool { + *self == Wls::_7BitCharacterLeng + } + #[doc = "8-bit character length."] + #[inline(always)] + pub fn is_8_bit_character_leng(&self) -> bool { + *self == Wls::_8BitCharacterLeng + } +} +#[doc = "Field `WLS` writer - Word Length Select"] +pub type WlsW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Wls>; +impl<'a, REG> WlsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "5-bit character length."] + #[inline(always)] + pub fn _5_bit_character_leng(self) -> &'a mut crate::W { + self.variant(Wls::_5BitCharacterLeng) + } + #[doc = "6-bit character length."] + #[inline(always)] + pub fn _6_bit_character_leng(self) -> &'a mut crate::W { + self.variant(Wls::_6BitCharacterLeng) + } + #[doc = "7-bit character length."] + #[inline(always)] + pub fn _7_bit_character_leng(self) -> &'a mut crate::W { + self.variant(Wls::_7BitCharacterLeng) + } + #[doc = "8-bit character length."] + #[inline(always)] + pub fn _8_bit_character_leng(self) -> &'a mut crate::W { + self.variant(Wls::_8BitCharacterLeng) + } +} +#[doc = "Stop Bit Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sbs { + #[doc = "0: 1 stop bit."] + _1StopBit_ = 0, + #[doc = "1: 2 stop bits (1.5 if LCR\\[1:0\\]=00)."] + _2StopBits = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sbs) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SBS` reader - Stop Bit Select"] +pub type SbsR = crate::BitReader; +impl SbsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sbs { + match self.bits { + false => Sbs::_1StopBit_, + true => Sbs::_2StopBits, + } + } + #[doc = "1 stop bit."] + #[inline(always)] + pub fn is_1_stop_bit_(&self) -> bool { + *self == Sbs::_1StopBit_ + } + #[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."] + #[inline(always)] + pub fn is_2_stop_bits(&self) -> bool { + *self == Sbs::_2StopBits + } +} +#[doc = "Field `SBS` writer - Stop Bit Select"] +pub type SbsW<'a, REG> = crate::BitWriter<'a, REG, Sbs>; +impl<'a, REG> SbsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "1 stop bit."] + #[inline(always)] + pub fn _1_stop_bit_(self) -> &'a mut crate::W { + self.variant(Sbs::_1StopBit_) + } + #[doc = "2 stop bits (1.5 if LCR\\[1:0\\]=00)."] + #[inline(always)] + pub fn _2_stop_bits(self) -> &'a mut crate::W { + self.variant(Sbs::_2StopBits) + } +} +#[doc = "Parity Enable\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Disable parity generation and checking."] + DisableParityGener = 0, + #[doc = "1: Enable parity generation and checking."] + EnableParityGenera = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Parity Enable"] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::DisableParityGener, + true => Pe::EnableParityGenera, + } + } + #[doc = "Disable parity generation and checking."] + #[inline(always)] + pub fn is_disable_parity_gener(&self) -> bool { + *self == Pe::DisableParityGener + } + #[doc = "Enable parity generation and checking."] + #[inline(always)] + pub fn is_enable_parity_genera(&self) -> bool { + *self == Pe::EnableParityGenera + } +} +#[doc = "Field `PE` writer - Parity Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG, Pe>; +impl<'a, REG> PeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable parity generation and checking."] + #[inline(always)] + pub fn disable_parity_gener(self) -> &'a mut crate::W { + self.variant(Pe::DisableParityGener) + } + #[doc = "Enable parity generation and checking."] + #[inline(always)] + pub fn enable_parity_genera(self) -> &'a mut crate::W { + self.variant(Pe::EnableParityGenera) + } +} +#[doc = "Parity Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Ps { + #[doc = "0: Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."] + OddParityNumberO = 0, + #[doc = "1: Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."] + EvenParityNumber_ = 1, + #[doc = "2: Forced 1 stick parity."] + Forced1StickParit = 2, + #[doc = "3: Forced 0 stick parity."] + Forced0StickParit = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Ps) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Ps { + type Ux = u8; +} +#[doc = "Field `PS` reader - Parity Select"] +pub type PsR = crate::FieldReader; +impl PsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ps { + match self.bits { + 0 => Ps::OddParityNumberO, + 1 => Ps::EvenParityNumber_, + 2 => Ps::Forced1StickParit, + 3 => Ps::Forced0StickParit, + _ => unreachable!(), + } + } + #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."] + #[inline(always)] + pub fn is_odd_parity_number_o(&self) -> bool { + *self == Ps::OddParityNumberO + } + #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."] + #[inline(always)] + pub fn is_even_parity_number_(&self) -> bool { + *self == Ps::EvenParityNumber_ + } + #[doc = "Forced 1 stick parity."] + #[inline(always)] + pub fn is_forced_1_stick_parit(&self) -> bool { + *self == Ps::Forced1StickParit + } + #[doc = "Forced 0 stick parity."] + #[inline(always)] + pub fn is_forced_0_stick_parit(&self) -> bool { + *self == Ps::Forced0StickParit + } +} +#[doc = "Field `PS` writer - Parity Select"] +pub type PsW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ps>; +impl<'a, REG> PsW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd."] + #[inline(always)] + pub fn odd_parity_number_o(self) -> &'a mut crate::W { + self.variant(Ps::OddParityNumberO) + } + #[doc = "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even."] + #[inline(always)] + pub fn even_parity_number_(self) -> &'a mut crate::W { + self.variant(Ps::EvenParityNumber_) + } + #[doc = "Forced 1 stick parity."] + #[inline(always)] + pub fn forced_1_stick_parit(self) -> &'a mut crate::W { + self.variant(Ps::Forced1StickParit) + } + #[doc = "Forced 0 stick parity."] + #[inline(always)] + pub fn forced_0_stick_parit(self) -> &'a mut crate::W { + self.variant(Ps::Forced0StickParit) + } +} +#[doc = "Break Control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bc { + #[doc = "0: Disable break transmission."] + DisableBreakTransm = 0, + #[doc = "1: Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR\\[6\\] +is active high."] + EnableBreakTransmi = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bc) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BC` reader - Break Control"] +pub type BcR = crate::BitReader; +impl BcR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bc { + match self.bits { + false => Bc::DisableBreakTransm, + true => Bc::EnableBreakTransmi, + } + } + #[doc = "Disable break transmission."] + #[inline(always)] + pub fn is_disable_break_transm(&self) -> bool { + *self == Bc::DisableBreakTransm + } + #[doc = "Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR\\[6\\] +is active high."] + #[inline(always)] + pub fn is_enable_break_transmi(&self) -> bool { + *self == Bc::EnableBreakTransmi + } +} +#[doc = "Field `BC` writer - Break Control"] +pub type BcW<'a, REG> = crate::BitWriter<'a, REG, Bc>; +impl<'a, REG> BcW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable break transmission."] + #[inline(always)] + pub fn disable_break_transm(self) -> &'a mut crate::W { + self.variant(Bc::DisableBreakTransm) + } + #[doc = "Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR\\[6\\] +is active high."] + #[inline(always)] + pub fn enable_break_transmi(self) -> &'a mut crate::W { + self.variant(Bc::EnableBreakTransmi) + } +} +#[doc = "Divisor Latch Access Bit\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dlab { + #[doc = "0: Disable access to Divisor Latches."] + DisableAccessToDi = 0, + #[doc = "1: Enable access to Divisor Latches."] + EnableAccessToDiv = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dlab) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DLAB` reader - Divisor Latch Access Bit"] +pub type DlabR = crate::BitReader; +impl DlabR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dlab { + match self.bits { + false => Dlab::DisableAccessToDi, + true => Dlab::EnableAccessToDiv, + } + } + #[doc = "Disable access to Divisor Latches."] + #[inline(always)] + pub fn is_disable_access_to_di(&self) -> bool { + *self == Dlab::DisableAccessToDi + } + #[doc = "Enable access to Divisor Latches."] + #[inline(always)] + pub fn is_enable_access_to_div(&self) -> bool { + *self == Dlab::EnableAccessToDiv + } +} +#[doc = "Field `DLAB` writer - Divisor Latch Access Bit"] +pub type DlabW<'a, REG> = crate::BitWriter<'a, REG, Dlab>; +impl<'a, REG> DlabW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable access to Divisor Latches."] + #[inline(always)] + pub fn disable_access_to_di(self) -> &'a mut crate::W { + self.variant(Dlab::DisableAccessToDi) + } + #[doc = "Enable access to Divisor Latches."] + #[inline(always)] + pub fn enable_access_to_div(self) -> &'a mut crate::W { + self.variant(Dlab::EnableAccessToDiv) + } +} +impl R { + #[doc = "Bits 0:1 - Word Length Select"] + #[inline(always)] + pub fn wls(&self) -> WlsR { + WlsR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Stop Bit Select"] + #[inline(always)] + pub fn sbs(&self) -> SbsR { + SbsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Parity Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Parity Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Break Control"] + #[inline(always)] + pub fn bc(&self) -> BcR { + BcR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Divisor Latch Access Bit"] + #[inline(always)] + pub fn dlab(&self) -> DlabR { + DlabR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Word Length Select"] + #[inline(always)] + #[must_use] + pub fn wls(&mut self) -> WlsW { + WlsW::new(self, 0) + } + #[doc = "Bit 2 - Stop Bit Select"] + #[inline(always)] + #[must_use] + pub fn sbs(&mut self) -> SbsW { + SbsW::new(self, 2) + } + #[doc = "Bit 3 - Parity Enable"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 3) + } + #[doc = "Bits 4:5 - Parity Select"] + #[inline(always)] + #[must_use] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 4) + } + #[doc = "Bit 6 - Break Control"] + #[inline(always)] + #[must_use] + pub fn bc(&mut self) -> BcW { + BcW::new(self, 6) + } + #[doc = "Bit 7 - Divisor Latch Access Bit"] + #[inline(always)] + #[must_use] + pub fn dlab(&mut self) -> DlabW { + DlabW::new(self, 7) + } +} +#[doc = "Line Control Register. Contains controls for frame formatting and break generation.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LcrSpec; +impl crate::RegisterSpec for LcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lcr::R`](R) reader structure"] +impl crate::Readable for LcrSpec {} +#[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"] +impl crate::Writable for LcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LCR to value 0"] +impl crate::Resettable for LcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/lsr.rs b/rust-embedded/lpc111x-pac/src/uart/lsr.rs new file mode 100644 index 0000000..63340ec --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/lsr.rs @@ -0,0 +1,352 @@ +#[doc = "Register `LSR` reader"] +pub type R = crate::R; +#[doc = "Receiver Data Ready. LSR\\[0\\] +is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rdr { + #[doc = "0: RBR is empty."] + Empty_ = 0, + #[doc = "1: RBR contains valid data."] + Valid = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rdr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDR` reader - Receiver Data Ready. LSR\\[0\\] +is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty."] +pub type RdrR = crate::BitReader; +impl RdrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rdr { + match self.bits { + false => Rdr::Empty_, + true => Rdr::Valid, + } + } + #[doc = "RBR is empty."] + #[inline(always)] + pub fn is_empty_(&self) -> bool { + *self == Rdr::Empty_ + } + #[doc = "RBR contains valid data."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Rdr::Valid + } +} +#[doc = "Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR\\[1\\]. LSR\\[1\\] +is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oe { + #[doc = "0: Overrun error status is inactive."] + Inactive = 0, + #[doc = "1: Overrun error status is active."] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OE` reader - Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR\\[1\\]. LSR\\[1\\] +is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost."] +pub type OeR = crate::BitReader; +impl OeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oe { + match self.bits { + false => Oe::Inactive, + true => Oe::Active, + } + } + #[doc = "Overrun error status is inactive."] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == Oe::Inactive + } + #[doc = "Overrun error status is active."] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Oe::Active + } +} +#[doc = "Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR\\[2\\]. Time of parity error detection is dependent on FCR\\[0\\]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Pe { + #[doc = "0: Parity error status is inactive."] + Inactive = 0, + #[doc = "1: Parity error status is active."] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Pe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PE` reader - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR\\[2\\]. Time of parity error detection is dependent on FCR\\[0\\]. Note: A parity error is associated with the character at the top of the UART RBR FIFO."] +pub type PeR = crate::BitReader; +impl PeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Pe { + match self.bits { + false => Pe::Inactive, + true => Pe::Active, + } + } + #[doc = "Parity error status is inactive."] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == Pe::Inactive + } + #[doc = "Parity error status is active."] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Pe::Active + } +} +#[doc = "Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR\\[3\\]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Fe { + #[doc = "0: Framing error status is inactive."] + Inactive = 0, + #[doc = "1: Framing error status is active."] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Fe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FE` reader - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR\\[3\\]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO."] +pub type FeR = crate::BitReader; +impl FeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Fe { + match self.bits { + false => Fe::Inactive, + true => Fe::Active, + } + } + #[doc = "Framing error status is inactive."] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == Fe::Inactive + } + #[doc = "Framing error status is active."] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Fe::Active + } +} +#[doc = "Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR\\[0\\]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Bi { + #[doc = "0: Break interrupt status is inactive."] + Inactive = 0, + #[doc = "1: Break interrupt status is active."] + Active = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Bi) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `BI` reader - Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR\\[0\\]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO."] +pub type BiR = crate::BitReader; +impl BiR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Bi { + match self.bits { + false => Bi::Inactive, + true => Bi::Active, + } + } + #[doc = "Break interrupt status is inactive."] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == Bi::Inactive + } + #[doc = "Break interrupt status is active."] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == Bi::Active + } +} +#[doc = "Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Thre { + #[doc = "0: THR contains valid data."] + Valid = 0, + #[doc = "1: THR is empty."] + Empty_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Thre) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `THRE` reader - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write."] +pub type ThreR = crate::BitReader; +impl ThreR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Thre { + match self.bits { + false => Thre::Valid, + true => Thre::Empty_, + } + } + #[doc = "THR contains valid data."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Thre::Valid + } + #[doc = "THR is empty."] + #[inline(always)] + pub fn is_empty_(&self) -> bool { + *self == Thre::Empty_ + } +} +#[doc = "Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Temt { + #[doc = "0: THR and/or the TSR contains valid data."] + Valid = 0, + #[doc = "1: THR and the TSR are empty."] + Empty_ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Temt) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TEMT` reader - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."] +pub type TemtR = crate::BitReader; +impl TemtR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Temt { + match self.bits { + false => Temt::Valid, + true => Temt::Empty_, + } + } + #[doc = "THR and/or the TSR contains valid data."] + #[inline(always)] + pub fn is_valid(&self) -> bool { + *self == Temt::Valid + } + #[doc = "THR and the TSR are empty."] + #[inline(always)] + pub fn is_empty_(&self) -> bool { + *self == Temt::Empty_ + } +} +#[doc = "Error in RX FIFO. LSR\\[7\\] +is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxfe { + #[doc = "0: RBR contains no UART RX errors or FCR\\[0\\]=0."] + Noerror = 0, + #[doc = "1: UART RBR contains at least one UART RX error."] + Error = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxfe) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXFE` reader - Error in RX FIFO. LSR\\[7\\] +is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO."] +pub type RxfeR = crate::BitReader; +impl RxfeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxfe { + match self.bits { + false => Rxfe::Noerror, + true => Rxfe::Error, + } + } + #[doc = "RBR contains no UART RX errors or FCR\\[0\\]=0."] + #[inline(always)] + pub fn is_noerror(&self) -> bool { + *self == Rxfe::Noerror + } + #[doc = "UART RBR contains at least one UART RX error."] + #[inline(always)] + pub fn is_error(&self) -> bool { + *self == Rxfe::Error + } +} +impl R { + #[doc = "Bit 0 - Receiver Data Ready. LSR\\[0\\] +is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty."] + #[inline(always)] + pub fn rdr(&self) -> RdrR { + RdrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR\\[1\\]. LSR\\[1\\] +is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost."] + #[inline(always)] + pub fn oe(&self) -> OeR { + OeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR\\[2\\]. Time of parity error detection is dependent on FCR\\[0\\]. Note: A parity error is associated with the character at the top of the UART RBR FIFO."] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR\\[3\\]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO."] + #[inline(always)] + pub fn fe(&self) -> FeR { + FeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR\\[0\\]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO."] + #[inline(always)] + pub fn bi(&self) -> BiR { + BiR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write."] + #[inline(always)] + pub fn thre(&self) -> ThreR { + ThreR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data."] + #[inline(always)] + pub fn temt(&self) -> TemtR { + TemtR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Error in RX FIFO. LSR\\[7\\] +is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO."] + #[inline(always)] + pub fn rxfe(&self) -> RxfeR { + RxfeR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R). WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LsrSpec; +impl crate::RegisterSpec for LsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`lsr::R`](R) reader structure"] +impl crate::Readable for LsrSpec {} +#[doc = "`reset()` method sets LSR to value 0x60"] +impl crate::Resettable for LsrSpec { + const RESET_VALUE: u32 = 0x60; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/mcr.rs b/rust-embedded/lpc111x-pac/src/uart/mcr.rs new file mode 100644 index 0000000..e96c057 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/mcr.rs @@ -0,0 +1,198 @@ +#[doc = "Register `MCR` reader"] +pub type R = crate::R; +#[doc = "Register `MCR` writer"] +pub type W = crate::W; +#[doc = "Field `DTRC` reader - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."] +pub type DtrcR = crate::BitReader; +#[doc = "Field `DTRC` writer - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."] +pub type DtrcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTSC` reader - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."] +pub type RtscR = crate::BitReader; +#[doc = "Field `RTSC` writer - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."] +pub type RtscW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LMS` reader - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."] +pub type LmsR = crate::BitReader; +#[doc = "Field `LMS` writer - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."] +pub type LmsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "RTS flow control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rtsen { + #[doc = "0: Disable auto-rts flow control."] + DisableAutoRtsFlo = 0, + #[doc = "1: Enable auto-rts flow control."] + EnableAutoRtsFlow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rtsen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RTSEN` reader - RTS flow control"] +pub type RtsenR = crate::BitReader; +impl RtsenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rtsen { + match self.bits { + false => Rtsen::DisableAutoRtsFlo, + true => Rtsen::EnableAutoRtsFlow, + } + } + #[doc = "Disable auto-rts flow control."] + #[inline(always)] + pub fn is_disable_auto_rts_flo(&self) -> bool { + *self == Rtsen::DisableAutoRtsFlo + } + #[doc = "Enable auto-rts flow control."] + #[inline(always)] + pub fn is_enable_auto_rts_flow(&self) -> bool { + *self == Rtsen::EnableAutoRtsFlow + } +} +#[doc = "Field `RTSEN` writer - RTS flow control"] +pub type RtsenW<'a, REG> = crate::BitWriter<'a, REG, Rtsen>; +impl<'a, REG> RtsenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable auto-rts flow control."] + #[inline(always)] + pub fn disable_auto_rts_flo(self) -> &'a mut crate::W { + self.variant(Rtsen::DisableAutoRtsFlo) + } + #[doc = "Enable auto-rts flow control."] + #[inline(always)] + pub fn enable_auto_rts_flow(self) -> &'a mut crate::W { + self.variant(Rtsen::EnableAutoRtsFlow) + } +} +#[doc = "CTS flow control\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ctsen { + #[doc = "0: Disable auto-cts flow control."] + DisableAutoCtsFlo = 0, + #[doc = "1: Enable auto-cts flow control."] + EnableAutoCtsFlow = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ctsen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CTSEN` reader - CTS flow control"] +pub type CtsenR = crate::BitReader; +impl CtsenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ctsen { + match self.bits { + false => Ctsen::DisableAutoCtsFlo, + true => Ctsen::EnableAutoCtsFlow, + } + } + #[doc = "Disable auto-cts flow control."] + #[inline(always)] + pub fn is_disable_auto_cts_flo(&self) -> bool { + *self == Ctsen::DisableAutoCtsFlo + } + #[doc = "Enable auto-cts flow control."] + #[inline(always)] + pub fn is_enable_auto_cts_flow(&self) -> bool { + *self == Ctsen::EnableAutoCtsFlow + } +} +#[doc = "Field `CTSEN` writer - CTS flow control"] +pub type CtsenW<'a, REG> = crate::BitWriter<'a, REG, Ctsen>; +impl<'a, REG> CtsenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable auto-cts flow control."] + #[inline(always)] + pub fn disable_auto_cts_flo(self) -> &'a mut crate::W { + self.variant(Ctsen::DisableAutoCtsFlo) + } + #[doc = "Enable auto-cts flow control."] + #[inline(always)] + pub fn enable_auto_cts_flow(self) -> &'a mut crate::W { + self.variant(Ctsen::EnableAutoCtsFlow) + } +} +impl R { + #[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."] + #[inline(always)] + pub fn dtrc(&self) -> DtrcR { + DtrcR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."] + #[inline(always)] + pub fn rtsc(&self) -> RtscR { + RtscR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."] + #[inline(always)] + pub fn lms(&self) -> LmsR { + LmsR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - RTS flow control"] + #[inline(always)] + pub fn rtsen(&self) -> RtsenR { + RtsenR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - CTS flow control"] + #[inline(always)] + pub fn ctsen(&self) -> CtsenR { + CtsenR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active."] + #[inline(always)] + #[must_use] + pub fn dtrc(&mut self) -> DtrcW { + DtrcW::new(self, 0) + } + #[doc = "Bit 1 - RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active."] + #[inline(always)] + #[must_use] + pub fn rtsc(&mut self) -> RtscW { + RtscW::new(self, 1) + } + #[doc = "Bit 4 - Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR."] + #[inline(always)] + #[must_use] + pub fn lms(&mut self) -> LmsW { + LmsW::new(self, 4) + } + #[doc = "Bit 6 - RTS flow control"] + #[inline(always)] + #[must_use] + pub fn rtsen(&mut self) -> RtsenW { + RtsenW::new(self, 6) + } + #[doc = "Bit 7 - CTS flow control"] + #[inline(always)] + #[must_use] + pub fn ctsen(&mut self) -> CtsenW { + CtsenW::new(self, 7) + } +} +#[doc = "Modem control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct McrSpec; +impl crate::RegisterSpec for McrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mcr::R`](R) reader structure"] +impl crate::Readable for McrSpec {} +#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"] +impl crate::Writable for McrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MCR to value 0"] +impl crate::Resettable for McrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/msr.rs b/rust-embedded/lpc111x-pac/src/uart/msr.rs new file mode 100644 index 0000000..ee473d8 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/msr.rs @@ -0,0 +1,215 @@ +#[doc = "Register `MSR` reader"] +pub type R = crate::R; +#[doc = "Delta CTS. Set upon state change of input CTS. Cleared on a MSR read.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dcts { + #[doc = "0: No change detected on modem input CTS."] + NoChangeDetectedO = 0, + #[doc = "1: State change detected on modem input CTS."] + StateChangeDetecte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dcts) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DCTS` reader - Delta CTS. Set upon state change of input CTS. Cleared on a MSR read."] +pub type DctsR = crate::BitReader; +impl DctsR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dcts { + match self.bits { + false => Dcts::NoChangeDetectedO, + true => Dcts::StateChangeDetecte, + } + } + #[doc = "No change detected on modem input CTS."] + #[inline(always)] + pub fn is_no_change_detected_o(&self) -> bool { + *self == Dcts::NoChangeDetectedO + } + #[doc = "State change detected on modem input CTS."] + #[inline(always)] + pub fn is_state_change_detecte(&self) -> bool { + *self == Dcts::StateChangeDetecte + } +} +#[doc = "Delta DSR. Set upon state change of input DSR. Cleared on a MSR read.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ddsr { + #[doc = "0: No change detected on modem input DSR."] + NoChangeDetectedO = 0, + #[doc = "1: State change detected on modem input DSR."] + StateChangeDetecte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ddsr) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DDSR` reader - Delta DSR. Set upon state change of input DSR. Cleared on a MSR read."] +pub type DdsrR = crate::BitReader; +impl DdsrR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ddsr { + match self.bits { + false => Ddsr::NoChangeDetectedO, + true => Ddsr::StateChangeDetecte, + } + } + #[doc = "No change detected on modem input DSR."] + #[inline(always)] + pub fn is_no_change_detected_o(&self) -> bool { + *self == Ddsr::NoChangeDetectedO + } + #[doc = "State change detected on modem input DSR."] + #[inline(always)] + pub fn is_state_change_detecte(&self) -> bool { + *self == Ddsr::StateChangeDetecte + } +} +#[doc = "Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Teri { + #[doc = "0: No change detected on modem input, RI."] + NoChangeDetectedO = 0, + #[doc = "1: Low-to-high transition detected on RI."] + LowToHighTransiti = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Teri) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TERI` reader - Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read."] +pub type TeriR = crate::BitReader; +impl TeriR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Teri { + match self.bits { + false => Teri::NoChangeDetectedO, + true => Teri::LowToHighTransiti, + } + } + #[doc = "No change detected on modem input, RI."] + #[inline(always)] + pub fn is_no_change_detected_o(&self) -> bool { + *self == Teri::NoChangeDetectedO + } + #[doc = "Low-to-high transition detected on RI."] + #[inline(always)] + pub fn is_low_to_high_transiti(&self) -> bool { + *self == Teri::LowToHighTransiti + } +} +#[doc = "Delta DCD. Set upon state change of input DCD. Cleared on a MSR read.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Ddcd { + #[doc = "0: No change detected on modem input DCD."] + NoChangeDetectedO = 0, + #[doc = "1: State change detected on modem input DCD."] + StateChangeDetecte = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Ddcd) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DDCD` reader - Delta DCD. Set upon state change of input DCD. Cleared on a MSR read."] +pub type DdcdR = crate::BitReader; +impl DdcdR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Ddcd { + match self.bits { + false => Ddcd::NoChangeDetectedO, + true => Ddcd::StateChangeDetecte, + } + } + #[doc = "No change detected on modem input DCD."] + #[inline(always)] + pub fn is_no_change_detected_o(&self) -> bool { + *self == Ddcd::NoChangeDetectedO + } + #[doc = "State change detected on modem input DCD."] + #[inline(always)] + pub fn is_state_change_detecte(&self) -> bool { + *self == Ddcd::StateChangeDetecte + } +} +#[doc = "Field `CTS` reader - Clear To Send State. Complement of input signal CTS. This bit is connected to MCR\\[1\\] +in modem loopback mode."] +pub type CtsR = crate::BitReader; +#[doc = "Field `DSR` reader - Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR\\[0\\] +in modem loopback mode."] +pub type DsrR = crate::BitReader; +#[doc = "Field `RI` reader - Ring Indicator State. Complement of input RI. This bit is connected to MCR\\[2\\] +in modem loopback mode."] +pub type RiR = crate::BitReader; +#[doc = "Field `DCD` reader - Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR\\[3\\] +in modem loopback mode."] +pub type DcdR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Delta CTS. Set upon state change of input CTS. Cleared on a MSR read."] + #[inline(always)] + pub fn dcts(&self) -> DctsR { + DctsR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Delta DSR. Set upon state change of input DSR. Cleared on a MSR read."] + #[inline(always)] + pub fn ddsr(&self) -> DdsrR { + DdsrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read."] + #[inline(always)] + pub fn teri(&self) -> TeriR { + TeriR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Delta DCD. Set upon state change of input DCD. Cleared on a MSR read."] + #[inline(always)] + pub fn ddcd(&self) -> DdcdR { + DdcdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Clear To Send State. Complement of input signal CTS. This bit is connected to MCR\\[1\\] +in modem loopback mode."] + #[inline(always)] + pub fn cts(&self) -> CtsR { + CtsR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR\\[0\\] +in modem loopback mode."] + #[inline(always)] + pub fn dsr(&self) -> DsrR { + DsrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Ring Indicator State. Complement of input RI. This bit is connected to MCR\\[2\\] +in modem loopback mode."] + #[inline(always)] + pub fn ri(&self) -> RiR { + RiR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR\\[3\\] +in modem loopback mode."] + #[inline(always)] + pub fn dcd(&self) -> DcdR { + DcdR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Modem status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R). WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MsrSpec; +impl crate::RegisterSpec for MsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`msr::R`](R) reader structure"] +impl crate::Readable for MsrSpec {} +#[doc = "`reset()` method sets MSR to value 0"] +impl crate::Resettable for MsrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/rbr.rs b/rust-embedded/lpc111x-pac/src/uart/rbr.rs new file mode 100644 index 0000000..31898d4 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/rbr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RBR` reader"] +pub type R = crate::R; +#[doc = "Field `RBR` reader - The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO."] +pub type RbrR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO."] + #[inline(always)] + pub fn rbr(&self) -> RbrR { + RbrR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`](R). WARN: The register is **modified** in some way after a read operation. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RbrSpec; +impl crate::RegisterSpec for RbrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rbr::R`](R) reader structure"] +impl crate::Readable for RbrSpec {} +#[doc = "`reset()` method sets RBR to value 0"] +impl crate::Resettable for RbrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/rs485adrmatch.rs b/rust-embedded/lpc111x-pac/src/uart/rs485adrmatch.rs new file mode 100644 index 0000000..1a0f9ce --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/rs485adrmatch.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RS485ADRMATCH` reader"] +pub type R = crate::R; +#[doc = "Register `RS485ADRMATCH` writer"] +pub type W = crate::W; +#[doc = "Field `ADRMATCH` reader - Contains the address match value."] +pub type AdrmatchR = crate::FieldReader; +#[doc = "Field `ADRMATCH` writer - Contains the address match value."] +pub type AdrmatchW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Contains the address match value."] + #[inline(always)] + pub fn adrmatch(&self) -> AdrmatchR { + AdrmatchR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Contains the address match value."] + #[inline(always)] + #[must_use] + pub fn adrmatch(&mut self) -> AdrmatchW { + AdrmatchW::new(self, 0) + } +} +#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485adrmatch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485adrmatch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rs485adrmatchSpec; +impl crate::RegisterSpec for Rs485adrmatchSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rs485adrmatch::R`](R) reader structure"] +impl crate::Readable for Rs485adrmatchSpec {} +#[doc = "`write(|w| ..)` method takes [`rs485adrmatch::W`](W) writer structure"] +impl crate::Writable for Rs485adrmatchSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RS485ADRMATCH to value 0"] +impl crate::Resettable for Rs485adrmatchSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/rs485ctrl.rs b/rust-embedded/lpc111x-pac/src/uart/rs485ctrl.rs new file mode 100644 index 0000000..706fabd --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/rs485ctrl.rs @@ -0,0 +1,409 @@ +#[doc = "Register `RS485CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `RS485CTRL` writer"] +pub type W = crate::W; +#[doc = "NMM enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Nmmen { + #[doc = "0: RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."] + Disabled = 0, + #[doc = "1: RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Nmmen) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NMMEN` reader - NMM enable."] +pub type NmmenR = crate::BitReader; +impl NmmenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Nmmen { + match self.bits { + false => Nmmen::Disabled, + true => Nmmen::Enabled, + } + } + #[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Nmmen::Disabled + } + #[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Nmmen::Enabled + } +} +#[doc = "Field `NMMEN` writer - NMM enable."] +pub type NmmenW<'a, REG> = crate::BitWriter<'a, REG, Nmmen>; +impl<'a, REG> NmmenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Nmmen::Disabled) + } + #[doc = "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Nmmen::Enabled) + } +} +#[doc = "Receiver enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Rxdis { + #[doc = "0: The receiver is enabled."] + Enabled = 0, + #[doc = "1: The receiver is disabled."] + Disabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Rxdis) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RXDIS` reader - Receiver enable."] +pub type RxdisR = crate::BitReader; +impl RxdisR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Rxdis { + match self.bits { + false => Rxdis::Enabled, + true => Rxdis::Disabled, + } + } + #[doc = "The receiver is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Rxdis::Enabled + } + #[doc = "The receiver is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Rxdis::Disabled + } +} +#[doc = "Field `RXDIS` writer - Receiver enable."] +pub type RxdisW<'a, REG> = crate::BitWriter<'a, REG, Rxdis>; +impl<'a, REG> RxdisW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The receiver is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Rxdis::Enabled) + } + #[doc = "The receiver is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Rxdis::Disabled) + } +} +#[doc = "AAD enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Aaden { + #[doc = "0: Auto Address Detect (AAD) is disabled."] + Disabled = 0, + #[doc = "1: Auto Address Detect (AAD) is enabled."] + Enabled = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Aaden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `AADEN` reader - AAD enable."] +pub type AadenR = crate::BitReader; +impl AadenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Aaden { + match self.bits { + false => Aaden::Disabled, + true => Aaden::Enabled, + } + } + #[doc = "Auto Address Detect (AAD) is disabled."] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == Aaden::Disabled + } + #[doc = "Auto Address Detect (AAD) is enabled."] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == Aaden::Enabled + } +} +#[doc = "Field `AADEN` writer - AAD enable."] +pub type AadenW<'a, REG> = crate::BitWriter<'a, REG, Aaden>; +impl<'a, REG> AadenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Auto Address Detect (AAD) is disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(Aaden::Disabled) + } + #[doc = "Auto Address Detect (AAD) is enabled."] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(Aaden::Enabled) + } +} +#[doc = "Select direction control pin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Sel { + #[doc = "0: If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."] + Rts = 0, + #[doc = "1: If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."] + Dtr = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Sel) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SEL` reader - Select direction control pin"] +pub type SelR = crate::BitReader; +impl SelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Sel { + match self.bits { + false => Sel::Rts, + true => Sel::Dtr, + } + } + #[doc = "If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."] + #[inline(always)] + pub fn is_rts(&self) -> bool { + *self == Sel::Rts + } + #[doc = "If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."] + #[inline(always)] + pub fn is_dtr(&self) -> bool { + *self == Sel::Dtr + } +} +#[doc = "Field `SEL` writer - Select direction control pin"] +pub type SelW<'a, REG> = crate::BitWriter<'a, REG, Sel>; +impl<'a, REG> SelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control."] + #[inline(always)] + pub fn rts(self) -> &'a mut crate::W { + self.variant(Sel::Rts) + } + #[doc = "If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control."] + #[inline(always)] + pub fn dtr(self) -> &'a mut crate::W { + self.variant(Sel::Dtr) + } +} +#[doc = "Auto direction control enable.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Dctrl { + #[doc = "0: Disable Auto Direction Control."] + DisableAutoDirecti = 0, + #[doc = "1: Enable Auto Direction Control."] + EnableAutoDirectio = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Dctrl) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DCTRL` reader - Auto direction control enable."] +pub type DctrlR = crate::BitReader; +impl DctrlR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Dctrl { + match self.bits { + false => Dctrl::DisableAutoDirecti, + true => Dctrl::EnableAutoDirectio, + } + } + #[doc = "Disable Auto Direction Control."] + #[inline(always)] + pub fn is_disable_auto_directi(&self) -> bool { + *self == Dctrl::DisableAutoDirecti + } + #[doc = "Enable Auto Direction Control."] + #[inline(always)] + pub fn is_enable_auto_directio(&self) -> bool { + *self == Dctrl::EnableAutoDirectio + } +} +#[doc = "Field `DCTRL` writer - Auto direction control enable."] +pub type DctrlW<'a, REG> = crate::BitWriter<'a, REG, Dctrl>; +impl<'a, REG> DctrlW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disable Auto Direction Control."] + #[inline(always)] + pub fn disable_auto_directi(self) -> &'a mut crate::W { + self.variant(Dctrl::DisableAutoDirecti) + } + #[doc = "Enable Auto Direction Control."] + #[inline(always)] + pub fn enable_auto_directio(self) -> &'a mut crate::W { + self.variant(Dctrl::EnableAutoDirectio) + } +} +#[doc = "Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Oinv { + #[doc = "0: The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."] + Low = 0, + #[doc = "1: The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."] + High = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Oinv) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `OINV` reader - Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."] +pub type OinvR = crate::BitReader; +impl OinvR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Oinv { + match self.bits { + false => Oinv::Low, + true => Oinv::High, + } + } + #[doc = "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == Oinv::Low + } + #[doc = "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == Oinv::High + } +} +#[doc = "Field `OINV` writer - Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."] +pub type OinvW<'a, REG> = crate::BitWriter<'a, REG, Oinv>; +impl<'a, REG> OinvW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted."] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(Oinv::Low) + } + #[doc = "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted."] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(Oinv::High) + } +} +impl R { + #[doc = "Bit 0 - NMM enable."] + #[inline(always)] + pub fn nmmen(&self) -> NmmenR { + NmmenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receiver enable."] + #[inline(always)] + pub fn rxdis(&self) -> RxdisR { + RxdisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - AAD enable."] + #[inline(always)] + pub fn aaden(&self) -> AadenR { + AadenR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Select direction control pin"] + #[inline(always)] + pub fn sel(&self) -> SelR { + SelR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Auto direction control enable."] + #[inline(always)] + pub fn dctrl(&self) -> DctrlR { + DctrlR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."] + #[inline(always)] + pub fn oinv(&self) -> OinvR { + OinvR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMM enable."] + #[inline(always)] + #[must_use] + pub fn nmmen(&mut self) -> NmmenW { + NmmenW::new(self, 0) + } + #[doc = "Bit 1 - Receiver enable."] + #[inline(always)] + #[must_use] + pub fn rxdis(&mut self) -> RxdisW { + RxdisW::new(self, 1) + } + #[doc = "Bit 2 - AAD enable."] + #[inline(always)] + #[must_use] + pub fn aaden(&mut self) -> AadenW { + AadenW::new(self, 2) + } + #[doc = "Bit 3 - Select direction control pin"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SelW { + SelW::new(self, 3) + } + #[doc = "Bit 4 - Auto direction control enable."] + #[inline(always)] + #[must_use] + pub fn dctrl(&mut self) -> DctrlW { + DctrlW::new(self, 4) + } + #[doc = "Bit 5 - Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin."] + #[inline(always)] + #[must_use] + pub fn oinv(&mut self) -> OinvW { + OinvW::new(self, 5) + } +} +#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rs485ctrlSpec; +impl crate::RegisterSpec for Rs485ctrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rs485ctrl::R`](R) reader structure"] +impl crate::Readable for Rs485ctrlSpec {} +#[doc = "`write(|w| ..)` method takes [`rs485ctrl::W`](W) writer structure"] +impl crate::Writable for Rs485ctrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RS485CTRL to value 0"] +impl crate::Resettable for Rs485ctrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/rs485dly.rs b/rust-embedded/lpc111x-pac/src/uart/rs485dly.rs new file mode 100644 index 0000000..914e9ce --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/rs485dly.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RS485DLY` reader"] +pub type R = crate::R; +#[doc = "Register `RS485DLY` writer"] +pub type W = crate::W; +#[doc = "Field `DLY` reader - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."] +pub type DlyR = crate::FieldReader; +#[doc = "Field `DLY` writer - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."] +pub type DlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."] + #[inline(always)] + pub fn dly(&self) -> DlyR { + DlyR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter."] + #[inline(always)] + #[must_use] + pub fn dly(&mut self) -> DlyW { + DlyW::new(self, 0) + } +} +#[doc = "RS-485/EIA-485 direction control delay.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rs485dly::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rs485dly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rs485dlySpec; +impl crate::RegisterSpec for Rs485dlySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rs485dly::R`](R) reader structure"] +impl crate::Readable for Rs485dlySpec {} +#[doc = "`write(|w| ..)` method takes [`rs485dly::W`](W) writer structure"] +impl crate::Writable for Rs485dlySpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RS485DLY to value 0"] +impl crate::Resettable for Rs485dlySpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/scr.rs b/rust-embedded/lpc111x-pac/src/uart/scr.rs new file mode 100644 index 0000000..eca129a --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/scr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SCR` reader"] +pub type R = crate::R; +#[doc = "Register `SCR` writer"] +pub type W = crate::W; +#[doc = "Field `pad` reader - A readable, writable byte."] +pub type PadR = crate::FieldReader; +#[doc = "Field `pad` writer - A readable, writable byte."] +pub type PadW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - A readable, writable byte."] + #[inline(always)] + pub fn pad(&self) -> PadR { + PadR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - A readable, writable byte."] + #[inline(always)] + #[must_use] + pub fn pad(&mut self) -> PadW { + PadW::new(self, 0) + } +} +#[doc = "Scratch Pad Register. Eight-bit temporary storage for software.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ScrSpec; +impl crate::RegisterSpec for ScrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for ScrSpec {} +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] +impl crate::Writable for ScrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for ScrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/ter.rs b/rust-embedded/lpc111x-pac/src/uart/ter.rs new file mode 100644 index 0000000..ec078a8 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/ter.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TER` reader"] +pub type R = crate::R; +#[doc = "Register `TER` writer"] +pub type W = crate::W; +#[doc = "Field `TXEN` reader - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."] +pub type TxenR = crate::BitReader; +#[doc = "Field `TXEN` writer - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."] +pub type TxenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."] + #[inline(always)] + pub fn txen(&self) -> TxenR { + TxenR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 7 - When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character."] + #[inline(always)] + #[must_use] + pub fn txen(&mut self) -> TxenW { + TxenW::new(self, 7) + } +} +#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ter::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TerSpec; +impl crate::RegisterSpec for TerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ter::R`](R) reader structure"] +impl crate::Readable for TerSpec {} +#[doc = "`write(|w| ..)` method takes [`ter::W`](W) writer structure"] +impl crate::Writable for TerSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TER to value 0x80"] +impl crate::Resettable for TerSpec { + const RESET_VALUE: u32 = 0x80; +} diff --git a/rust-embedded/lpc111x-pac/src/uart/thr.rs b/rust-embedded/lpc111x-pac/src/uart/thr.rs new file mode 100644 index 0000000..abd5ac3 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/uart/thr.rs @@ -0,0 +1,27 @@ +#[doc = "Register `THR` writer"] +pub type W = crate::W; +#[doc = "Field `THR` writer - Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."] +pub type ThrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available."] + #[inline(always)] + #[must_use] + pub fn thr(&mut self) -> ThrW { + ThrW::new(self, 0) + } +} +#[doc = "Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ThrSpec; +impl crate::RegisterSpec for ThrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"] +impl crate::Writable for ThrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets THR to value 0"] +impl crate::Resettable for ThrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt.rs b/rust-embedded/lpc111x-pac/src/wwdt.rs new file mode 100644 index 0000000..84f8dec --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt.rs @@ -0,0 +1,79 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + wdmod: Wdmod, + wdtc: Wdtc, + wdfeed: Wdfeed, + wdtv: Wdtv, + _reserved4: [u8; 0x04], + wdwarnint: Wdwarnint, + wdwindow: Wdwindow, +} +impl RegisterBlock { + #[doc = "0x00 - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."] + #[inline(always)] + pub const fn wdmod(&self) -> &Wdmod { + &self.wdmod + } + #[doc = "0x04 - Watchdog timer constant register. This register determines the time-out value."] + #[inline(always)] + pub const fn wdtc(&self) -> &Wdtc { + &self.wdtc + } + #[doc = "0x08 - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."] + #[inline(always)] + pub const fn wdfeed(&self) -> &Wdfeed { + &self.wdfeed + } + #[doc = "0x0c - Watchdog timer value register. This register reads out the current value of the Watchdog timer."] + #[inline(always)] + pub const fn wdtv(&self) -> &Wdtv { + &self.wdtv + } + #[doc = "0x14 - Watchdog Warning Interrupt compare value."] + #[inline(always)] + pub const fn wdwarnint(&self) -> &Wdwarnint { + &self.wdwarnint + } + #[doc = "0x18 - Watchdog Window compare value."] + #[inline(always)] + pub const fn wdwindow(&self) -> &Wdwindow { + &self.wdwindow + } +} +#[doc = "WDMOD (rw) register accessor: Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdmod::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdmod::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdmod`] +module"] +#[doc(alias = "WDMOD")] +pub type Wdmod = crate::Reg; +#[doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer."] +pub mod wdmod; +#[doc = "WDTC (rw) register accessor: Watchdog timer constant register. This register determines the time-out value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtc`] +module"] +#[doc(alias = "WDTC")] +pub type Wdtc = crate::Reg; +#[doc = "Watchdog timer constant register. This register determines the time-out value."] +pub mod wdtc; +#[doc = "WDFEED (w) register accessor: Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdfeed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdfeed`] +module"] +#[doc(alias = "WDFEED")] +pub type Wdfeed = crate::Reg; +#[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC."] +pub mod wdfeed; +#[doc = "WDTV (r) register accessor: Watchdog timer value register. This register reads out the current value of the Watchdog timer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtv::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdtv`] +module"] +#[doc(alias = "WDTV")] +pub type Wdtv = crate::Reg; +#[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer."] +pub mod wdtv; +#[doc = "WDWARNINT (rw) register accessor: Watchdog Warning Interrupt compare value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdwarnint::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdwarnint::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdwarnint`] +module"] +#[doc(alias = "WDWARNINT")] +pub type Wdwarnint = crate::Reg; +#[doc = "Watchdog Warning Interrupt compare value."] +pub mod wdwarnint; +#[doc = "WDWINDOW (rw) register accessor: Watchdog Window compare value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdwindow::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdwindow::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdwindow`] +module"] +#[doc(alias = "WDWINDOW")] +pub type Wdwindow = crate::Reg; +#[doc = "Watchdog Window compare value."] +pub mod wdwindow; diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdfeed.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdfeed.rs new file mode 100644 index 0000000..3e9afd7 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdfeed.rs @@ -0,0 +1,27 @@ +#[doc = "Register `WDFEED` writer"] +pub type W = crate::W; +#[doc = "Field `Feed` writer - Feed value should be 0xAA followed by 0x55."] +pub type FeedW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7 - Feed value should be 0xAA followed by 0x55."] + #[inline(always)] + #[must_use] + pub fn feed(&mut self) -> FeedW { + FeedW::new(self, 0) + } +} +#[doc = "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdfeed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdfeedSpec; +impl crate::RegisterSpec for WdfeedSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`wdfeed::W`](W) writer structure"] +impl crate::Writable for WdfeedSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDFEED to value 0"] +impl crate::Resettable for WdfeedSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdmod.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdmod.rs new file mode 100644 index 0000000..09cee6d --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdmod.rs @@ -0,0 +1,247 @@ +#[doc = "Register `WDMOD` reader"] +pub type R = crate::R; +#[doc = "Register `WDMOD` writer"] +pub type W = crate::W; +#[doc = "Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wden { + #[doc = "0: The watchdog timer is stopped."] + Stopped = 0, + #[doc = "1: The watchdog timer is running."] + Run = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wden) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDEN` reader - Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one."] +pub type WdenR = crate::BitReader; +impl WdenR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wden { + match self.bits { + false => Wden::Stopped, + true => Wden::Run, + } + } + #[doc = "The watchdog timer is stopped."] + #[inline(always)] + pub fn is_stopped(&self) -> bool { + *self == Wden::Stopped + } + #[doc = "The watchdog timer is running."] + #[inline(always)] + pub fn is_run(&self) -> bool { + *self == Wden::Run + } +} +#[doc = "Field `WDEN` writer - Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one."] +pub type WdenW<'a, REG> = crate::BitWriter<'a, REG, Wden>; +impl<'a, REG> WdenW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The watchdog timer is stopped."] + #[inline(always)] + pub fn stopped(self) -> &'a mut crate::W { + self.variant(Wden::Stopped) + } + #[doc = "The watchdog timer is running."] + #[inline(always)] + pub fn run(self) -> &'a mut crate::W { + self.variant(Wden::Run) + } +} +#[doc = "Watchdog reset enable bit. This bit is Set Only.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdreset { + #[doc = "0: A watchdog timeout will not cause a chip reset."] + Noreset = 0, + #[doc = "1: A watchdog timeout will cause a chip reset."] + Reset = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdreset) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDRESET` reader - Watchdog reset enable bit. This bit is Set Only."] +pub type WdresetR = crate::BitReader; +impl WdresetR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdreset { + match self.bits { + false => Wdreset::Noreset, + true => Wdreset::Reset, + } + } + #[doc = "A watchdog timeout will not cause a chip reset."] + #[inline(always)] + pub fn is_noreset(&self) -> bool { + *self == Wdreset::Noreset + } + #[doc = "A watchdog timeout will cause a chip reset."] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == Wdreset::Reset + } +} +#[doc = "Field `WDRESET` writer - Watchdog reset enable bit. This bit is Set Only."] +pub type WdresetW<'a, REG> = crate::BitWriter<'a, REG, Wdreset>; +impl<'a, REG> WdresetW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "A watchdog timeout will not cause a chip reset."] + #[inline(always)] + pub fn noreset(self) -> &'a mut crate::W { + self.variant(Wdreset::Noreset) + } + #[doc = "A watchdog timeout will cause a chip reset."] + #[inline(always)] + pub fn reset(self) -> &'a mut crate::W { + self.variant(Wdreset::Reset) + } +} +#[doc = "Field `WDTOF` reader - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1."] +pub type WdtofR = crate::BitReader; +#[doc = "Field `WDTOF` writer - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1."] +pub type WdtofW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDINT` reader - Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software."] +pub type WdintR = crate::BitReader; +#[doc = "Field `WDINT` writer - Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software."] +pub type WdintW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Watchdog update mode. This bit is Set Only.\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum Wdprotect { + #[doc = "0: The watchdog reload value (WDTC) can be changed at any time."] + Anytime = 0, + #[doc = "1: The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1."] + Lowcounter = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: Wdprotect) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `WDPROTECT` reader - Watchdog update mode. This bit is Set Only."] +pub type WdprotectR = crate::BitReader; +impl WdprotectR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Wdprotect { + match self.bits { + false => Wdprotect::Anytime, + true => Wdprotect::Lowcounter, + } + } + #[doc = "The watchdog reload value (WDTC) can be changed at any time."] + #[inline(always)] + pub fn is_anytime(&self) -> bool { + *self == Wdprotect::Anytime + } + #[doc = "The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1."] + #[inline(always)] + pub fn is_lowcounter(&self) -> bool { + *self == Wdprotect::Lowcounter + } +} +#[doc = "Field `WDPROTECT` writer - Watchdog update mode. This bit is Set Only."] +pub type WdprotectW<'a, REG> = crate::BitWriter<'a, REG, Wdprotect>; +impl<'a, REG> WdprotectW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "The watchdog reload value (WDTC) can be changed at any time."] + #[inline(always)] + pub fn anytime(self) -> &'a mut crate::W { + self.variant(Wdprotect::Anytime) + } + #[doc = "The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1."] + #[inline(always)] + pub fn lowcounter(self) -> &'a mut crate::W { + self.variant(Wdprotect::Lowcounter) + } +} +impl R { + #[doc = "Bit 0 - Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one."] + #[inline(always)] + pub fn wden(&self) -> WdenR { + WdenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Watchdog reset enable bit. This bit is Set Only."] + #[inline(always)] + pub fn wdreset(&self) -> WdresetR { + WdresetR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1."] + #[inline(always)] + pub fn wdtof(&self) -> WdtofR { + WdtofR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software."] + #[inline(always)] + pub fn wdint(&self) -> WdintR { + WdintR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Watchdog update mode. This bit is Set Only."] + #[inline(always)] + pub fn wdprotect(&self) -> WdprotectR { + WdprotectR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one."] + #[inline(always)] + #[must_use] + pub fn wden(&mut self) -> WdenW { + WdenW::new(self, 0) + } + #[doc = "Bit 1 - Watchdog reset enable bit. This bit is Set Only."] + #[inline(always)] + #[must_use] + pub fn wdreset(&mut self) -> WdresetW { + WdresetW::new(self, 1) + } + #[doc = "Bit 2 - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1."] + #[inline(always)] + #[must_use] + pub fn wdtof(&mut self) -> WdtofW { + WdtofW::new(self, 2) + } + #[doc = "Bit 3 - Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software."] + #[inline(always)] + #[must_use] + pub fn wdint(&mut self) -> WdintW { + WdintW::new(self, 3) + } + #[doc = "Bit 4 - Watchdog update mode. This bit is Set Only."] + #[inline(always)] + #[must_use] + pub fn wdprotect(&mut self) -> WdprotectW { + WdprotectW::new(self, 4) + } +} +#[doc = "Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdmod::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdmod::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdmodSpec; +impl crate::RegisterSpec for WdmodSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdmod::R`](R) reader structure"] +impl crate::Readable for WdmodSpec {} +#[doc = "`write(|w| ..)` method takes [`wdmod::W`](W) writer structure"] +impl crate::Writable for WdmodSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDMOD to value 0"] +impl crate::Resettable for WdmodSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdtc.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdtc.rs new file mode 100644 index 0000000..e9570a6 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdtc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDTC` reader"] +pub type R = crate::R; +#[doc = "Register `WDTC` writer"] +pub type W = crate::W; +#[doc = "Field `Count` reader - Watchdog time-out interval."] +pub type CountR = crate::FieldReader; +#[doc = "Field `Count` writer - Watchdog time-out interval."] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Watchdog time-out interval."] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Watchdog time-out interval."] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "Watchdog timer constant register. This register determines the time-out value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdtc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtcSpec; +impl crate::RegisterSpec for WdtcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtc::R`](R) reader structure"] +impl crate::Readable for WdtcSpec {} +#[doc = "`write(|w| ..)` method takes [`wdtc::W`](W) writer structure"] +impl crate::Writable for WdtcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDTC to value 0xff"] +impl crate::Resettable for WdtcSpec { + const RESET_VALUE: u32 = 0xff; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdtv.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdtv.rs new file mode 100644 index 0000000..4639305 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdtv.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDTV` reader"] +pub type R = crate::R; +#[doc = "Field `Count` reader - Counter timer value."] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Counter timer value."] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits & 0x00ff_ffff) + } +} +#[doc = "Watchdog timer value register. This register reads out the current value of the Watchdog timer.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdtv::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdtvSpec; +impl crate::RegisterSpec for WdtvSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdtv::R`](R) reader structure"] +impl crate::Readable for WdtvSpec {} +#[doc = "`reset()` method sets WDTV to value 0xff"] +impl crate::Resettable for WdtvSpec { + const RESET_VALUE: u32 = 0xff; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdwarnint.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdwarnint.rs new file mode 100644 index 0000000..5891161 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdwarnint.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDWARNINT` reader"] +pub type R = crate::R; +#[doc = "Register `WDWARNINT` writer"] +pub type W = crate::W; +#[doc = "Field `WARNINT` reader - Watchdog warning interrupt compare value."] +pub type WarnintR = crate::FieldReader; +#[doc = "Field `WARNINT` writer - Watchdog warning interrupt compare value."] +pub type WarnintW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - Watchdog warning interrupt compare value."] + #[inline(always)] + pub fn warnint(&self) -> WarnintR { + WarnintR::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Watchdog warning interrupt compare value."] + #[inline(always)] + #[must_use] + pub fn warnint(&mut self) -> WarnintW { + WarnintW::new(self, 0) + } +} +#[doc = "Watchdog Warning Interrupt compare value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdwarnint::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdwarnint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdwarnintSpec; +impl crate::RegisterSpec for WdwarnintSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdwarnint::R`](R) reader structure"] +impl crate::Readable for WdwarnintSpec {} +#[doc = "`write(|w| ..)` method takes [`wdwarnint::W`](W) writer structure"] +impl crate::Writable for WdwarnintSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDWARNINT to value 0"] +impl crate::Resettable for WdwarnintSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/rust-embedded/lpc111x-pac/src/wwdt/wdwindow.rs b/rust-embedded/lpc111x-pac/src/wwdt/wdwindow.rs new file mode 100644 index 0000000..1d83064 --- /dev/null +++ b/rust-embedded/lpc111x-pac/src/wwdt/wdwindow.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDWINDOW` reader"] +pub type R = crate::R; +#[doc = "Register `WDWINDOW` writer"] +pub type W = crate::W; +#[doc = "Field `WINDOW` reader - Watchdog window value."] +pub type WindowR = crate::FieldReader; +#[doc = "Field `WINDOW` writer - Watchdog window value."] +pub type WindowW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Watchdog window value."] + #[inline(always)] + pub fn window(&self) -> WindowR { + WindowR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Watchdog window value."] + #[inline(always)] + #[must_use] + pub fn window(&mut self) -> WindowW { + WindowW::new(self, 0) + } +} +#[doc = "Watchdog Window compare value.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdwindow::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdwindow::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdwindowSpec; +impl crate::RegisterSpec for WdwindowSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdwindow::R`](R) reader structure"] +impl crate::Readable for WdwindowSpec {} +#[doc = "`write(|w| ..)` method takes [`wdwindow::W`](W) writer structure"] +impl crate::Writable for WdwindowSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDWINDOW to value 0x00ff_ffff"] +impl crate::Resettable for WdwindowSpec { + const RESET_VALUE: u32 = 0x00ff_ffff; +} diff --git a/rust-embedded/lpc111x-pac/svd/LPC111x.yaml b/rust-embedded/lpc111x-pac/svd/LPC111x.yaml index fcde172..912ae7d 100644 --- a/rust-embedded/lpc111x-pac/svd/LPC111x.yaml +++ b/rust-embedded/lpc111x-pac/svd/LPC111x.yaml @@ -1 +1,86 @@ _svd: LPC111x.svd + +"CT16B0,CT32B0": + CTCR: + CTM: + _replace_enum: + TIMER: [0, "Increment on every rising PCLK edge"] + COUNTER_RISING: [1, "Increment on rising CAP pin edge"] + COUNTER_FALLING: [2, "Increment on falling CAP pin edge"] + COUNTER_BOTH: [3, "Increment on both CAP pin edges"] + SELCC: + _replace_enum: + CAP0_RISING: [0, "Rising Edge of CAP0 clears the timer"] + CAP0_FALLING: [1, "Falling Edge of CAP0 clears the timer"] + CAP1_RISING: [2, "Rising Edge of CAP1 clears the timer"] + CAP1_FALLING: [3, "Falling Edge of CAP1 clears the timer"] + +IOCON: + _strip: + - "IOCON_" + + "PIO0_[45]": + I2CMODE: + _replace_enum: + STANDARD_I2C: [0, "Standard mode/Fast-mode I2C"] + STANDARD_IO: [1, "Standard I/O"] + FAST_PLUS_I2C: [2, "Fast-mode Plus I2C"] + + SCK0_LOC: + SCKLOC: + _replace_enum: + PI00_10: [0, ""] + PI02_11: [1, ""] + PI00_6: [2, ""] + DSR_LOC: + DSRLOC: + _replace_enum: + PIO2_1: [0, ""] + PIO3_1: [1, ""] + DCD_LOC: + DCDLOC: + _replace_enum: + PIO2_2: [0, ""] + PIO3_2: [1, ""] + RI_LOC: + RILOC: + _replace_enum: + PIO2_3: [0, ""] + PIO3_3: [1, ""] + SSEL1_LOC: + SSEL1LOC: + _replace_enum: + PIO2_2: [0, ""] + PIO3_4: [1, ""] + CT16B0_CAP0_LOC: + CT16B0_CAP0LOC: + _replace_enum: + PIO0_2: [0, ""] + PIO3_3: [1, ""] + CT32B0_CAP0_LOC: + CT32B0_CAP0LOC: + _replace_enum: + PIO1_5: [0, ""] + PIO2_9: [1, ""] + SCK1_LOC: + SCK1LOC: + _replace_enum: + PIO2_1: [0, ""] + PIO3_2: [1, ""] + MISO1_LOC: + MISO1LOC: + _replace_enum: + PIO2_2: [0, ""] + PIO1_10: [1, ""] + MOSI1_LOC: + MOSI1LOC: + _replace_enum: + PIO2_3: [0, ""] + PIO1_9: [1, ""] + RXD_LOC: + RXDLOC: + _replace_enum: + PIO1_6: [0, ""] + PIO2_7: [1, ""] + PIO3_1: [2, ""] + PIO3_4: [3, ""]