diff --git a/rust-embedded/lpc1114-test/src/main.rs b/rust-embedded/lpc1114-test/src/main.rs
index 91b0dc0..16bf2a9 100644
--- a/rust-embedded/lpc1114-test/src/main.rs
+++ b/rust-embedded/lpc1114-test/src/main.rs
@@ -10,16 +10,16 @@ fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap();
// SAFETY: yes... ha ha ha... YES
- let gpio0 = unsafe { &(*lpc11xx::GPIO0::ptr()) };
+ let gpio0 = unsafe { &(*lpc111x_pac::Gpio0::ptr()) };
- gpio0.dir.write(|w| w.dir7().output());
+ gpio0.dir().write(|w| w.io7().bit(true));
let mut delay = cortex_m::delay::Delay::new(cp.SYST, 12_000_000);
loop {
- gpio0.data.write(|w| w.data7().high());
+ gpio0.data().write(|w| w.data7().bit(true));
delay.delay_ms(500);
- gpio0.data.write(|w| w.data7().low());
+ gpio0.data().write(|w| w.data7().bit(false));
delay.delay_ms(500);
}
}
diff --git a/rust-embedded/lpc111x-pac/generate.sh b/rust-embedded/lpc111x-pac/generate.sh
index e459ebe..9324258 100755
--- a/rust-embedded/lpc111x-pac/generate.sh
+++ b/rust-embedded/lpc111x-pac/generate.sh
@@ -3,6 +3,10 @@
set -euo pipefail
svdtools patch svd/LPC111x.yaml
+
+# Hard to do this in svdtools, easy in sed
+sed -E -i 's#(ENUM|test)##' svd/LPC111x.svd.patched
+
svd2rust -i svd/LPC111x.svd.patched
rm -r src
form -i lib.rs -o src
diff --git a/rust-embedded/lpc111x-pac/src/adc.rs b/rust-embedded/lpc111x-pac/src/adc.rs
new file mode 100644
index 0000000..1f5e9a0
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc.rs
@@ -0,0 +1,73 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+ cr: Cr,
+ gdr: Gdr,
+ _reserved2: [u8; 0x04],
+ inten: Inten,
+ dr: [Dr; 8],
+ stat: Stat,
+}
+impl RegisterBlock {
+ #[doc = "0x00 - A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
+ #[inline(always)]
+ pub const fn cr(&self) -> &Cr {
+ &self.cr
+ }
+ #[doc = "0x04 - A/D Global Data Register. Contains the result of the most recent A/D conversion."]
+ #[inline(always)]
+ pub const fn gdr(&self) -> &Gdr {
+ &self.gdr
+ }
+ #[doc = "0x0c - A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
+ #[inline(always)]
+ pub const fn inten(&self) -> &Inten {
+ &self.inten
+ }
+ #[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
+ #[inline(always)]
+ pub const fn dr(&self, n: usize) -> &Dr {
+ &self.dr[n]
+ }
+ #[doc = "Iterator for array of:"]
+ #[doc = "0x10..0x30 - A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
+ #[inline(always)]
+ pub fn dr_iter(&self) -> impl Iterator- {
+ self.dr.iter()
+ }
+ #[doc = "0x30 - A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
+ #[inline(always)]
+ pub const fn stat(&self) -> &Stat {
+ &self.stat
+ }
+}
+#[doc = "CR (rw) register accessor: A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
+module"]
+#[doc(alias = "CR")]
+pub type Cr = crate::Reg;
+#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur."]
+pub mod cr;
+#[doc = "GDR (rw) register accessor: A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gdr`]
+module"]
+#[doc(alias = "GDR")]
+pub type Gdr = crate::Reg;
+#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion."]
+pub mod gdr;
+#[doc = "STAT (r) register accessor: A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
+module"]
+#[doc(alias = "STAT")]
+pub type Stat = crate::Reg;
+#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag."]
+pub mod stat;
+#[doc = "INTEN (rw) register accessor: A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
+module"]
+#[doc(alias = "INTEN")]
+pub type Inten = crate::Reg;
+#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt."]
+pub mod inten;
+#[doc = "DR (rw) register accessor: A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dr`]
+module"]
+#[doc(alias = "DR")]
+pub type Dr = crate::Reg;
+#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n."]
+pub mod dr;
diff --git a/rust-embedded/lpc111x-pac/src/adc/cr.rs b/rust-embedded/lpc111x-pac/src/adc/cr.rs
new file mode 100644
index 0000000..66326cf
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc/cr.rs
@@ -0,0 +1,479 @@
+#[doc = "Register `CR` reader"]
+pub type R = crate::R;
+#[doc = "Register `CR` writer"]
+pub type W = crate::W;
+#[doc = "Field `SEL` reader - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
+pub type SelR = crate::FieldReader;
+#[doc = "Field `SEL` writer - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
+pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `CLKDIV` reader - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
+pub type ClkdivR = crate::FieldReader;
+#[doc = "Field `CLKDIV` writer - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
+pub type ClkdivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Burst mode\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Burst {
+ #[doc = "0: Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
+ Swmode = 0,
+ #[doc = "1: Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
+ Hwmode = 1,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Burst) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `BURST` reader - Burst mode"]
+pub type BurstR = crate::BitReader;
+impl BurstR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Burst {
+ match self.bits {
+ false => Burst::Swmode,
+ true => Burst::Hwmode,
+ }
+ }
+ #[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
+ #[inline(always)]
+ pub fn is_swmode(&self) -> bool {
+ *self == Burst::Swmode
+ }
+ #[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
+ #[inline(always)]
+ pub fn is_hwmode(&self) -> bool {
+ *self == Burst::Hwmode
+ }
+}
+#[doc = "Field `BURST` writer - Burst mode"]
+pub type BurstW<'a, REG> = crate::BitWriter<'a, REG, Burst>;
+impl<'a, REG> BurstW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Software-controlled mode: Conversions are software-controlled and require 11 clocks."]
+ #[inline(always)]
+ pub fn swmode(self) -> &'a mut crate::W {
+ self.variant(Burst::Swmode)
+ }
+ #[doc = "Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start."]
+ #[inline(always)]
+ pub fn hwmode(self) -> &'a mut crate::W {
+ self.variant(Burst::Hwmode)
+ }
+}
+#[doc = "This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Clks {
+ #[doc = "0: 11 clocks / 10 bits"]
+ _10bit = 0,
+ #[doc = "1: 10 clocks / 9 bits"]
+ _9bit = 1,
+ #[doc = "2: 9 clocks / 8 bits"]
+ _8bit = 2,
+ #[doc = "3: 8 clocks / 7 bits"]
+ _7bit = 3,
+ #[doc = "4: 7 clocks / 6 bits"]
+ _6bit = 4,
+ #[doc = "5: 6 clocks / 5 bits"]
+ _5bit = 5,
+ #[doc = "6: 5 clocks / 4 bits"]
+ _4bit = 6,
+ #[doc = "7: 4 clocks / 3 bits"]
+ _3bit = 7,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Clks) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Clks {
+ type Ux = u8;
+}
+#[doc = "Field `CLKS` reader - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
+pub type ClksR = crate::FieldReader;
+impl ClksR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Clks {
+ match self.bits {
+ 0 => Clks::_10bit,
+ 1 => Clks::_9bit,
+ 2 => Clks::_8bit,
+ 3 => Clks::_7bit,
+ 4 => Clks::_6bit,
+ 5 => Clks::_5bit,
+ 6 => Clks::_4bit,
+ 7 => Clks::_3bit,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "11 clocks / 10 bits"]
+ #[inline(always)]
+ pub fn is_10bit(&self) -> bool {
+ *self == Clks::_10bit
+ }
+ #[doc = "10 clocks / 9 bits"]
+ #[inline(always)]
+ pub fn is_9bit(&self) -> bool {
+ *self == Clks::_9bit
+ }
+ #[doc = "9 clocks / 8 bits"]
+ #[inline(always)]
+ pub fn is_8bit(&self) -> bool {
+ *self == Clks::_8bit
+ }
+ #[doc = "8 clocks / 7 bits"]
+ #[inline(always)]
+ pub fn is_7bit(&self) -> bool {
+ *self == Clks::_7bit
+ }
+ #[doc = "7 clocks / 6 bits"]
+ #[inline(always)]
+ pub fn is_6bit(&self) -> bool {
+ *self == Clks::_6bit
+ }
+ #[doc = "6 clocks / 5 bits"]
+ #[inline(always)]
+ pub fn is_5bit(&self) -> bool {
+ *self == Clks::_5bit
+ }
+ #[doc = "5 clocks / 4 bits"]
+ #[inline(always)]
+ pub fn is_4bit(&self) -> bool {
+ *self == Clks::_4bit
+ }
+ #[doc = "4 clocks / 3 bits"]
+ #[inline(always)]
+ pub fn is_3bit(&self) -> bool {
+ *self == Clks::_3bit
+ }
+}
+#[doc = "Field `CLKS` writer - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
+pub type ClksW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Clks>;
+impl<'a, REG> ClksW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "11 clocks / 10 bits"]
+ #[inline(always)]
+ pub fn _10bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_10bit)
+ }
+ #[doc = "10 clocks / 9 bits"]
+ #[inline(always)]
+ pub fn _9bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_9bit)
+ }
+ #[doc = "9 clocks / 8 bits"]
+ #[inline(always)]
+ pub fn _8bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_8bit)
+ }
+ #[doc = "8 clocks / 7 bits"]
+ #[inline(always)]
+ pub fn _7bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_7bit)
+ }
+ #[doc = "7 clocks / 6 bits"]
+ #[inline(always)]
+ pub fn _6bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_6bit)
+ }
+ #[doc = "6 clocks / 5 bits"]
+ #[inline(always)]
+ pub fn _5bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_5bit)
+ }
+ #[doc = "5 clocks / 4 bits"]
+ #[inline(always)]
+ pub fn _4bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_4bit)
+ }
+ #[doc = "4 clocks / 3 bits"]
+ #[inline(always)]
+ pub fn _3bit(self) -> &'a mut crate::W {
+ self.variant(Clks::_3bit)
+ }
+}
+#[doc = "When the BURST bit is 0, these bits control whether and when an A/D conversion is started:\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Start {
+ #[doc = "0: No start (this value should be used when clearing PDN to 0)."]
+ Stop = 0,
+ #[doc = "1: Start conversion now."]
+ Start = 1,
+ #[doc = "2: Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
+ Edgepio0_2 = 2,
+ #[doc = "3: Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
+ Edgepio1_5 = 3,
+ #[doc = "4: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
+ Edgect32b0Mat0_1 = 4,
+ #[doc = "5: Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
+ Edgect32b0Mat1_1 = 5,
+ #[doc = "6: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
+ Edgect16b0Mat0_1 = 6,
+ #[doc = "7: Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
+ Edgect16b0Mat1_1 = 7,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Start) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Start {
+ type Ux = u8;
+}
+#[doc = "Field `START` reader - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
+pub type StartR = crate::FieldReader;
+impl StartR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Start {
+ match self.bits {
+ 0 => Start::Stop,
+ 1 => Start::Start,
+ 2 => Start::Edgepio0_2,
+ 3 => Start::Edgepio1_5,
+ 4 => Start::Edgect32b0Mat0_1,
+ 5 => Start::Edgect32b0Mat1_1,
+ 6 => Start::Edgect16b0Mat0_1,
+ 7 => Start::Edgect16b0Mat1_1,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "No start (this value should be used when clearing PDN to 0)."]
+ #[inline(always)]
+ pub fn is_stop(&self) -> bool {
+ *self == Start::Stop
+ }
+ #[doc = "Start conversion now."]
+ #[inline(always)]
+ pub fn is_start(&self) -> bool {
+ *self == Start::Start
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
+ #[inline(always)]
+ pub fn is_edgepio0_2(&self) -> bool {
+ *self == Start::Edgepio0_2
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
+ #[inline(always)]
+ pub fn is_edgepio1_5(&self) -> bool {
+ *self == Start::Edgepio1_5
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
+ #[inline(always)]
+ pub fn is_edgect32b0_mat0_1(&self) -> bool {
+ *self == Start::Edgect32b0Mat0_1
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
+ #[inline(always)]
+ pub fn is_edgect32b0_mat1_1(&self) -> bool {
+ *self == Start::Edgect32b0Mat1_1
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
+ #[inline(always)]
+ pub fn is_edgect16b0_mat0_1(&self) -> bool {
+ *self == Start::Edgect16b0Mat0_1
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
+ #[inline(always)]
+ pub fn is_edgect16b0_mat1_1(&self) -> bool {
+ *self == Start::Edgect16b0Mat1_1
+ }
+}
+#[doc = "Field `START` writer - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
+pub type StartW<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, Start>;
+impl<'a, REG> StartW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "No start (this value should be used when clearing PDN to 0)."]
+ #[inline(always)]
+ pub fn stop(self) -> &'a mut crate::W {
+ self.variant(Start::Stop)
+ }
+ #[doc = "Start conversion now."]
+ #[inline(always)]
+ pub fn start(self) -> &'a mut crate::W {
+ self.variant(Start::Start)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0."]
+ #[inline(always)]
+ pub fn edgepio0_2(self) -> &'a mut crate::W {
+ self.variant(Start::Edgepio0_2)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0."]
+ #[inline(always)]
+ pub fn edgepio1_5(self) -> &'a mut crate::W {
+ self.variant(Start::Edgepio1_5)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0\\[1\\]."]
+ #[inline(always)]
+ pub fn edgect32b0_mat0_1(self) -> &'a mut crate::W {
+ self.variant(Start::Edgect32b0Mat0_1)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1\\[1\\]."]
+ #[inline(always)]
+ pub fn edgect32b0_mat1_1(self) -> &'a mut crate::W {
+ self.variant(Start::Edgect32b0Mat1_1)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0\\[1\\]."]
+ #[inline(always)]
+ pub fn edgect16b0_mat0_1(self) -> &'a mut crate::W {
+ self.variant(Start::Edgect16b0Mat0_1)
+ }
+ #[doc = "Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1\\[1\\]."]
+ #[inline(always)]
+ pub fn edgect16b0_mat1_1(self) -> &'a mut crate::W {
+ self.variant(Start::Edgect16b0Mat1_1)
+ }
+}
+#[doc = "This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Edge {
+ #[doc = "0: Start conversion on a rising edge on the selected CAP/MAT signal."]
+ Rising = 0,
+ #[doc = "1: Start conversion on a rising edge on the selected CAP/MAT signal."]
+ Falling = 1,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Edge) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `EDGE` reader - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
+pub type EdgeR = crate::BitReader;
+impl EdgeR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Edge {
+ match self.bits {
+ false => Edge::Rising,
+ true => Edge::Falling,
+ }
+ }
+ #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ pub fn is_rising(&self) -> bool {
+ *self == Edge::Rising
+ }
+ #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ pub fn is_falling(&self) -> bool {
+ *self == Edge::Falling
+ }
+}
+#[doc = "Field `EDGE` writer - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
+pub type EdgeW<'a, REG> = crate::BitWriter<'a, REG, Edge>;
+impl<'a, REG> EdgeW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ pub fn rising(self) -> &'a mut crate::W {
+ self.variant(Edge::Rising)
+ }
+ #[doc = "Start conversion on a rising edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ pub fn falling(self) -> &'a mut crate::W {
+ self.variant(Edge::Falling)
+ }
+}
+impl R {
+ #[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
+ #[inline(always)]
+ pub fn sel(&self) -> SelR {
+ SelR::new((self.bits & 0xff) as u8)
+ }
+ #[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
+ #[inline(always)]
+ pub fn clkdiv(&self) -> ClkdivR {
+ ClkdivR::new(((self.bits >> 8) & 0xff) as u8)
+ }
+ #[doc = "Bit 16 - Burst mode"]
+ #[inline(always)]
+ pub fn burst(&self) -> BurstR {
+ BurstR::new(((self.bits >> 16) & 1) != 0)
+ }
+ #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
+ #[inline(always)]
+ pub fn clks(&self) -> ClksR {
+ ClksR::new(((self.bits >> 17) & 7) as u8)
+ }
+ #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
+ #[inline(always)]
+ pub fn start(&self) -> StartR {
+ StartR::new(((self.bits >> 24) & 7) as u8)
+ }
+ #[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ pub fn edge(&self) -> EdgeR {
+ EdgeR::new(((self.bits >> 27) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 0:7 - Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn sel(&mut self) -> SelW {
+ SelW::new(self, 0)
+ }
+ #[doc = "Bits 8:15 - The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable."]
+ #[inline(always)]
+ #[must_use]
+ pub fn clkdiv(&mut self) -> ClkdivW {
+ ClkdivW::new(self, 8)
+ }
+ #[doc = "Bit 16 - Burst mode"]
+ #[inline(always)]
+ #[must_use]
+ pub fn burst(&mut self) -> BurstW {
+ BurstW::new(self, 16)
+ }
+ #[doc = "Bits 17:19 - This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn clks(&mut self) -> ClksW {
+ ClksW::new(self, 17)
+ }
+ #[doc = "Bits 24:26 - When the BURST bit is 0, these bits control whether and when an A/D conversion is started:"]
+ #[inline(always)]
+ #[must_use]
+ pub fn start(&mut self) -> StartW {
+ StartW::new(self, 24)
+ }
+ #[doc = "Bit 27 - This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal."]
+ #[inline(always)]
+ #[must_use]
+ pub fn edge(&mut self) -> EdgeW {
+ EdgeW::new(self, 27)
+ }
+}
+#[doc = "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CrSpec;
+impl crate::RegisterSpec for CrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
+impl crate::Readable for CrSpec {}
+#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
+impl crate::Writable for CrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CR to value 0"]
+impl crate::Resettable for CrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/adc/dr.rs b/rust-embedded/lpc111x-pac/src/adc/dr.rs
new file mode 100644
index 0000000..d9024d5
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc/dr.rs
@@ -0,0 +1,70 @@
+#[doc = "Register `DR%s` reader"]
+pub type R = crate::R;
+#[doc = "Register `DR%s` writer"]
+pub type W = crate::W;
+#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
+pub type VVrefR = crate::FieldReader;
+#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
+pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
+pub type OverrunR = crate::BitReader;
+#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
+pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
+pub type DoneR = crate::BitReader;
+#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
+pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+ #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
+ #[inline(always)]
+ pub fn v_vref(&self) -> VVrefR {
+ VVrefR::new(((self.bits >> 6) & 0x03ff) as u16)
+ }
+ #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
+ #[inline(always)]
+ pub fn overrun(&self) -> OverrunR {
+ OverrunR::new(((self.bits >> 30) & 1) != 0)
+ }
+ #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
+ #[inline(always)]
+ pub fn done(&self) -> DoneR {
+ DoneR::new(((self.bits >> 31) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF."]
+ #[inline(always)]
+ #[must_use]
+ pub fn v_vref(&mut self) -> VVrefW {
+ VVrefW::new(self, 6)
+ }
+ #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register."]
+ #[inline(always)]
+ #[must_use]
+ pub fn overrun(&mut self) -> OverrunW {
+ OverrunW::new(self, 30)
+ }
+ #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read."]
+ #[inline(always)]
+ #[must_use]
+ pub fn done(&mut self) -> DoneW {
+ DoneW::new(self, 31)
+ }
+}
+#[doc = "A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DrSpec;
+impl crate::RegisterSpec for DrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`dr::R`](R) reader structure"]
+impl crate::Readable for DrSpec {}
+#[doc = "`write(|w| ..)` method takes [`dr::W`](W) writer structure"]
+impl crate::Writable for DrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DR%s to value 0"]
+impl crate::Resettable for DrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/adc/gdr.rs b/rust-embedded/lpc111x-pac/src/adc/gdr.rs
new file mode 100644
index 0000000..5495fab
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc/gdr.rs
@@ -0,0 +1,85 @@
+#[doc = "Register `GDR` reader"]
+pub type R = crate::R;
+#[doc = "Register `GDR` writer"]
+pub type W = crate::W;
+#[doc = "Field `V_VREF` reader - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
+pub type VVrefR = crate::FieldReader;
+#[doc = "Field `V_VREF` writer - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
+pub type VVrefW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
+#[doc = "Field `CHN` reader - These bits contain the channel from which the result bits V_VREF were converted."]
+pub type ChnR = crate::FieldReader;
+#[doc = "Field `CHN` writer - These bits contain the channel from which the result bits V_VREF were converted."]
+pub type ChnW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `OVERRUN` reader - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
+pub type OverrunR = crate::BitReader;
+#[doc = "Field `OVERRUN` writer - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
+pub type OverrunW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DONE` reader - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
+pub type DoneR = crate::BitReader;
+#[doc = "Field `DONE` writer - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
+pub type DoneW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+ #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
+ #[inline(always)]
+ pub fn v_vref(&self) -> VVrefR {
+ VVrefR::new(((self.bits >> 6) & 0x03ff) as u16)
+ }
+ #[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."]
+ #[inline(always)]
+ pub fn chn(&self) -> ChnR {
+ ChnR::new(((self.bits >> 24) & 7) as u8)
+ }
+ #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
+ #[inline(always)]
+ pub fn overrun(&self) -> OverrunR {
+ OverrunR::new(((self.bits >> 30) & 1) != 0)
+ }
+ #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
+ #[inline(always)]
+ pub fn done(&self) -> DoneR {
+ DoneR::new(((self.bits >> 31) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 6:15 - When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF."]
+ #[inline(always)]
+ #[must_use]
+ pub fn v_vref(&mut self) -> VVrefW {
+ VVrefW::new(self, 6)
+ }
+ #[doc = "Bits 24:26 - These bits contain the channel from which the result bits V_VREF were converted."]
+ #[inline(always)]
+ #[must_use]
+ pub fn chn(&mut self) -> ChnW {
+ ChnW::new(self, 24)
+ }
+ #[doc = "Bit 30 - This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits."]
+ #[inline(always)]
+ #[must_use]
+ pub fn overrun(&mut self) -> OverrunW {
+ OverrunW::new(self, 30)
+ }
+ #[doc = "Bit 31 - This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started."]
+ #[inline(always)]
+ #[must_use]
+ pub fn done(&mut self) -> DoneW {
+ DoneW::new(self, 31)
+ }
+}
+#[doc = "A/D Global Data Register. Contains the result of the most recent A/D conversion.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct GdrSpec;
+impl crate::RegisterSpec for GdrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`gdr::R`](R) reader structure"]
+impl crate::Readable for GdrSpec {}
+#[doc = "`write(|w| ..)` method takes [`gdr::W`](W) writer structure"]
+impl crate::Writable for GdrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets GDR to value 0"]
+impl crate::Resettable for GdrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/adc/inten.rs b/rust-embedded/lpc111x-pac/src/adc/inten.rs
new file mode 100644
index 0000000..adb6488
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc/inten.rs
@@ -0,0 +1,55 @@
+#[doc = "Register `INTEN` reader"]
+pub type R = crate::R;
+#[doc = "Register `INTEN` writer"]
+pub type W = crate::W;
+#[doc = "Field `ADINTENn` reader - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
+pub type AdintennR = crate::FieldReader;
+#[doc = "Field `ADINTENn` writer - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
+pub type AdintennW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+#[doc = "Field `ADGINTEN` reader - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
+pub type AdgintenR = crate::BitReader;
+#[doc = "Field `ADGINTEN` writer - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
+pub type AdgintenW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+ #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
+ #[inline(always)]
+ pub fn adintenn(&self) -> AdintennR {
+ AdintennR::new((self.bits & 0xff) as u8)
+ }
+ #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
+ #[inline(always)]
+ pub fn adginten(&self) -> AdgintenR {
+ AdgintenR::new(((self.bits >> 8) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bits 0:7 - These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc."]
+ #[inline(always)]
+ #[must_use]
+ pub fn adintenn(&mut self) -> AdintennW {
+ AdintennW::new(self, 0)
+ }
+ #[doc = "Bit 8 - When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts."]
+ #[inline(always)]
+ #[must_use]
+ pub fn adginten(&mut self) -> AdgintenW {
+ AdgintenW::new(self, 8)
+ }
+}
+#[doc = "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IntenSpec;
+impl crate::RegisterSpec for IntenSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`inten::R`](R) reader structure"]
+impl crate::Readable for IntenSpec {}
+#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
+impl crate::Writable for IntenSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INTEN to value 0x0100"]
+impl crate::Resettable for IntenSpec {
+ const RESET_VALUE: u32 = 0x0100;
+}
diff --git a/rust-embedded/lpc111x-pac/src/adc/stat.rs b/rust-embedded/lpc111x-pac/src/adc/stat.rs
new file mode 100644
index 0000000..6acc5cb
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/adc/stat.rs
@@ -0,0 +1,36 @@
+#[doc = "Register `STAT` reader"]
+pub type R = crate::R;
+#[doc = "Field `DONE` reader - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."]
+pub type DoneR = crate::FieldReader;
+#[doc = "Field `OVERRUN` reader - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."]
+pub type OverrunR = crate::FieldReader;
+#[doc = "Field `ADINT` reader - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
+pub type AdintR = crate::BitReader;
+impl R {
+ #[doc = "Bits 0:7 - These bits mirror the DONE status flags that appear in the result register for each A/D channel n."]
+ #[inline(always)]
+ pub fn done(&self) -> DoneR {
+ DoneR::new((self.bits & 0xff) as u8)
+ }
+ #[doc = "Bits 8:15 - These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously."]
+ #[inline(always)]
+ pub fn overrun(&self) -> OverrunR {
+ OverrunR::new(((self.bits >> 8) & 0xff) as u8)
+ }
+ #[doc = "Bit 16 - This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register."]
+ #[inline(always)]
+ pub fn adint(&self) -> AdintR {
+ AdintR::new(((self.bits >> 16) & 1) != 0)
+ }
+}
+#[doc = "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatSpec;
+impl crate::RegisterSpec for StatSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`stat::R`](R) reader structure"]
+impl crate::Readable for StatSpec {}
+#[doc = "`reset()` method sets STAT to value 0"]
+impl crate::Resettable for StatSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0.rs b/rust-embedded/lpc111x-pac/src/ct16b0.rs
new file mode 100644
index 0000000..30805e1
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0.rs
@@ -0,0 +1,164 @@
+#[repr(C)]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+ ir: Ir,
+ tcr: Tcr,
+ tc: Tc,
+ pr: Pr,
+ pc: Pc,
+ mcr: Mcr,
+ mr: [Mr; 4],
+ ccr: Ccr,
+ cr: [Cr; 2],
+ _reserved9: [u8; 0x08],
+ emr: Emr,
+ _reserved10: [u8; 0x30],
+ ctcr: Ctcr,
+ pwmc: Pwmc,
+}
+impl RegisterBlock {
+ #[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
+ #[inline(always)]
+ pub const fn ir(&self) -> &Ir {
+ &self.ir
+ }
+ #[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
+ #[inline(always)]
+ pub const fn tcr(&self) -> &Tcr {
+ &self.tcr
+ }
+ #[doc = "0x08 - Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
+ #[inline(always)]
+ pub const fn tc(&self) -> &Tc {
+ &self.tc
+ }
+ #[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
+ #[inline(always)]
+ pub const fn pr(&self) -> &Pr {
+ &self.pr
+ }
+ #[doc = "0x10 - Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
+ #[inline(always)]
+ pub const fn pc(&self) -> &Pc {
+ &self.pc
+ }
+ #[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
+ #[inline(always)]
+ pub const fn mcr(&self) -> &Mcr {
+ &self.mcr
+ }
+ #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
+ #[inline(always)]
+ pub const fn mr(&self, n: usize) -> &Mr {
+ &self.mr[n]
+ }
+ #[doc = "Iterator for array of:"]
+ #[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
+ #[inline(always)]
+ pub fn mr_iter(&self) -> impl Iterator
- {
+ self.mr.iter()
+ }
+ #[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
+ #[inline(always)]
+ pub const fn ccr(&self) -> &Ccr {
+ &self.ccr
+ }
+ #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
+ #[inline(always)]
+ pub const fn cr(&self, n: usize) -> &Cr {
+ &self.cr[n]
+ }
+ #[doc = "Iterator for array of:"]
+ #[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
+ #[inline(always)]
+ pub fn cr_iter(&self) -> impl Iterator
- {
+ self.cr.iter()
+ }
+ #[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."]
+ #[inline(always)]
+ pub const fn emr(&self) -> &Emr {
+ &self.emr
+ }
+ #[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
+ #[inline(always)]
+ pub const fn ctcr(&self) -> &Ctcr {
+ &self.ctcr
+ }
+ #[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."]
+ #[inline(always)]
+ pub const fn pwmc(&self) -> &Pwmc {
+ &self.pwmc
+ }
+}
+#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
+module"]
+#[doc(alias = "IR")]
+pub type Ir = crate::Reg;
+#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
+pub mod ir;
+#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
+module"]
+#[doc(alias = "TCR")]
+pub type Tcr = crate::Reg;
+#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
+pub mod tcr;
+#[doc = "TC (rw) register accessor: Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`]
+module"]
+#[doc(alias = "TC")]
+pub type Tc = crate::Reg;
+#[doc = "Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
+pub mod tc;
+#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`]
+module"]
+#[doc(alias = "PR")]
+pub type Pr = crate::Reg;
+#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
+pub mod pr;
+#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`]
+module"]
+#[doc(alias = "PC")]
+pub type Pc = crate::Reg;
+#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
+pub mod pc;
+#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
+module"]
+#[doc(alias = "MCR")]
+pub type Mcr = crate::Reg;
+#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
+pub mod mcr;
+#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`]
+module"]
+#[doc(alias = "MR")]
+pub type Mr = crate::Reg;
+#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
+pub mod mr;
+#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
+module"]
+#[doc(alias = "CCR")]
+pub type Ccr = crate::Reg;
+#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
+pub mod ccr;
+#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
+module"]
+#[doc(alias = "CR")]
+pub type Cr = crate::Reg;
+#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
+pub mod cr;
+#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
+module"]
+#[doc(alias = "EMR")]
+pub type Emr = crate::Reg;
+#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\]."]
+pub mod emr;
+#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`]
+module"]
+#[doc(alias = "CTCR")]
+pub type Ctcr = crate::Reg;
+#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
+pub mod ctcr;
+#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`]
+module"]
+#[doc(alias = "PWMC")]
+pub type Pwmc = crate::Reg;
+#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT\\[2:0\\]."]
+pub mod pwmc;
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs
new file mode 100644
index 0000000..3eba3a4
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/ccr.rs
@@ -0,0 +1,409 @@
+#[doc = "Register `CCR` reader"]
+pub type R = crate::R;
+#[doc = "Register `CCR` writer"]
+pub type W = crate::W;
+#[doc = "Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap0re {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap0re) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP0RE` reader - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+pub type Cap0reR = crate::BitReader;
+impl Cap0reR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap0re {
+ match self.bits {
+ true => Cap0re::Enabled,
+ false => Cap0re::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap0re::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap0re::Disabled
+ }
+}
+#[doc = "Field `CAP0RE` writer - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+pub type Cap0reW<'a, REG> = crate::BitWriter<'a, REG, Cap0re>;
+impl<'a, REG> Cap0reW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap0re::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap0re::Disabled)
+ }
+}
+#[doc = "Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap0fe {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap0fe) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP0FE` reader - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+pub type Cap0feR = crate::BitReader;
+impl Cap0feR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap0fe {
+ match self.bits {
+ true => Cap0fe::Enabled,
+ false => Cap0fe::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap0fe::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap0fe::Disabled
+ }
+}
+#[doc = "Field `CAP0FE` writer - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+pub type Cap0feW<'a, REG> = crate::BitWriter<'a, REG, Cap0fe>;
+impl<'a, REG> Cap0feW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap0fe::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap0fe::Disabled)
+ }
+}
+#[doc = "Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap0i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap0i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP0I` reader - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
+pub type Cap0iR = crate::BitReader;
+impl Cap0iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap0i {
+ match self.bits {
+ true => Cap0i::Enabled,
+ false => Cap0i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap0i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap0i::Disabled
+ }
+}
+#[doc = "Field `CAP0I` writer - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
+pub type Cap0iW<'a, REG> = crate::BitWriter<'a, REG, Cap0i>;
+impl<'a, REG> Cap0iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap0i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap0i::Disabled)
+ }
+}
+#[doc = "Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap1re {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap1re) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP1RE` reader - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+pub type Cap1reR = crate::BitReader;
+impl Cap1reR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap1re {
+ match self.bits {
+ true => Cap1re::Enabled,
+ false => Cap1re::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap1re::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap1re::Disabled
+ }
+}
+#[doc = "Field `CAP1RE` writer - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+pub type Cap1reW<'a, REG> = crate::BitWriter<'a, REG, Cap1re>;
+impl<'a, REG> Cap1reW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap1re::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap1re::Disabled)
+ }
+}
+#[doc = "Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap1fe {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap1fe) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP1FE` reader - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+pub type Cap1feR = crate::BitReader;
+impl Cap1feR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap1fe {
+ match self.bits {
+ true => Cap1fe::Enabled,
+ false => Cap1fe::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap1fe::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap1fe::Disabled
+ }
+}
+#[doc = "Field `CAP1FE` writer - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+pub type Cap1feW<'a, REG> = crate::BitWriter<'a, REG, Cap1fe>;
+impl<'a, REG> Cap1feW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap1fe::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap1fe::Disabled)
+ }
+}
+#[doc = "Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Cap1i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Cap1i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `CAP1I` reader - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
+pub type Cap1iR = crate::BitReader;
+impl Cap1iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Cap1i {
+ match self.bits {
+ true => Cap1i::Enabled,
+ false => Cap1i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Cap1i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Cap1i::Disabled
+ }
+}
+#[doc = "Field `CAP1I` writer - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
+pub type Cap1iW<'a, REG> = crate::BitWriter<'a, REG, Cap1i>;
+impl<'a, REG> Cap1iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Cap1i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Cap1i::Disabled)
+ }
+}
+impl R {
+ #[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+ #[inline(always)]
+ pub fn cap0re(&self) -> Cap0reR {
+ Cap0reR::new((self.bits & 1) != 0)
+ }
+ #[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+ #[inline(always)]
+ pub fn cap0fe(&self) -> Cap0feR {
+ Cap0feR::new(((self.bits >> 1) & 1) != 0)
+ }
+ #[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
+ #[inline(always)]
+ pub fn cap0i(&self) -> Cap0iR {
+ Cap0iR::new(((self.bits >> 2) & 1) != 0)
+ }
+ #[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+ #[inline(always)]
+ pub fn cap1re(&self) -> Cap1reR {
+ Cap1reR::new(((self.bits >> 3) & 1) != 0)
+ }
+ #[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+ #[inline(always)]
+ pub fn cap1fe(&self) -> Cap1feR {
+ Cap1feR::new(((self.bits >> 4) & 1) != 0)
+ }
+ #[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
+ #[inline(always)]
+ pub fn cap1i(&self) -> Cap1iR {
+ Cap1iR::new(((self.bits >> 5) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap0re(&mut self) -> Cap0reW {
+ Cap0reW::new(self, 0)
+ }
+ #[doc = "Bit 1 - Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap0fe(&mut self) -> Cap0feW {
+ Cap0feW::new(self, 1)
+ }
+ #[doc = "Bit 2 - Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap0i(&mut self) -> Cap0iW {
+ Cap0iW::new(self, 2)
+ }
+ #[doc = "Bit 3 - Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap1re(&mut self) -> Cap1reW {
+ Cap1reW::new(self, 3)
+ }
+ #[doc = "Bit 4 - Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap1fe(&mut self) -> Cap1feW {
+ Cap1feW::new(self, 4)
+ }
+ #[doc = "Bit 5 - Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cap1i(&mut self) -> Cap1iW {
+ Cap1iW::new(self, 5)
+ }
+}
+#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CcrSpec;
+impl crate::RegisterSpec for CcrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
+impl crate::Readable for CcrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
+impl crate::Writable for CcrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CCR to value 0"]
+impl crate::Resettable for CcrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs
new file mode 100644
index 0000000..0430469
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/cr.rs
@@ -0,0 +1,22 @@
+#[doc = "Register `CR%s` reader"]
+pub type R = crate::R;
+#[doc = "Field `CAP` reader - Timer counter capture value."]
+pub type CapR = crate::FieldReader;
+impl R {
+ #[doc = "Bits 0:15 - Timer counter capture value."]
+ #[inline(always)]
+ pub fn cap(&self) -> CapR {
+ CapR::new((self.bits & 0xffff) as u16)
+ }
+}
+#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CrSpec;
+impl crate::RegisterSpec for CrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`cr::R`](R) reader structure"]
+impl crate::Readable for CrSpec {}
+#[doc = "`reset()` method sets CR%s to value 0"]
+impl crate::Resettable for CrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs
new file mode 100644
index 0000000..d50bbc4
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/ctcr.rs
@@ -0,0 +1,302 @@
+#[doc = "Register `CTCR` reader"]
+pub type R = crate::R;
+#[doc = "Register `CTCR` writer"]
+pub type W = crate::W;
+#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Ctm {
+ #[doc = "0: Increment on every rising PCLK edge"]
+ Timer = 0,
+ #[doc = "1: Increment on rising CAP pin edge"]
+ CounterRising = 1,
+ #[doc = "2: Increment on falling CAP pin edge"]
+ CounterFalling = 2,
+ #[doc = "3: Increment on both CAP pin edges"]
+ CounterBoth = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Ctm) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Ctm {
+ type Ux = u8;
+}
+#[doc = "Field `CTM` reader - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
+pub type CtmR = crate::FieldReader;
+impl CtmR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Ctm {
+ match self.bits {
+ 0 => Ctm::Timer,
+ 1 => Ctm::CounterRising,
+ 2 => Ctm::CounterFalling,
+ 3 => Ctm::CounterBoth,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Increment on every rising PCLK edge"]
+ #[inline(always)]
+ pub fn is_timer(&self) -> bool {
+ *self == Ctm::Timer
+ }
+ #[doc = "Increment on rising CAP pin edge"]
+ #[inline(always)]
+ pub fn is_counter_rising(&self) -> bool {
+ *self == Ctm::CounterRising
+ }
+ #[doc = "Increment on falling CAP pin edge"]
+ #[inline(always)]
+ pub fn is_counter_falling(&self) -> bool {
+ *self == Ctm::CounterFalling
+ }
+ #[doc = "Increment on both CAP pin edges"]
+ #[inline(always)]
+ pub fn is_counter_both(&self) -> bool {
+ *self == Ctm::CounterBoth
+ }
+}
+#[doc = "Field `CTM` writer - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
+pub type CtmW<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Ctm>;
+impl<'a, REG> CtmW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Increment on every rising PCLK edge"]
+ #[inline(always)]
+ pub fn timer(self) -> &'a mut crate::W {
+ self.variant(Ctm::Timer)
+ }
+ #[doc = "Increment on rising CAP pin edge"]
+ #[inline(always)]
+ pub fn counter_rising(self) -> &'a mut crate::W {
+ self.variant(Ctm::CounterRising)
+ }
+ #[doc = "Increment on falling CAP pin edge"]
+ #[inline(always)]
+ pub fn counter_falling(self) -> &'a mut crate::W {
+ self.variant(Ctm::CounterFalling)
+ }
+ #[doc = "Increment on both CAP pin edges"]
+ #[inline(always)]
+ pub fn counter_both(self) -> &'a mut crate::W {
+ self.variant(Ctm::CounterBoth)
+ }
+}
+#[doc = "Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Cis {
+ #[doc = "0: CT16Bn_CAP0"]
+ Ct16bnCap0 = 0,
+ #[doc = "1: CT16Bn_CAP1"]
+ Ct16bnCap1 = 1,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Cis) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Cis {
+ type Ux = u8;
+}
+#[doc = "Field `CIS` reader - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
+pub type CisR = crate::FieldReader;
+impl CisR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Option {
+ match self.bits {
+ 0 => Some(Cis::Ct16bnCap0),
+ 1 => Some(Cis::Ct16bnCap1),
+ _ => None,
+ }
+ }
+ #[doc = "CT16Bn_CAP0"]
+ #[inline(always)]
+ pub fn is_ct16bn_cap0(&self) -> bool {
+ *self == Cis::Ct16bnCap0
+ }
+ #[doc = "CT16Bn_CAP1"]
+ #[inline(always)]
+ pub fn is_ct16bn_cap1(&self) -> bool {
+ *self == Cis::Ct16bnCap1
+ }
+}
+#[doc = "Field `CIS` writer - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
+pub type CisW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cis>;
+impl<'a, REG> CisW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "CT16Bn_CAP0"]
+ #[inline(always)]
+ pub fn ct16bn_cap0(self) -> &'a mut crate::W {
+ self.variant(Cis::Ct16bnCap0)
+ }
+ #[doc = "CT16Bn_CAP1"]
+ #[inline(always)]
+ pub fn ct16bn_cap1(self) -> &'a mut crate::W {
+ self.variant(Cis::Ct16bnCap1)
+ }
+}
+#[doc = "Field `ENCC` reader - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
+pub type EnccR = crate::BitReader;
+#[doc = "Field `ENCC` writer - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
+pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Selcc {
+ #[doc = "0: Rising Edge of CAP0 clears the timer"]
+ Cap0Rising = 0,
+ #[doc = "1: Falling Edge of CAP0 clears the timer"]
+ Cap0Falling = 1,
+ #[doc = "2: Rising Edge of CAP1 clears the timer"]
+ Cap1Rising = 2,
+ #[doc = "3: Falling Edge of CAP1 clears the timer"]
+ Cap1Falling = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Selcc) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Selcc {
+ type Ux = u8;
+}
+#[doc = "Field `SELCC` reader - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
+pub type SelccR = crate::FieldReader;
+impl SelccR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Option {
+ match self.bits {
+ 0 => Some(Selcc::Cap0Rising),
+ 1 => Some(Selcc::Cap0Falling),
+ 2 => Some(Selcc::Cap1Rising),
+ 3 => Some(Selcc::Cap1Falling),
+ _ => None,
+ }
+ }
+ #[doc = "Rising Edge of CAP0 clears the timer"]
+ #[inline(always)]
+ pub fn is_cap0_rising(&self) -> bool {
+ *self == Selcc::Cap0Rising
+ }
+ #[doc = "Falling Edge of CAP0 clears the timer"]
+ #[inline(always)]
+ pub fn is_cap0_falling(&self) -> bool {
+ *self == Selcc::Cap0Falling
+ }
+ #[doc = "Rising Edge of CAP1 clears the timer"]
+ #[inline(always)]
+ pub fn is_cap1_rising(&self) -> bool {
+ *self == Selcc::Cap1Rising
+ }
+ #[doc = "Falling Edge of CAP1 clears the timer"]
+ #[inline(always)]
+ pub fn is_cap1_falling(&self) -> bool {
+ *self == Selcc::Cap1Falling
+ }
+}
+#[doc = "Field `SELCC` writer - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
+pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc>;
+impl<'a, REG> SelccW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Rising Edge of CAP0 clears the timer"]
+ #[inline(always)]
+ pub fn cap0_rising(self) -> &'a mut crate::W {
+ self.variant(Selcc::Cap0Rising)
+ }
+ #[doc = "Falling Edge of CAP0 clears the timer"]
+ #[inline(always)]
+ pub fn cap0_falling(self) -> &'a mut crate::W {
+ self.variant(Selcc::Cap0Falling)
+ }
+ #[doc = "Rising Edge of CAP1 clears the timer"]
+ #[inline(always)]
+ pub fn cap1_rising(self) -> &'a mut crate::W {
+ self.variant(Selcc::Cap1Rising)
+ }
+ #[doc = "Falling Edge of CAP1 clears the timer"]
+ #[inline(always)]
+ pub fn cap1_falling(self) -> &'a mut crate::W {
+ self.variant(Selcc::Cap1Falling)
+ }
+}
+impl R {
+ #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
+ #[inline(always)]
+ pub fn ctm(&self) -> CtmR {
+ CtmR::new((self.bits & 3) as u8)
+ }
+ #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
+ #[inline(always)]
+ pub fn cis(&self) -> CisR {
+ CisR::new(((self.bits >> 2) & 3) as u8)
+ }
+ #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
+ #[inline(always)]
+ pub fn encc(&self) -> EnccR {
+ EnccR::new(((self.bits >> 4) & 1) != 0)
+ }
+ #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
+ #[inline(always)]
+ pub fn selcc(&self) -> SelccR {
+ SelccR::new(((self.bits >> 5) & 7) as u8)
+ }
+}
+impl W {
+ #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn ctm(&mut self) -> CtmW {
+ CtmW::new(self, 0)
+ }
+ #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cis(&mut self) -> CisW {
+ CisW::new(self, 2)
+ }
+ #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
+ #[inline(always)]
+ #[must_use]
+ pub fn encc(&mut self) -> EnccW {
+ EnccW::new(self, 4)
+ }
+ #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
+ #[inline(always)]
+ #[must_use]
+ pub fn selcc(&mut self) -> SelccW {
+ SelccW::new(self, 5)
+ }
+}
+#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtcrSpec;
+impl crate::RegisterSpec for CtcrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"]
+impl crate::Readable for CtcrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"]
+impl crate::Writable for CtcrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTCR to value 0"]
+impl crate::Resettable for CtcrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs
new file mode 100644
index 0000000..038e606
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/emr.rs
@@ -0,0 +1,485 @@
+#[doc = "Register `EMR` reader"]
+pub type R = crate::R;
+#[doc = "Register `EMR` writer"]
+pub type W = crate::W;
+#[doc = "Field `EM0` reader - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em0R = crate::BitReader;
+#[doc = "Field `EM0` writer - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EM1` reader - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em1R = crate::BitReader;
+#[doc = "Field `EM1` writer - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EM2` reader - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
+control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em2R = crate::BitReader;
+#[doc = "Field `EM2` writer - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
+control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+pub type Em2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EM3` reader - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
+control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
+pub type Em3R = crate::BitReader;
+#[doc = "Field `EM3` writer - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
+control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
+pub type Em3W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "External Match Control 0. Determines the functionality of External Match 0.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Emc0 {
+ #[doc = "0: Do Nothing."]
+ DoNothing_ = 0,
+ #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ ClearTheCorrespond = 1,
+ #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ SetTheCorrespondin = 2,
+ #[doc = "3: Toggle the corresponding External Match bit/output."]
+ ToggleTheCorrespon = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Emc0) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Emc0 {
+ type Ux = u8;
+}
+#[doc = "Field `EMC0` reader - External Match Control 0. Determines the functionality of External Match 0."]
+pub type Emc0R = crate::FieldReader;
+impl Emc0R {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Emc0 {
+ match self.bits {
+ 0 => Emc0::DoNothing_,
+ 1 => Emc0::ClearTheCorrespond,
+ 2 => Emc0::SetTheCorrespondin,
+ 3 => Emc0::ToggleTheCorrespon,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn is_do_nothing_(&self) -> bool {
+ *self == Emc0::DoNothing_
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn is_clear_the_correspond(&self) -> bool {
+ *self == Emc0::ClearTheCorrespond
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn is_set_the_correspondin(&self) -> bool {
+ *self == Emc0::SetTheCorrespondin
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn is_toggle_the_correspon(&self) -> bool {
+ *self == Emc0::ToggleTheCorrespon
+ }
+}
+#[doc = "Field `EMC0` writer - External Match Control 0. Determines the functionality of External Match 0."]
+pub type Emc0W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc0>;
+impl<'a, REG> Emc0W<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn do_nothing_(self) -> &'a mut crate::W {
+ self.variant(Emc0::DoNothing_)
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn clear_the_correspond(self) -> &'a mut crate::W {
+ self.variant(Emc0::ClearTheCorrespond)
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn set_the_correspondin(self) -> &'a mut crate::W {
+ self.variant(Emc0::SetTheCorrespondin)
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn toggle_the_correspon(self) -> &'a mut crate::W {
+ self.variant(Emc0::ToggleTheCorrespon)
+ }
+}
+#[doc = "External Match Control 1. Determines the functionality of External Match 1.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Emc1 {
+ #[doc = "0: Do Nothing."]
+ DoNothing_ = 0,
+ #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ ClearTheCorrespond = 1,
+ #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ SetTheCorrespondin = 2,
+ #[doc = "3: Toggle the corresponding External Match bit/output."]
+ ToggleTheCorrespon = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Emc1) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Emc1 {
+ type Ux = u8;
+}
+#[doc = "Field `EMC1` reader - External Match Control 1. Determines the functionality of External Match 1."]
+pub type Emc1R = crate::FieldReader;
+impl Emc1R {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Emc1 {
+ match self.bits {
+ 0 => Emc1::DoNothing_,
+ 1 => Emc1::ClearTheCorrespond,
+ 2 => Emc1::SetTheCorrespondin,
+ 3 => Emc1::ToggleTheCorrespon,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn is_do_nothing_(&self) -> bool {
+ *self == Emc1::DoNothing_
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn is_clear_the_correspond(&self) -> bool {
+ *self == Emc1::ClearTheCorrespond
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn is_set_the_correspondin(&self) -> bool {
+ *self == Emc1::SetTheCorrespondin
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn is_toggle_the_correspon(&self) -> bool {
+ *self == Emc1::ToggleTheCorrespon
+ }
+}
+#[doc = "Field `EMC1` writer - External Match Control 1. Determines the functionality of External Match 1."]
+pub type Emc1W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc1>;
+impl<'a, REG> Emc1W<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn do_nothing_(self) -> &'a mut crate::W {
+ self.variant(Emc1::DoNothing_)
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn clear_the_correspond(self) -> &'a mut crate::W {
+ self.variant(Emc1::ClearTheCorrespond)
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn set_the_correspondin(self) -> &'a mut crate::W {
+ self.variant(Emc1::SetTheCorrespondin)
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn toggle_the_correspon(self) -> &'a mut crate::W {
+ self.variant(Emc1::ToggleTheCorrespon)
+ }
+}
+#[doc = "External Match Control 2. Determines the functionality of External Match 2.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Emc2 {
+ #[doc = "0: Do Nothing."]
+ DoNothing_ = 0,
+ #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ ClearTheCorrespond = 1,
+ #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ SetTheCorrespondin = 2,
+ #[doc = "3: Toggle the corresponding External Match bit/output."]
+ ToggleTheCorrespon = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Emc2) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Emc2 {
+ type Ux = u8;
+}
+#[doc = "Field `EMC2` reader - External Match Control 2. Determines the functionality of External Match 2."]
+pub type Emc2R = crate::FieldReader;
+impl Emc2R {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Emc2 {
+ match self.bits {
+ 0 => Emc2::DoNothing_,
+ 1 => Emc2::ClearTheCorrespond,
+ 2 => Emc2::SetTheCorrespondin,
+ 3 => Emc2::ToggleTheCorrespon,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn is_do_nothing_(&self) -> bool {
+ *self == Emc2::DoNothing_
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn is_clear_the_correspond(&self) -> bool {
+ *self == Emc2::ClearTheCorrespond
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn is_set_the_correspondin(&self) -> bool {
+ *self == Emc2::SetTheCorrespondin
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn is_toggle_the_correspon(&self) -> bool {
+ *self == Emc2::ToggleTheCorrespon
+ }
+}
+#[doc = "Field `EMC2` writer - External Match Control 2. Determines the functionality of External Match 2."]
+pub type Emc2W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc2>;
+impl<'a, REG> Emc2W<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn do_nothing_(self) -> &'a mut crate::W {
+ self.variant(Emc2::DoNothing_)
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn clear_the_correspond(self) -> &'a mut crate::W {
+ self.variant(Emc2::ClearTheCorrespond)
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn set_the_correspondin(self) -> &'a mut crate::W {
+ self.variant(Emc2::SetTheCorrespondin)
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn toggle_the_correspon(self) -> &'a mut crate::W {
+ self.variant(Emc2::ToggleTheCorrespon)
+ }
+}
+#[doc = "External Match Control 3. Determines the functionality of External Match 3.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+#[repr(u8)]
+pub enum Emc3 {
+ #[doc = "0: Do Nothing."]
+ DoNothing_ = 0,
+ #[doc = "1: Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ ClearTheCorrespond = 1,
+ #[doc = "2: Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ SetTheCorrespondin = 2,
+ #[doc = "3: Toggle the corresponding External Match bit/output."]
+ ToggleTheCorrespon = 3,
+}
+impl From for u8 {
+ #[inline(always)]
+ fn from(variant: Emc3) -> Self {
+ variant as _
+ }
+}
+impl crate::FieldSpec for Emc3 {
+ type Ux = u8;
+}
+#[doc = "Field `EMC3` reader - External Match Control 3. Determines the functionality of External Match 3."]
+pub type Emc3R = crate::FieldReader;
+impl Emc3R {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Emc3 {
+ match self.bits {
+ 0 => Emc3::DoNothing_,
+ 1 => Emc3::ClearTheCorrespond,
+ 2 => Emc3::SetTheCorrespondin,
+ 3 => Emc3::ToggleTheCorrespon,
+ _ => unreachable!(),
+ }
+ }
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn is_do_nothing_(&self) -> bool {
+ *self == Emc3::DoNothing_
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn is_clear_the_correspond(&self) -> bool {
+ *self == Emc3::ClearTheCorrespond
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn is_set_the_correspondin(&self) -> bool {
+ *self == Emc3::SetTheCorrespondin
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn is_toggle_the_correspon(&self) -> bool {
+ *self == Emc3::ToggleTheCorrespon
+ }
+}
+#[doc = "Field `EMC3` writer - External Match Control 3. Determines the functionality of External Match 3."]
+pub type Emc3W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, Emc3>;
+impl<'a, REG> Emc3W<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+ REG::Ux: From,
+{
+ #[doc = "Do Nothing."]
+ #[inline(always)]
+ pub fn do_nothing_(self) -> &'a mut crate::W {
+ self.variant(Emc3::DoNothing_)
+ }
+ #[doc = "Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out)."]
+ #[inline(always)]
+ pub fn clear_the_correspond(self) -> &'a mut crate::W {
+ self.variant(Emc3::ClearTheCorrespond)
+ }
+ #[doc = "Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out)."]
+ #[inline(always)]
+ pub fn set_the_correspondin(self) -> &'a mut crate::W {
+ self.variant(Emc3::SetTheCorrespondin)
+ }
+ #[doc = "Toggle the corresponding External Match bit/output."]
+ #[inline(always)]
+ pub fn toggle_the_correspon(self) -> &'a mut crate::W {
+ self.variant(Emc3::ToggleTheCorrespon)
+ }
+}
+impl R {
+ #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ pub fn em0(&self) -> Em0R {
+ Em0R::new((self.bits & 1) != 0)
+ }
+ #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ pub fn em1(&self) -> Em1R {
+ Em1R::new(((self.bits >> 1) & 1) != 0)
+ }
+ #[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
+control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ pub fn em2(&self) -> Em2R {
+ Em2R::new(((self.bits >> 2) & 1) != 0)
+ }
+ #[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
+control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
+ #[inline(always)]
+ pub fn em3(&self) -> Em3R {
+ Em3R::new(((self.bits >> 3) & 1) != 0)
+ }
+ #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
+ #[inline(always)]
+ pub fn emc0(&self) -> Emc0R {
+ Emc0R::new(((self.bits >> 4) & 3) as u8)
+ }
+ #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
+ #[inline(always)]
+ pub fn emc1(&self) -> Emc1R {
+ Emc1R::new(((self.bits >> 6) & 3) as u8)
+ }
+ #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
+ #[inline(always)]
+ pub fn emc2(&self) -> Emc2R {
+ Emc2R::new(((self.bits >> 8) & 3) as u8)
+ }
+ #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
+ #[inline(always)]
+ pub fn emc3(&self) -> Emc3R {
+ Emc3R::new(((self.bits >> 10) & 3) as u8)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[5:4\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn em0(&mut self) -> Em0W {
+ Em0W::new(self, 0)
+ }
+ #[doc = "Bit 1 - External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[7:6\\]
+control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn em1(&mut self) -> Em1W {
+ Em1W::new(self, 1)
+ }
+ #[doc = "Bit 2 - External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[9:8\\]
+control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH)."]
+ #[inline(always)]
+ #[must_use]
+ pub fn em2(&mut self) -> Em2W {
+ Em2W::new(self, 2)
+ }
+ #[doc = "Bit 3 - External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR\\[11:10\\]
+control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers."]
+ #[inline(always)]
+ #[must_use]
+ pub fn em3(&mut self) -> Em3W {
+ Em3W::new(self, 3)
+ }
+ #[doc = "Bits 4:5 - External Match Control 0. Determines the functionality of External Match 0."]
+ #[inline(always)]
+ #[must_use]
+ pub fn emc0(&mut self) -> Emc0W {
+ Emc0W::new(self, 4)
+ }
+ #[doc = "Bits 6:7 - External Match Control 1. Determines the functionality of External Match 1."]
+ #[inline(always)]
+ #[must_use]
+ pub fn emc1(&mut self) -> Emc1W {
+ Emc1W::new(self, 6)
+ }
+ #[doc = "Bits 8:9 - External Match Control 2. Determines the functionality of External Match 2."]
+ #[inline(always)]
+ #[must_use]
+ pub fn emc2(&mut self) -> Emc2W {
+ Emc2W::new(self, 8)
+ }
+ #[doc = "Bits 10:11 - External Match Control 3. Determines the functionality of External Match 3."]
+ #[inline(always)]
+ #[must_use]
+ pub fn emc3(&mut self) -> Emc3W {
+ Emc3W::new(self, 10)
+ }
+}
+#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT\\[2:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EmrSpec;
+impl crate::RegisterSpec for EmrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`emr::R`](R) reader structure"]
+impl crate::Readable for EmrSpec {}
+#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"]
+impl crate::Writable for EmrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets EMR to value 0"]
+impl crate::Resettable for EmrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs b/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs
new file mode 100644
index 0000000..ba6862b
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/ir.rs
@@ -0,0 +1,115 @@
+#[doc = "Register `IR` reader"]
+pub type R = crate::R;
+#[doc = "Register `IR` writer"]
+pub type W = crate::W;
+#[doc = "Field `MR0INT` reader - Interrupt flag for match channel 0."]
+pub type Mr0intR = crate::BitReader;
+#[doc = "Field `MR0INT` writer - Interrupt flag for match channel 0."]
+pub type Mr0intW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MR1INT` reader - Interrupt flag for match channel 1."]
+pub type Mr1intR = crate::BitReader;
+#[doc = "Field `MR1INT` writer - Interrupt flag for match channel 1."]
+pub type Mr1intW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MR2INT` reader - Interrupt flag for match channel 2."]
+pub type Mr2intR = crate::BitReader;
+#[doc = "Field `MR2INT` writer - Interrupt flag for match channel 2."]
+pub type Mr2intW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MR3INT` reader - Interrupt flag for match channel 3."]
+pub type Mr3intR = crate::BitReader;
+#[doc = "Field `MR3INT` writer - Interrupt flag for match channel 3."]
+pub type Mr3intW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CR0INT` reader - Interrupt flag for capture channel 0 event."]
+pub type Cr0intR = crate::BitReader;
+#[doc = "Field `CR0INT` writer - Interrupt flag for capture channel 0 event."]
+pub type Cr0intW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CR1INT` reader - Interrupt flag for capture channel 1 event."]
+pub type Cr1intR = crate::BitReader;
+#[doc = "Field `CR1INT` writer - Interrupt flag for capture channel 1 event."]
+pub type Cr1intW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+ #[doc = "Bit 0 - Interrupt flag for match channel 0."]
+ #[inline(always)]
+ pub fn mr0int(&self) -> Mr0intR {
+ Mr0intR::new((self.bits & 1) != 0)
+ }
+ #[doc = "Bit 1 - Interrupt flag for match channel 1."]
+ #[inline(always)]
+ pub fn mr1int(&self) -> Mr1intR {
+ Mr1intR::new(((self.bits >> 1) & 1) != 0)
+ }
+ #[doc = "Bit 2 - Interrupt flag for match channel 2."]
+ #[inline(always)]
+ pub fn mr2int(&self) -> Mr2intR {
+ Mr2intR::new(((self.bits >> 2) & 1) != 0)
+ }
+ #[doc = "Bit 3 - Interrupt flag for match channel 3."]
+ #[inline(always)]
+ pub fn mr3int(&self) -> Mr3intR {
+ Mr3intR::new(((self.bits >> 3) & 1) != 0)
+ }
+ #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
+ #[inline(always)]
+ pub fn cr0int(&self) -> Cr0intR {
+ Cr0intR::new(((self.bits >> 4) & 1) != 0)
+ }
+ #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
+ #[inline(always)]
+ pub fn cr1int(&self) -> Cr1intR {
+ Cr1intR::new(((self.bits >> 5) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Interrupt flag for match channel 0."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr0int(&mut self) -> Mr0intW {
+ Mr0intW::new(self, 0)
+ }
+ #[doc = "Bit 1 - Interrupt flag for match channel 1."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr1int(&mut self) -> Mr1intW {
+ Mr1intW::new(self, 1)
+ }
+ #[doc = "Bit 2 - Interrupt flag for match channel 2."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr2int(&mut self) -> Mr2intW {
+ Mr2intW::new(self, 2)
+ }
+ #[doc = "Bit 3 - Interrupt flag for match channel 3."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr3int(&mut self) -> Mr3intW {
+ Mr3intW::new(self, 3)
+ }
+ #[doc = "Bit 4 - Interrupt flag for capture channel 0 event."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cr0int(&mut self) -> Cr0intW {
+ Cr0intW::new(self, 4)
+ }
+ #[doc = "Bit 5 - Interrupt flag for capture channel 1 event."]
+ #[inline(always)]
+ #[must_use]
+ pub fn cr1int(&mut self) -> Cr1intW {
+ Cr1intW::new(self, 5)
+ }
+}
+#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrSpec;
+impl crate::RegisterSpec for IrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`ir::R`](R) reader structure"]
+impl crate::Readable for IrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
+impl crate::Writable for IrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IR to value 0"]
+impl crate::Resettable for IrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs
new file mode 100644
index 0000000..89ad4d2
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/mcr.rs
@@ -0,0 +1,813 @@
+#[doc = "Register `MCR` reader"]
+pub type R = crate::R;
+#[doc = "Register `MCR` writer"]
+pub type W = crate::W;
+#[doc = "Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr0i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr0i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR0I` reader - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
+pub type Mr0iR = crate::BitReader;
+impl Mr0iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr0i {
+ match self.bits {
+ true => Mr0i::Enabled,
+ false => Mr0i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr0i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr0i::Disabled
+ }
+}
+#[doc = "Field `MR0I` writer - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
+pub type Mr0iW<'a, REG> = crate::BitWriter<'a, REG, Mr0i>;
+impl<'a, REG> Mr0iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr0i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr0i::Disabled)
+ }
+}
+#[doc = "Reset on MR0: the TC will be reset if MR0 matches it.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr0r {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr0r) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR0R` reader - Reset on MR0: the TC will be reset if MR0 matches it."]
+pub type Mr0rR = crate::BitReader;
+impl Mr0rR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr0r {
+ match self.bits {
+ true => Mr0r::Enabled,
+ false => Mr0r::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr0r::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr0r::Disabled
+ }
+}
+#[doc = "Field `MR0R` writer - Reset on MR0: the TC will be reset if MR0 matches it."]
+pub type Mr0rW<'a, REG> = crate::BitWriter<'a, REG, Mr0r>;
+impl<'a, REG> Mr0rW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr0r::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr0r::Disabled)
+ }
+}
+#[doc = "Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR0 matches the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr0s {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr0s) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR0S` reader - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR0 matches the TC."]
+pub type Mr0sR = crate::BitReader;
+impl Mr0sR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr0s {
+ match self.bits {
+ true => Mr0s::Enabled,
+ false => Mr0s::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr0s::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr0s::Disabled
+ }
+}
+#[doc = "Field `MR0S` writer - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR0 matches the TC."]
+pub type Mr0sW<'a, REG> = crate::BitWriter<'a, REG, Mr0s>;
+impl<'a, REG> Mr0sW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr0s::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr0s::Disabled)
+ }
+}
+#[doc = "Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr1i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr1i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR1I` reader - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
+pub type Mr1iR = crate::BitReader;
+impl Mr1iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr1i {
+ match self.bits {
+ true => Mr1i::Enabled,
+ false => Mr1i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr1i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr1i::Disabled
+ }
+}
+#[doc = "Field `MR1I` writer - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
+pub type Mr1iW<'a, REG> = crate::BitWriter<'a, REG, Mr1i>;
+impl<'a, REG> Mr1iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr1i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr1i::Disabled)
+ }
+}
+#[doc = "Reset on MR1: the TC will be reset if MR1 matches it.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr1r {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr1r) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR1R` reader - Reset on MR1: the TC will be reset if MR1 matches it."]
+pub type Mr1rR = crate::BitReader;
+impl Mr1rR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr1r {
+ match self.bits {
+ true => Mr1r::Enabled,
+ false => Mr1r::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr1r::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr1r::Disabled
+ }
+}
+#[doc = "Field `MR1R` writer - Reset on MR1: the TC will be reset if MR1 matches it."]
+pub type Mr1rW<'a, REG> = crate::BitWriter<'a, REG, Mr1r>;
+impl<'a, REG> Mr1rW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr1r::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr1r::Disabled)
+ }
+}
+#[doc = "Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR1 matches the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr1s {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr1s) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR1S` reader - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR1 matches the TC."]
+pub type Mr1sR = crate::BitReader;
+impl Mr1sR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr1s {
+ match self.bits {
+ true => Mr1s::Enabled,
+ false => Mr1s::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr1s::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr1s::Disabled
+ }
+}
+#[doc = "Field `MR1S` writer - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR1 matches the TC."]
+pub type Mr1sW<'a, REG> = crate::BitWriter<'a, REG, Mr1s>;
+impl<'a, REG> Mr1sW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr1s::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr1s::Disabled)
+ }
+}
+#[doc = "Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr2i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr2i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR2I` reader - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
+pub type Mr2iR = crate::BitReader;
+impl Mr2iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr2i {
+ match self.bits {
+ true => Mr2i::Enabled,
+ false => Mr2i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr2i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr2i::Disabled
+ }
+}
+#[doc = "Field `MR2I` writer - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
+pub type Mr2iW<'a, REG> = crate::BitWriter<'a, REG, Mr2i>;
+impl<'a, REG> Mr2iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr2i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr2i::Disabled)
+ }
+}
+#[doc = "Reset on MR2: the TC will be reset if MR2 matches it.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr2r {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr2r) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR2R` reader - Reset on MR2: the TC will be reset if MR2 matches it."]
+pub type Mr2rR = crate::BitReader;
+impl Mr2rR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr2r {
+ match self.bits {
+ true => Mr2r::Enabled,
+ false => Mr2r::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr2r::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr2r::Disabled
+ }
+}
+#[doc = "Field `MR2R` writer - Reset on MR2: the TC will be reset if MR2 matches it."]
+pub type Mr2rW<'a, REG> = crate::BitWriter<'a, REG, Mr2r>;
+impl<'a, REG> Mr2rW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr2r::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr2r::Disabled)
+ }
+}
+#[doc = "Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR2 matches the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr2s {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr2s) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR2S` reader - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR2 matches the TC."]
+pub type Mr2sR = crate::BitReader;
+impl Mr2sR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr2s {
+ match self.bits {
+ true => Mr2s::Enabled,
+ false => Mr2s::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr2s::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr2s::Disabled
+ }
+}
+#[doc = "Field `MR2S` writer - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR2 matches the TC."]
+pub type Mr2sW<'a, REG> = crate::BitWriter<'a, REG, Mr2s>;
+impl<'a, REG> Mr2sW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr2s::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr2s::Disabled)
+ }
+}
+#[doc = "Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr3i {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr3i) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR3I` reader - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
+pub type Mr3iR = crate::BitReader;
+impl Mr3iR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr3i {
+ match self.bits {
+ true => Mr3i::Enabled,
+ false => Mr3i::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr3i::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr3i::Disabled
+ }
+}
+#[doc = "Field `MR3I` writer - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
+pub type Mr3iW<'a, REG> = crate::BitWriter<'a, REG, Mr3i>;
+impl<'a, REG> Mr3iW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr3i::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr3i::Disabled)
+ }
+}
+#[doc = "Reset on MR3: the TC will be reset if MR3 matches it.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr3r {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr3r) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR3R` reader - Reset on MR3: the TC will be reset if MR3 matches it."]
+pub type Mr3rR = crate::BitReader;
+impl Mr3rR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr3r {
+ match self.bits {
+ true => Mr3r::Enabled,
+ false => Mr3r::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr3r::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr3r::Disabled
+ }
+}
+#[doc = "Field `MR3R` writer - Reset on MR3: the TC will be reset if MR3 matches it."]
+pub type Mr3rW<'a, REG> = crate::BitWriter<'a, REG, Mr3r>;
+impl<'a, REG> Mr3rW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr3r::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr3r::Disabled)
+ }
+}
+#[doc = "Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR3 matches the TC.\n\nValue on reset: 0"]
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum Mr3s {
+ #[doc = "1: Enabled"]
+ Enabled = 1,
+ #[doc = "0: Disabled"]
+ Disabled = 0,
+}
+impl From for bool {
+ #[inline(always)]
+ fn from(variant: Mr3s) -> Self {
+ variant as u8 != 0
+ }
+}
+#[doc = "Field `MR3S` reader - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR3 matches the TC."]
+pub type Mr3sR = crate::BitReader;
+impl Mr3sR {
+ #[doc = "Get enumerated values variant"]
+ #[inline(always)]
+ pub const fn variant(&self) -> Mr3s {
+ match self.bits {
+ true => Mr3s::Enabled,
+ false => Mr3s::Disabled,
+ }
+ }
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn is_enabled(&self) -> bool {
+ *self == Mr3s::Enabled
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn is_disabled(&self) -> bool {
+ *self == Mr3s::Disabled
+ }
+}
+#[doc = "Field `MR3S` writer - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR3 matches the TC."]
+pub type Mr3sW<'a, REG> = crate::BitWriter<'a, REG, Mr3s>;
+impl<'a, REG> Mr3sW<'a, REG>
+where
+ REG: crate::Writable + crate::RegisterSpec,
+{
+ #[doc = "Enabled"]
+ #[inline(always)]
+ pub fn enabled(self) -> &'a mut crate::W {
+ self.variant(Mr3s::Enabled)
+ }
+ #[doc = "Disabled"]
+ #[inline(always)]
+ pub fn disabled(self) -> &'a mut crate::W {
+ self.variant(Mr3s::Disabled)
+ }
+}
+impl R {
+ #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
+ #[inline(always)]
+ pub fn mr0i(&self) -> Mr0iR {
+ Mr0iR::new((self.bits & 1) != 0)
+ }
+ #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
+ #[inline(always)]
+ pub fn mr0r(&self) -> Mr0rR {
+ Mr0rR::new(((self.bits >> 1) & 1) != 0)
+ }
+ #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR0 matches the TC."]
+ #[inline(always)]
+ pub fn mr0s(&self) -> Mr0sR {
+ Mr0sR::new(((self.bits >> 2) & 1) != 0)
+ }
+ #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
+ #[inline(always)]
+ pub fn mr1i(&self) -> Mr1iR {
+ Mr1iR::new(((self.bits >> 3) & 1) != 0)
+ }
+ #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
+ #[inline(always)]
+ pub fn mr1r(&self) -> Mr1rR {
+ Mr1rR::new(((self.bits >> 4) & 1) != 0)
+ }
+ #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR1 matches the TC."]
+ #[inline(always)]
+ pub fn mr1s(&self) -> Mr1sR {
+ Mr1sR::new(((self.bits >> 5) & 1) != 0)
+ }
+ #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
+ #[inline(always)]
+ pub fn mr2i(&self) -> Mr2iR {
+ Mr2iR::new(((self.bits >> 6) & 1) != 0)
+ }
+ #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
+ #[inline(always)]
+ pub fn mr2r(&self) -> Mr2rR {
+ Mr2rR::new(((self.bits >> 7) & 1) != 0)
+ }
+ #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR2 matches the TC."]
+ #[inline(always)]
+ pub fn mr2s(&self) -> Mr2sR {
+ Mr2sR::new(((self.bits >> 8) & 1) != 0)
+ }
+ #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
+ #[inline(always)]
+ pub fn mr3i(&self) -> Mr3iR {
+ Mr3iR::new(((self.bits >> 9) & 1) != 0)
+ }
+ #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
+ #[inline(always)]
+ pub fn mr3r(&self) -> Mr3rR {
+ Mr3rR::new(((self.bits >> 10) & 1) != 0)
+ }
+ #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR3 matches the TC."]
+ #[inline(always)]
+ pub fn mr3s(&self) -> Mr3sR {
+ Mr3sR::new(((self.bits >> 11) & 1) != 0)
+ }
+}
+impl W {
+ #[doc = "Bit 0 - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr0i(&mut self) -> Mr0iW {
+ Mr0iW::new(self, 0)
+ }
+ #[doc = "Bit 1 - Reset on MR0: the TC will be reset if MR0 matches it."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr0r(&mut self) -> Mr0rW {
+ Mr0rW::new(self, 1)
+ }
+ #[doc = "Bit 2 - Stop on MR0: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR0 matches the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr0s(&mut self) -> Mr0sW {
+ Mr0sW::new(self, 2)
+ }
+ #[doc = "Bit 3 - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr1i(&mut self) -> Mr1iW {
+ Mr1iW::new(self, 3)
+ }
+ #[doc = "Bit 4 - Reset on MR1: the TC will be reset if MR1 matches it."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr1r(&mut self) -> Mr1rW {
+ Mr1rW::new(self, 4)
+ }
+ #[doc = "Bit 5 - Stop on MR1: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR1 matches the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr1s(&mut self) -> Mr1sW {
+ Mr1sW::new(self, 5)
+ }
+ #[doc = "Bit 6 - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr2i(&mut self) -> Mr2iW {
+ Mr2iW::new(self, 6)
+ }
+ #[doc = "Bit 7 - Reset on MR2: the TC will be reset if MR2 matches it."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr2r(&mut self) -> Mr2rW {
+ Mr2rW::new(self, 7)
+ }
+ #[doc = "Bit 8 - Stop on MR2: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR2 matches the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr2s(&mut self) -> Mr2sW {
+ Mr2sW::new(self, 8)
+ }
+ #[doc = "Bit 9 - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr3i(&mut self) -> Mr3iW {
+ Mr3iW::new(self, 9)
+ }
+ #[doc = "Bit 10 - Reset on MR3: the TC will be reset if MR3 matches it."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr3r(&mut self) -> Mr3rW {
+ Mr3rW::new(self, 10)
+ }
+ #[doc = "Bit 11 - Stop on MR3: the TC and PC will be stopped and TCR\\[0\\]
+will be set to 0 if MR3 matches the TC."]
+ #[inline(always)]
+ #[must_use]
+ pub fn mr3s(&mut self) -> Mr3sW {
+ Mr3sW::new(self, 11)
+ }
+}
+#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct McrSpec;
+impl crate::RegisterSpec for McrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`mcr::R`](R) reader structure"]
+impl crate::Readable for McrSpec {}
+#[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
+impl crate::Writable for McrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MCR to value 0"]
+impl crate::Resettable for McrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs
new file mode 100644
index 0000000..29b4f01
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/mr.rs
@@ -0,0 +1,40 @@
+#[doc = "Register `MR%s` reader"]
+pub type R = crate::R;
+#[doc = "Register `MR%s` writer"]
+pub type W = crate::W;
+#[doc = "Field `MATCH` reader - Timer counter match value."]
+pub type MatchR = crate::FieldReader;
+#[doc = "Field `MATCH` writer - Timer counter match value."]
+pub type MatchW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+ #[doc = "Bits 0:15 - Timer counter match value."]
+ #[inline(always)]
+ pub fn match_(&self) -> MatchR {
+ MatchR::new((self.bits & 0xffff) as u16)
+ }
+}
+impl W {
+ #[doc = "Bits 0:15 - Timer counter match value."]
+ #[inline(always)]
+ #[must_use]
+ pub fn match_(&mut self) -> MatchW {
+ MatchW::new(self, 0)
+ }
+}
+#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MrSpec;
+impl crate::RegisterSpec for MrSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`mr::R`](R) reader structure"]
+impl crate::Readable for MrSpec {}
+#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"]
+impl crate::Writable for MrSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MR%s to value 0"]
+impl crate::Resettable for MrSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs b/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs
new file mode 100644
index 0000000..e1664ca
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/pc.rs
@@ -0,0 +1,40 @@
+#[doc = "Register `PC` reader"]
+pub type R = crate::R;
+#[doc = "Register `PC` writer"]
+pub type W = crate::W;
+#[doc = "Field `PC` reader - Prescale counter value."]
+pub type PcR = crate::FieldReader;
+#[doc = "Field `PC` writer - Prescale counter value."]
+pub type PcW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+impl R {
+ #[doc = "Bits 0:15 - Prescale counter value."]
+ #[inline(always)]
+ pub fn pc(&self) -> PcR {
+ PcR::new((self.bits & 0xffff) as u16)
+ }
+}
+impl W {
+ #[doc = "Bits 0:15 - Prescale counter value."]
+ #[inline(always)]
+ #[must_use]
+ pub fn pc(&mut self) -> PcW {
+ PcW::new(self, 0)
+ }
+}
+#[doc = "Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PcSpec;
+impl crate::RegisterSpec for PcSpec {
+ type Ux = u32;
+}
+#[doc = "`read()` method returns [`pc::R`](R) reader structure"]
+impl crate::Readable for PcSpec {}
+#[doc = "`write(|w| ..)` method takes [`pc::W`](W) writer structure"]
+impl crate::Writable for PcSpec {
+ type Safety = crate::Unsafe;
+ const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+ const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PC to value 0"]
+impl crate::Resettable for PcSpec {
+ const RESET_VALUE: u32 = 0;
+}
diff --git a/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs b/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs
new file mode 100644
index 0000000..6b0f858
--- /dev/null
+++ b/rust-embedded/lpc111x-pac/src/ct16b0/pr.rs
@@ -0,0 +1,40 @@
+#[doc = "Register `PR` reader"]
+pub type R = crate::R;
+#[doc = "Register `PR` writer"]
+pub type W = crate::W