165 lines
14 KiB
Rust
165 lines
14 KiB
Rust
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#[repr(C)]
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#[doc = "Register block"]
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pub struct RegisterBlock {
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ir: Ir,
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tcr: Tcr,
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tc: Tc,
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pr: Pr,
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pc: Pc,
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mcr: Mcr,
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mr: [Mr; 4],
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ccr: Ccr,
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cr: [Cr; 2],
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_reserved9: [u8; 0x08],
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emr: Emr,
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_reserved10: [u8; 0x30],
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ctcr: Ctcr,
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pwmc: Pwmc,
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}
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impl RegisterBlock {
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#[doc = "0x00 - Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
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#[inline(always)]
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pub const fn ir(&self) -> &Ir {
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&self.ir
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}
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#[doc = "0x04 - Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
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#[inline(always)]
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pub const fn tcr(&self) -> &Tcr {
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&self.tcr
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}
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#[doc = "0x08 - Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
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#[inline(always)]
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pub const fn tc(&self) -> &Tc {
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&self.tc
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}
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#[doc = "0x0c - Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
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#[inline(always)]
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pub const fn pr(&self) -> &Pr {
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&self.pr
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}
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#[doc = "0x10 - Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
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#[inline(always)]
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pub const fn pc(&self) -> &Pc {
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&self.pc
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}
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#[doc = "0x14 - Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
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#[inline(always)]
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pub const fn mcr(&self) -> &Mcr {
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&self.mcr
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}
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#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
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#[inline(always)]
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pub const fn mr(&self, n: usize) -> &Mr {
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&self.mr[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x18..0x28 - Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
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#[inline(always)]
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pub fn mr_iter(&self) -> impl Iterator<Item = &Mr> {
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self.mr.iter()
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}
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#[doc = "0x28 - Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
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#[inline(always)]
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pub const fn ccr(&self) -> &Ccr {
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&self.ccr
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}
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#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
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#[inline(always)]
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pub const fn cr(&self, n: usize) -> &Cr {
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&self.cr[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x2c..0x34 - Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
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#[inline(always)]
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pub fn cr_iter(&self) -> impl Iterator<Item = &Cr> {
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self.cr.iter()
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}
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#[doc = "0x3c - External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."]
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#[inline(always)]
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pub const fn emr(&self) -> &Emr {
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&self.emr
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}
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#[doc = "0x70 - Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
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#[inline(always)]
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pub const fn ctcr(&self) -> &Ctcr {
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&self.ctcr
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}
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#[doc = "0x74 - PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."]
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#[inline(always)]
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pub const fn pwmc(&self) -> &Pwmc {
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&self.pwmc
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}
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}
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#[doc = "IR (rw) register accessor: Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
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module"]
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#[doc(alias = "IR")]
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pub type Ir = crate::Reg<ir::IrSpec>;
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#[doc = "Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending."]
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pub mod ir;
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#[doc = "TCR (rw) register accessor: Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
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module"]
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#[doc(alias = "TCR")]
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pub type Tcr = crate::Reg<tcr::TcrSpec>;
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#[doc = "Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
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pub mod tcr;
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#[doc = "TC (rw) register accessor: Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`]
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module"]
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#[doc(alias = "TC")]
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pub type Tc = crate::Reg<tc::TcSpec>;
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#[doc = "Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR."]
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pub mod tc;
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#[doc = "PR (rw) register accessor: Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`]
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module"]
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#[doc(alias = "PR")]
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pub type Pr = crate::Reg<pr::PrSpec>;
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#[doc = "Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC."]
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pub mod pr;
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#[doc = "PC (rw) register accessor: Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`]
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module"]
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#[doc(alias = "PC")]
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pub type Pc = crate::Reg<pc::PcSpec>;
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#[doc = "Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
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pub mod pc;
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#[doc = "MCR (rw) register accessor: Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
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module"]
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#[doc(alias = "MCR")]
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pub type Mcr = crate::Reg<mcr::McrSpec>;
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#[doc = "Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
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pub mod mcr;
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#[doc = "MR (rw) register accessor: Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`]
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module"]
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#[doc(alias = "MR")]
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pub type Mr = crate::Reg<mr::MrSpec>;
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#[doc = "Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
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pub mod mr;
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#[doc = "CCR (rw) register accessor: Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
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module"]
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#[doc(alias = "CCR")]
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pub type Ccr = crate::Reg<ccr::CcrSpec>;
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#[doc = "Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
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pub mod ccr;
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#[doc = "CR (r) register accessor: Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
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module"]
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#[doc(alias = "CR")]
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pub type Cr = crate::Reg<cr::CrSpec>;
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#[doc = "Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input."]
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pub mod cr;
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#[doc = "EMR (rw) register accessor: External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
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module"]
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#[doc(alias = "EMR")]
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pub type Emr = crate::Reg<emr::EmrSpec>;
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#[doc = "External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT\\[3:0\\]."]
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pub mod emr;
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#[doc = "CTCR (rw) register accessor: Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`]
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module"]
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#[doc(alias = "CTCR")]
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pub type Ctcr = crate::Reg<ctcr::CtcrSpec>;
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#[doc = "Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
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pub mod ctcr;
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#[doc = "PWMC (rw) register accessor: PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\].\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`]
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module"]
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#[doc(alias = "PWMC")]
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pub type Pwmc = crate::Reg<pwmc::PwmcSpec>;
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#[doc = "PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT\\[3:0\\]."]
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pub mod pwmc;
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