221 lines
12 KiB
Rust
221 lines
12 KiB
Rust
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#[doc = "Register `STARTAPRP0` reader"]
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pub type R = crate::R<Startaprp0Spec>;
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#[doc = "Register `STARTAPRP0` writer"]
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pub type W = crate::W<Startaprp0Spec>;
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#[doc = "Field `APRPIO0_0` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_0R = crate::BitReader;
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#[doc = "Field `APRPIO0_0` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_0W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_1` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_1R = crate::BitReader;
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#[doc = "Field `APRPIO0_1` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_1W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_2` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_2R = crate::BitReader;
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#[doc = "Field `APRPIO0_2` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_2W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_3` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_3R = crate::BitReader;
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#[doc = "Field `APRPIO0_3` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_3W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_4` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_4R = crate::BitReader;
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#[doc = "Field `APRPIO0_4` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_4W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_5` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_5R = crate::BitReader;
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#[doc = "Field `APRPIO0_5` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_5W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_6` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_6R = crate::BitReader;
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#[doc = "Field `APRPIO0_6` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_6W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_7` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_7R = crate::BitReader;
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#[doc = "Field `APRPIO0_7` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_7W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_8` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_8R = crate::BitReader;
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#[doc = "Field `APRPIO0_8` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_8W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_9` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_9R = crate::BitReader;
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#[doc = "Field `APRPIO0_9` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_9W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_10` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_10R = crate::BitReader;
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#[doc = "Field `APRPIO0_10` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_10W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO0_11` reader - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_11R = crate::BitReader;
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#[doc = "Field `APRPIO0_11` writer - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio0_11W<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `APRPIO1_0` reader - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio1_0R = crate::BitReader;
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#[doc = "Field `APRPIO1_0` writer - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"]
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pub type Aprpio1_0W<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_0(&self) -> Aprpio0_0R {
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Aprpio0_0R::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_1(&self) -> Aprpio0_1R {
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Aprpio0_1R::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_2(&self) -> Aprpio0_2R {
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Aprpio0_2R::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_3(&self) -> Aprpio0_3R {
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Aprpio0_3R::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_4(&self) -> Aprpio0_4R {
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Aprpio0_4R::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_5(&self) -> Aprpio0_5R {
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Aprpio0_5R::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 6 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_6(&self) -> Aprpio0_6R {
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Aprpio0_6R::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_7(&self) -> Aprpio0_7R {
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Aprpio0_7R::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bit 8 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_8(&self) -> Aprpio0_8R {
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Aprpio0_8R::new(((self.bits >> 8) & 1) != 0)
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}
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#[doc = "Bit 9 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_9(&self) -> Aprpio0_9R {
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Aprpio0_9R::new(((self.bits >> 9) & 1) != 0)
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}
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#[doc = "Bit 10 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_10(&self) -> Aprpio0_10R {
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Aprpio0_10R::new(((self.bits >> 10) & 1) != 0)
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}
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#[doc = "Bit 11 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio0_11(&self) -> Aprpio0_11R {
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Aprpio0_11R::new(((self.bits >> 11) & 1) != 0)
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}
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#[doc = "Bit 12 - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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pub fn aprpio1_0(&self) -> Aprpio1_0R {
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Aprpio1_0R::new(((self.bits >> 12) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_0(&mut self) -> Aprpio0_0W<Startaprp0Spec> {
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Aprpio0_0W::new(self, 0)
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}
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#[doc = "Bit 1 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_1(&mut self) -> Aprpio0_1W<Startaprp0Spec> {
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Aprpio0_1W::new(self, 1)
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}
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#[doc = "Bit 2 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_2(&mut self) -> Aprpio0_2W<Startaprp0Spec> {
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Aprpio0_2W::new(self, 2)
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}
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#[doc = "Bit 3 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_3(&mut self) -> Aprpio0_3W<Startaprp0Spec> {
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Aprpio0_3W::new(self, 3)
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}
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#[doc = "Bit 4 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_4(&mut self) -> Aprpio0_4W<Startaprp0Spec> {
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Aprpio0_4W::new(self, 4)
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}
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#[doc = "Bit 5 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_5(&mut self) -> Aprpio0_5W<Startaprp0Spec> {
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Aprpio0_5W::new(self, 5)
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}
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#[doc = "Bit 6 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_6(&mut self) -> Aprpio0_6W<Startaprp0Spec> {
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Aprpio0_6W::new(self, 6)
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}
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#[doc = "Bit 7 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_7(&mut self) -> Aprpio0_7W<Startaprp0Spec> {
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Aprpio0_7W::new(self, 7)
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}
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#[doc = "Bit 8 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_8(&mut self) -> Aprpio0_8W<Startaprp0Spec> {
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Aprpio0_8W::new(self, 8)
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}
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#[doc = "Bit 9 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_9(&mut self) -> Aprpio0_9W<Startaprp0Spec> {
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Aprpio0_9W::new(self, 9)
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}
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#[doc = "Bit 10 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_10(&mut self) -> Aprpio0_10W<Startaprp0Spec> {
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Aprpio0_10W::new(self, 10)
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}
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#[doc = "Bit 11 - Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio0_11(&mut self) -> Aprpio0_11W<Startaprp0Spec> {
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Aprpio0_11W::new(self, 11)
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}
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#[doc = "Bit 12 - Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge"]
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#[inline(always)]
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#[must_use]
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pub fn aprpio1_0(&mut self) -> Aprpio1_0W<Startaprp0Spec> {
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Aprpio1_0W::new(self, 12)
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}
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}
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#[doc = "Start logic edge control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`startaprp0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`startaprp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Startaprp0Spec;
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impl crate::RegisterSpec for Startaprp0Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`startaprp0::R`](R) reader structure"]
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impl crate::Readable for Startaprp0Spec {}
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#[doc = "`write(|w| ..)` method takes [`startaprp0::W`](W) writer structure"]
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impl crate::Writable for Startaprp0Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets STARTAPRP0 to value 0"]
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impl crate::Resettable for Startaprp0Spec {
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const RESET_VALUE: u32 = 0;
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}
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