162 lines
5 KiB
C++
162 lines
5 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <bit>
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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static Id StorageIndex(EmitContext& ctx, const IR::Value& offset, size_t element_size) {
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if (offset.IsImmediate()) {
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const u32 imm_offset{static_cast<u32>(offset.U32() / element_size)};
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return ctx.Constant(ctx.U32[1], imm_offset);
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}
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const u32 shift{static_cast<u32>(std::countr_zero(element_size))};
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const Id index{ctx.Def(offset)};
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if (shift == 0) {
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return index;
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}
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const Id shift_id{ctx.Constant(ctx.U32[1], shift)};
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return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id);
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}
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void EmitLoadGlobalU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobalS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobal32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobal64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadGlobal128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobalS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobal32(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobal64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteGlobal128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadStorageU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadStorageS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadStorageU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadStorageS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
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if (!binding.IsImmediate()) {
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throw NotImplementedException("Dynamic storage buffer indexing");
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}
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const Id ssbo{ctx.ssbos[binding.U32()]};
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const Id index{StorageIndex(ctx, offset, sizeof(u32))};
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const Id pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, index)};
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return ctx.OpLoad(ctx.U32[1], pointer);
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}
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void EmitLoadStorage64(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitLoadStorage128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteStorageU8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteStorageS8(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteStorageU16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteStorageS16(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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if (!binding.IsImmediate()) {
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throw NotImplementedException("Dynamic storage buffer indexing");
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}
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const Id ssbo{ctx.ssbos[binding.U32()]};
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const Id index{StorageIndex(ctx, offset, sizeof(u32))};
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const Id pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, index)};
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ctx.OpStore(pointer, value);
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}
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void EmitWriteStorage64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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if (!binding.IsImmediate()) {
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throw NotImplementedException("Dynamic storage buffer indexing");
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}
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// TODO: Support reinterpreting bindings, guaranteed to be aligned
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const Id ssbo{ctx.ssbos[binding.U32()]};
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const Id low_index{StorageIndex(ctx, offset, sizeof(u32))};
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const Id high_index{ctx.OpIAdd(ctx.U32[1], low_index, ctx.Constant(ctx.U32[1], 1U))};
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const Id low_pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, low_index)};
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const Id high_pointer{ctx.OpAccessChain(ctx.storage_u32, ssbo, ctx.u32_zero_value, high_index)};
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ctx.OpStore(low_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 0U));
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ctx.OpStore(high_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 1U));
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}
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void EmitWriteStorage128(EmitContext&) {
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throw NotImplementedException("SPIR-V Instruction");
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}
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} // namespace Shader::Backend::SPIRV
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