b9238edd0d
These types are within the common library, so they should be within the Common namespace.
58 lines
2.2 KiB
C++
58 lines
2.2 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/core.h"
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#include "core/memory.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra::Engines {
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Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
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ASSERT_MSG(method_call.method < Regs::NUM_REGS,
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"Invalid Fermi2D register, increase the size of the Regs structure");
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regs.reg_array[method_call.method] = method_call.argument;
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switch (method_call.method) {
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// Trigger the surface copy on the last register write. This is blit_src_y, but this is 64-bit,
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// so trigger on the second 32-bit write.
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case FERMI2D_REG_INDEX(blit_src_y) + 1: {
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HandleSurfaceCopy();
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break;
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}
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}
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}
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void Fermi2D::HandleSurfaceCopy() {
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LOG_WARNING(HW_GPU, "Requested a surface copy with operation {}",
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static_cast<u32>(regs.operation));
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// TODO(Subv): Only raw copies are implemented.
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ASSERT(regs.operation == Regs::Operation::SrcCopy);
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const u32 src_blit_x1{static_cast<u32>(regs.blit_src_x >> 32)};
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const u32 src_blit_y1{static_cast<u32>(regs.blit_src_y >> 32)};
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const u32 src_blit_x2{
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static_cast<u32>((regs.blit_src_x + (regs.blit_dst_width * regs.blit_du_dx)) >> 32)};
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const u32 src_blit_y2{
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static_cast<u32>((regs.blit_src_y + (regs.blit_dst_height * regs.blit_dv_dy)) >> 32)};
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const Common::Rectangle<u32> src_rect{src_blit_x1, src_blit_y1, src_blit_x2, src_blit_y2};
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const Common::Rectangle<u32> dst_rect{regs.blit_dst_x, regs.blit_dst_y,
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regs.blit_dst_x + regs.blit_dst_width,
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regs.blit_dst_y + regs.blit_dst_height};
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if (!rasterizer.AccelerateSurfaceCopy(regs.src, regs.dst, src_rect, dst_rect)) {
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UNIMPLEMENTED();
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}
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}
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} // namespace Tegra::Engines
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