303 lines
7 KiB
C++
303 lines
7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra::Texture {
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enum class TextureFormat : u32 {
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R32_G32_B32_A32 = 0x01,
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R32_G32_B32 = 0x02,
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R16_G16_B16_A16 = 0x03,
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R32_G32 = 0x04,
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R32_B24G8 = 0x05,
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ETC2_RGB = 0x06,
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X8B8G8R8 = 0x07,
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A8R8G8B8 = 0x08,
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A2B10G10R10 = 0x09,
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ETC2_RGB_PTA = 0x0a,
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ETC2_RGBA = 0x0b,
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R16_G16 = 0x0c,
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G8R24 = 0x0d,
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G24R8 = 0x0e,
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R32 = 0x0f,
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BC6H_SF16 = 0x10,
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BC6H_UF16 = 0x11,
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A4B4G4R4 = 0x12,
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A5B5G5R1 = 0x13,
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A1B5G5R5 = 0x14,
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B5G6R5 = 0x15,
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B6G5R5 = 0x16,
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BC7U = 0x17,
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G8R8 = 0x18,
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EAC = 0x19,
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EACX2 = 0x1a,
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R16 = 0x1b,
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Y8_VIDEO = 0x1c,
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R8 = 0x1d,
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G4R4 = 0x1e,
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R1 = 0x1f,
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E5B9G9R9_SHAREDEXP = 0x20,
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BF10GF11RF11 = 0x21,
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G8B8G8R8 = 0x22,
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B8G8R8G8 = 0x23,
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DXT1 = 0x24,
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DXT23 = 0x25,
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DXT45 = 0x26,
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DXN1 = 0x27,
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DXN2 = 0x28,
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Z24S8 = 0x29,
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X8Z24 = 0x2a,
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S8Z24 = 0x2b,
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X4V4Z24__COV4R4V = 0x2c,
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X4V4Z24__COV8R8V = 0x2d,
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V8Z24__COV4R12V = 0x2e,
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ZF32 = 0x2f,
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ZF32_X24S8 = 0x30,
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X8Z24_X20V4S8__COV4R4V = 0x31,
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X8Z24_X20V4S8__COV8R8V = 0x32,
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ZF32_X20V4X8__COV4R4V = 0x33,
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ZF32_X20V4X8__COV8R8V = 0x34,
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ZF32_X20V4S8__COV4R4V = 0x35,
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ZF32_X20V4S8__COV8R8V = 0x36,
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X8Z24_X16V8S8__COV4R12V = 0x37,
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ZF32_X16V8X8__COV4R12V = 0x38,
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ZF32_X16V8S8__COV4R12V = 0x39,
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Z16 = 0x3a,
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V8Z24__COV8R24V = 0x3b,
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X8Z24_X16V8S8__COV8R24V = 0x3c,
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ZF32_X16V8X8__COV8R24V = 0x3d,
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ZF32_X16V8S8__COV8R24V = 0x3e,
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ASTC_2D_4X4 = 0x40,
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ASTC_2D_5X5 = 0x41,
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ASTC_2D_6X6 = 0x42,
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ASTC_2D_8X8 = 0x44,
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ASTC_2D_10X10 = 0x45,
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ASTC_2D_12X12 = 0x46,
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ASTC_2D_5X4 = 0x50,
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ASTC_2D_6X5 = 0x51,
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ASTC_2D_8X6 = 0x52,
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ASTC_2D_10X8 = 0x53,
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ASTC_2D_12X10 = 0x54,
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ASTC_2D_8X5 = 0x55,
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ASTC_2D_10X5 = 0x56,
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ASTC_2D_10X6 = 0x57,
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};
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enum class TextureType : u32 {
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Texture1D = 0,
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Texture2D = 1,
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Texture3D = 2,
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TextureCubemap = 3,
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Texture1DArray = 4,
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Texture2DArray = 5,
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Texture1DBuffer = 6,
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Texture2DNoMipmap = 7,
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TextureCubeArray = 8,
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};
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enum class TICHeaderVersion : u32 {
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OneDBuffer = 0,
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PitchColorKey = 1,
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Pitch = 2,
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BlockLinear = 3,
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BlockLinearColorKey = 4,
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};
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enum class ComponentType : u32 {
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SNORM = 1,
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UNORM = 2,
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SINT = 3,
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UINT = 4,
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SNORM_FORCE_FP16 = 5,
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UNORM_FORCE_FP16 = 6,
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FLOAT = 7
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};
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enum class SwizzleSource : u32 {
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Zero = 0,
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R = 2,
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G = 3,
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B = 4,
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A = 5,
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OneInt = 6,
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OneFloat = 7,
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};
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union TextureHandle {
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u32 raw;
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BitField<0, 20, u32> tic_id;
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BitField<20, 12, u32> tsc_id;
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};
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static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
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struct TICEntry {
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static constexpr u32 DefaultBlockHeight = 16;
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static constexpr u32 DefaultBlockDepth = 1;
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union {
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u32 raw;
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BitField<0, 7, TextureFormat> format;
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BitField<7, 3, ComponentType> r_type;
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BitField<10, 3, ComponentType> g_type;
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BitField<13, 3, ComponentType> b_type;
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BitField<16, 3, ComponentType> a_type;
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BitField<19, 3, SwizzleSource> x_source;
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BitField<22, 3, SwizzleSource> y_source;
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BitField<25, 3, SwizzleSource> z_source;
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BitField<28, 3, SwizzleSource> w_source;
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};
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u32 address_low;
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union {
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BitField<0, 16, u32> address_high;
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BitField<21, 3, TICHeaderVersion> header_version;
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};
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union {
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BitField<0, 3, u32> block_width;
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BitField<3, 3, u32> block_height;
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BitField<6, 3, u32> block_depth;
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// High 16 bits of the pitch value
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BitField<0, 16, u32> pitch_high;
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BitField<28, 4, u32> max_mip_level;
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};
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union {
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BitField<0, 16, u32> width_minus_1;
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BitField<22, 1, u32> srgb_conversion;
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BitField<23, 4, TextureType> texture_type;
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};
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union {
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BitField<0, 16, u32> height_minus_1;
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BitField<16, 15, u32> depth_minus_1;
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};
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INSERT_PADDING_BYTES(8);
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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}
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u32 Pitch() const {
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ASSERT(header_version == TICHeaderVersion::Pitch ||
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header_version == TICHeaderVersion::PitchColorKey);
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// The pitch value is 21 bits, and is 32B aligned.
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return pitch_high << 5;
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}
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u32 Width() const {
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return width_minus_1 + 1;
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}
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u32 Height() const {
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return height_minus_1 + 1;
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}
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u32 Depth() const {
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return depth_minus_1 + 1;
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}
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u32 BlockWidth() const {
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ASSERT(IsTiled());
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// The block height is stored in log2 format.
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return 1 << block_width;
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}
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u32 BlockHeight() const {
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ASSERT(IsTiled());
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// The block height is stored in log2 format.
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return 1 << block_height;
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}
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u32 BlockDepth() const {
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ASSERT(IsTiled());
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// The block height is stored in log2 format.
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return 1 << block_depth;
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}
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bool IsTiled() const {
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return header_version == TICHeaderVersion::BlockLinear ||
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header_version == TICHeaderVersion::BlockLinearColorKey;
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}
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bool IsSrgbConversionEnabled() const {
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return srgb_conversion != 0;
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}
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};
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static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
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enum class WrapMode : u32 {
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Wrap = 0,
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Mirror = 1,
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ClampToEdge = 2,
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Border = 3,
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ClampOGL = 4,
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MirrorOnceClampToEdge = 5,
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MirrorOnceBorder = 6,
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MirrorOnceClampOGL = 7,
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};
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enum class DepthCompareFunc : u32 {
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Never = 0,
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Less = 1,
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Equal = 2,
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LessEqual = 3,
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Greater = 4,
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NotEqual = 5,
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GreaterEqual = 6,
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Always = 7,
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};
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enum class TextureFilter : u32 {
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Nearest = 1,
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Linear = 2,
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};
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enum class TextureMipmapFilter : u32 {
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None = 1,
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Nearest = 2,
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Linear = 3,
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};
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struct TSCEntry {
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union {
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BitField<0, 3, WrapMode> wrap_u;
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BitField<3, 3, WrapMode> wrap_v;
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BitField<6, 3, WrapMode> wrap_p;
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BitField<9, 1, u32> depth_compare_enabled;
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BitField<10, 3, DepthCompareFunc> depth_compare_func;
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};
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union {
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BitField<0, 2, TextureFilter> mag_filter;
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BitField<4, 2, TextureFilter> min_filter;
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BitField<6, 2, TextureMipmapFilter> mip_filter;
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};
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INSERT_PADDING_BYTES(8);
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float border_color_r;
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float border_color_g;
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float border_color_b;
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float border_color_a;
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};
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static_assert(sizeof(TSCEntry) == 0x20, "TSCEntry has wrong size");
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struct FullTextureInfo {
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u32 index;
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TICEntry tic;
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TSCEntry tsc;
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bool enabled;
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};
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/// Returns the number of bytes per pixel of the input texture format.
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u32 BytesPerPixel(TextureFormat format);
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} // namespace Tegra::Texture
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