358 lines
9.5 KiB
C++
358 lines
9.5 KiB
C++
/*
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armvfp.c - ARM VFPv3 emulation unit
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Copyright (C) 2003 Skyeye Develop Group
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for help please send mail to <skyeye-developer@lists.gro.clinux.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Note: this file handles interface with arm core and vfp registers */
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/* Opens debug for classic interpreter only */
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//#define DEBUG
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#include "common/common.h"
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#include "core/arm/interpreter/armdefs.h"
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#include "core/arm/interpreter/vfp/vfp.h"
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//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
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unsigned
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VFPInit (ARMul_State *state)
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{
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state->VFP[VFP_OFFSET(VFP_FPSID)] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
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VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
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state->VFP[VFP_OFFSET(VFP_FPEXC)] = 0;
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state->VFP[VFP_OFFSET(VFP_FPSCR)] = 0;
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//persistent_state = state;
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/* Reset only specify VFP_FPEXC_EN = '0' */
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return No_exp;
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}
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unsigned
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VFPMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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{
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/* MRC<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int OPC_1 = BITS (21, 23);
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int Rt = BITS (12, 15);
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int CRn = BITS (16, 19);
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int CRm = BITS (0, 3);
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int OPC_2 = BITS (5, 7);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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#define VFP_MRC_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MRC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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return ARMul_CANT;
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}
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unsigned
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VFPMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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{
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/* MCR<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int OPC_1 = BITS (21, 23);
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int Rt = BITS (12, 15);
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int CRn = BITS (16, 19);
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int CRm = BITS (0, 3);
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int OPC_2 = BITS (5, 7);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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#define VFP_MCR_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MCR_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
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instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
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return ARMul_CANT;
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}
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unsigned
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VFPMRRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value1, ARMword * value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int OPC_1 = BITS (4, 7);
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int Rt = BITS (12, 15);
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int Rt2 = BITS (16, 19);
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int CRm = BITS (0, 3);
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if (CoProc == 10 || CoProc == 11)
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{
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#define VFP_MRRC_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MRRC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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return ARMul_CANT;
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}
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unsigned
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VFPMCRR (ARMul_State * state, unsigned type, ARMword instr, ARMword value1, ARMword value2)
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{
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/* MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int OPC_1 = BITS (4, 7);
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int Rt = BITS (12, 15);
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int Rt2 = BITS (16, 19);
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int CRm = BITS (0, 3);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 11 || CoProc == 10)
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{
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#define VFP_MCRR_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MCRR_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
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instr, CoProc, OPC_1, Rt, Rt2, CRm);
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return ARMul_CANT;
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}
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unsigned
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VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
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{
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/* STC{L}<c> <coproc>,<CRd>,[<Rn>],<option> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int CRd = BITS (12, 15);
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int Rn = BITS (16, 19);
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int imm8 = BITS (0, 7);
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int P = BIT(24);
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int U = BIT(23);
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int D = BIT(22);
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int W = BIT(21);
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/* TODO check access permission */
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/* VSTM */
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if ( (P|U|D|W) == 0 )
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{
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DEBUG_LOG(ARM11, "In %s, UNDEFINED\n", __FUNCTION__); exit(-1);
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}
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if (CoProc == 10 || CoProc == 11)
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{
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#if 1
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if (P == 0 && U == 0 && W == 0)
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{
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DEBUG_LOG(ARM11, "VSTM Related encodings\n"); exit(-1);
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}
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if (P == U && W == 1)
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{
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DEBUG_LOG(ARM11, "UNDEFINED\n"); exit(-1);
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}
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#endif
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#define VFP_STC_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_STC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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return ARMul_CANT;
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}
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unsigned
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VFPLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
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{
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/* LDC{L}<c> <coproc>,<CRd>,[<Rn>] */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int CRd = BITS (12, 15);
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int Rn = BITS (16, 19);
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int imm8 = BITS (0, 7);
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int P = BIT(24);
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int U = BIT(23);
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int D = BIT(22);
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int W = BIT(21);
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/* TODO check access permission */
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if ( (P|U|D|W) == 0 )
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{
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DEBUG_LOG(ARM11, "In %s, UNDEFINED\n", __FUNCTION__); exit(-1);
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}
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if (CoProc == 10 || CoProc == 11)
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{
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#define VFP_LDC_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_LDC_TRANS
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}
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DEBUG_LOG(ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
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instr, CoProc, CRd, Rn, imm8, P, U, D, W);
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return ARMul_CANT;
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}
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unsigned
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VFPCDP (ARMul_State * state, unsigned type, ARMword instr)
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{
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/* CDP<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2> */
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int CoProc = BITS (8, 11); /* 10 or 11 */
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int OPC_1 = BITS (20, 23);
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int CRd = BITS (12, 15);
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int CRn = BITS (16, 19);
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int CRm = BITS (0, 3);
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int OPC_2 = BITS (5, 7);
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/* TODO check access permission */
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/* CRn/opc1 CRm/opc2 */
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if (CoProc == 10 || CoProc == 11)
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{
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#define VFP_CDP_TRANS
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_CDP_TRANS
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int exceptions = 0;
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if (CoProc == 10)
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exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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else
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exceptions = vfp_double_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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vfp_raise_exceptions(state, exceptions, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
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return ARMul_DONE;
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}
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DEBUG_LOG(ARM11, "Can't identify %x\n", instr);
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return ARMul_CANT;
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}
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/* ----------- MRC ------------ */
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#define VFP_MRC_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MRC_IMPL
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#define VFP_MRRC_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MRRC_IMPL
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/* ----------- MCR ------------ */
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#define VFP_MCR_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MCR_IMPL
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#define VFP_MCRR_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_MCRR_IMPL
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/* Memory operation are not inlined, as old Interpreter and Fast interpreter
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don't have the same memory operation interface.
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Old interpreter framework does one access to coprocessor per data, and
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handles already data write, as well as address computation,
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which is not the case for Fast interpreter. Therefore, implementation
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of vfp instructions in old interpreter and fast interpreter are separate. */
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/* ----------- STC ------------ */
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#define VFP_STC_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_STC_IMPL
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/* ----------- LDC ------------ */
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#define VFP_LDC_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_LDC_IMPL
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/* ----------- CDP ------------ */
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#define VFP_CDP_IMPL
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#include "core/arm/interpreter/vfp/vfpinstr.cpp"
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#undef VFP_CDP_IMPL
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/* Miscellaneous functions */
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int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
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{
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DBG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
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return state->ExtReg[reg];
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}
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void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
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{
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DBG("VFP put float: s%d <= [%08x]\n", reg, val);
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state->ExtReg[reg] = val;
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}
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uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
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{
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uint64_t result;
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result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
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DBG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result);
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return result;
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}
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void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
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{
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DBG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff));
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state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
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state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
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}
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/*
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* Process bitmask of exception conditions. (from vfpmodule.c)
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*/
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void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr)
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{
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int si_code = 0;
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vfpdebug("VFP: raising exceptions %08x\n", exceptions);
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if (exceptions == VFP_EXCEPTION_ERROR) {
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DEBUG_LOG(ARM11, "unhandled bounce %x\n", inst);
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exit(-1);
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return;
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}
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/*
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* If any of the status flags are set, update the FPSCR.
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* Comparison instructions always return at least one of
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* these flags set.
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*/
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if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
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fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
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fpscr |= exceptions;
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state->VFP[VFP_OFFSET(VFP_FPSCR)] = fpscr;
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}
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