Emmanuel Gil Peyrot
643e590b5c
Core: Add a forgotten #include <cstring> for memcpy.
2016-12-11 01:20:45 +00:00
MerryMage
27be446049
dynarmic: Add ticks based on ticks executed, not ticks requested
2016-11-26 20:32:33 +00:00
James Rowe
bbe57a66ca
Expose page table to dynarmic for optimized reads and writes to the JIT
2016-11-24 20:41:18 -07:00
Yuri Kunde Schlesner
84fbbe2629
Use negative priorities to avoid special-casing the self-include
2016-09-21 00:15:56 -07:00
Emmanuel Gil Peyrot
ebdae19fd2
Remove empty newlines in #include blocks.
...
This makes clang-format useful on those.
Also add a bunch of forgotten transitive includes, which otherwise
prevented compilation.
2016-09-21 11:15:47 +09:00
Yuri Kunde Schlesner
396a8d91a4
Manually tweak source formatting and then re-run clang-format
2016-09-18 21:14:25 -07:00
Emmanuel Gil Peyrot
dc8479928c
Sources: Run clang-format on everything.
2016-09-18 09:38:01 +09:00
Emmanuel Gil Peyrot
bfc454e951
Dyncom: Disable clang-format on the decoding table.
2016-09-18 09:36:57 +09:00
bunnei
1b95f61d82
arm_dynarmic: Implement GetVFPSystemReg/SetVFPSystemReg.
2016-09-15 17:58:06 -04:00
bunnei
05e120a4cc
arm: ResetContext shouldn't be part of ARM_Interface.
2016-09-15 17:49:30 -04:00
bunnei
85861d44b7
arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.
2016-09-15 17:49:30 -04:00
bunnei
b7aef81cb4
dyncom: Use VFP_FPSCR/VFP_FPEXC.
2016-09-15 17:49:29 -04:00
bunnei
1976a2d773
dynarmic: Implement ARM CPU interface.
2016-09-15 17:49:26 -04:00
wwylele
2161f52661
ARM: add ClearInstructionCache function
2016-08-27 21:38:06 +08:00
MerryMage
15b2eec4bd
dyncom: Read-after-write in SMLA
...
In the case when RD === RN, RD was updated before AddOverflow was called
to check for an overflow, resulting in an incorrect state of the Q flag.
2016-08-22 15:13:33 +01:00
MerryMage
50407a8dc8
Dyncom: Correct implementation of STM for R15
2016-08-14 00:49:34 +01:00
MerryMage
60c93ca3b5
dyncom: Fix translation of thumb REVSH
2016-07-28 11:51:29 +01:00
archshift
ca20b1f87d
Make arm_dyncom_trans* into a fully fledged compilation unit
2016-06-12 01:54:45 -07:00
archshift
54b5178f6c
arm_dyncom_interpreter: slightly change AllocBuffer to be intuitive
2016-06-12 00:31:52 -07:00
archshift
765eef3319
arm_dyncom_interpreter: Add specialized GetAddressingOpLoadStoreT func
...
This allows us to get the addressing operation for STRT, LDRT, STRBT,
and LDRBT. We do this so that translation functions don't need to
see the addressing ops directly.
2016-06-10 18:45:48 -07:00
archshift
eac4c016cb
arm_dyncom_interpreter: rename operation functions to fit style guide
2016-06-10 18:42:08 -07:00
archshift
5297f5dfc9
arm_dyncom_interpreter: Rename anonymous enum to TransExtData
2016-06-10 18:35:57 -07:00
archshift
2c482722e7
arm_dyncom_interpreter.cpp: #include translation info from inc files
2016-06-10 18:25:30 -07:00
Mat M
031a9c57bb
Merge pull request #1568 from JayFoxRox/fix-printf
...
Fix ftoi and disable VFPv3
2016-05-26 19:03:00 -04:00
Jannik Vogel
edf30d84cc
Remove exceptions parameter from normaliseround VFP functions
2016-05-18 16:28:13 +02:00
Jannik Vogel
693cca8f1f
Fix exception propagation for VFP single precision
2016-05-18 15:24:42 +02:00
Jannik Vogel
7dde13f875
Fix exception propagation for VFP double precision
2016-05-18 15:24:42 +02:00
Jannik Vogel
3a45eacb16
Fix read-after-write in SMUAD, SMLAD, SMUSD, SMLSD
2016-05-18 14:03:02 +02:00
Jannik Vogel
af37dd0d52
Set fpscr for new threads
2016-05-17 08:59:52 +02:00
Jannik Vogel
501d0bc5ed
Fix ftoi behaviour
2016-05-16 15:00:45 +02:00
Jannik Vogel
6fe0cb671d
Respect fpscr in ftoiz
2016-05-16 15:00:45 +02:00
Jannik Vogel
1643786c04
Disable VFP3 instructions
2016-05-16 15:00:45 +02:00
Lioncash
0f941d0245
dyncom: Reset the context into user mode correctly
...
The other mode was system mode.
2016-05-09 16:30:55 -04:00
Yuri Kunde Schlesner
e3a8292495
Common: Remove section measurement from profiler ( #1731 )
...
This has been entirely superseded by MicroProfile. The rest of the code
can go when a simpler frametime/FPS meter is added to the GUI.
2016-04-29 00:07:10 -07:00
mailwl
2efc1c9348
Fix BLX LR opcode interpretation
2016-04-09 19:11:02 +03:00
mailwl
4630209c4c
Update cpsr (T)humb bit while creating thread
2016-04-08 18:41:09 +03:00
mailwl
06a4369f75
Fix thumb ADR instruction alignment
2016-04-06 19:46:58 +03:00
Mathew Maidment
aa6380e5bc
Merge pull request #1643 from MerryMage/make_unique
...
Common: Remove Common::make_unique, use std::make_unique
2016-04-05 20:10:11 -04:00
MerryMage
a06dcfeb61
Common: Remove Common::make_unique, use std::make_unique
2016-04-05 13:31:17 +01:00
Mathew Maidment
80c16961ae
Merge pull request #1618 from MerryMage/one-step
...
Prevent cache overflow when single stepping
2016-03-31 11:00:42 -04:00
MerryMage
cbba0bec7c
DynCom: Optimize single stepping
2016-03-30 18:57:59 +01:00
Lioncash
d53c9cde1a
armstate: Correct FIQ register banking
...
FIQ has seven banked registers (R8 to R14), not two.
2016-03-21 18:56:27 -04:00
rob turner
d29578d467
ARM_Disasm::DisassembleMemHalf: actually use width in determining opcode name
2016-01-19 18:42:16 +01:00
Lioncash
532dc797c9
arm_dyncom_dec: Fix decoding of VMLS
...
Previously, all VMLS variants would misdecode as CDP
(which isn't necessarily wrong in itself, however
VMLS has it's own label of execution)
2015-12-30 14:23:07 -05:00
Lioncash
fddfe946c8
dyncom: Handle modifying the APSR via an MRC instruction
2015-12-28 07:52:04 -05:00
Lioncash
d09b7a3c12
dyncom: Remove PC dispatch from several instructions
...
These instructions aren't capable of using the PC as a destination
2015-12-20 21:19:02 -05:00
Lioncash
5a531d7ec2
dyncom: Handle unprivileged load/store variants correctly
...
LDRT/LDRBT/STRBT/STRT should simulate the load or store
as if the host CPU is in user mode.
STRT is also allowed to use the PC as an operand
2015-12-19 19:05:50 -05:00
Lioncash
56e22e6aac
dyncom: Remove static keyword from header functions
2015-12-06 15:14:51 -05:00
Lioncash
1ea0702eaa
arm_interface: Make GetNumInstructions const
2015-12-06 15:07:59 -05:00
Lioncash
de9a625c7e
arm_interface: directly initialize class members
2015-12-06 15:07:00 -05:00
