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Author SHA1 Message Date
Lioncash b51e7e0288 arm_interface: Remove ARM11-isms from the CPU interface 
This modifies the CPU interface to more accurately match an
AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods
don't even make sense to keep around for this interface, as Adv Simd is
used, rather than the VFP in the primary execution state. This is
essentially a modernization change that should have occurred from the
get-go.
 2018-09-18 03:20:04 -04:00
fearlessTobi 63c2e32e20 Port #4182 from Citra: "Prefix all size_t with std::" 2018-09-15 15:21:06 +02:00
Markus Wick 10bc725944 Update microprofile scopes. 
Blame the subsystems which deserve the blame :)

The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
 2018-09-04 11:04:26 +02:00
Lioncash 4a587b81b2 core/core: Replace includes with forward declarations where applicable 
The follow-up to e2457418da, which
replaces most of the includes in the core header with forward declarations.

This makes it so that if any of the headers the core header was
previously including change, then no one will need to rebuild the bulk
of the core, due to core.h being quite a prevalent inclusion.

This should make turnaround for changes much faster for developers.
 2018-08-31 16:30:14 -04:00
Lioncash 43e0d865fa core: Namespace all code in the arm subdirectory under the Core namespace 
Gets all of these types and interfaces out of the global namespace.
 2018-08-24 21:50:39 -04:00
MerryMage 94329038b6 dynarmic: Update to 550d662 
550d662 load_store_exclusive: Define s == t state to be Constraint_NONE
0b69381 A64/translate: Allow for unpredictable behaviour to be defined
6d236d4 system: Implement MRS CNTFRQ_EL0
6cbb6fb A32/testenv: Add missing headers
6729328 externals: Update xbyak to v5.67
1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805
9a95802 externals: Document subtrees
714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants
8cab459 A64: Implement UQADD/UQSUB's scalar variants
18a8151 ir: Add opcodes for unsigned saturating add and subtract
a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo()
29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR
55190bd fuzz_with_unicorn: Split utility functions into fuzz_util
23b049d A32/translate/load_store: Correct detection of writeback
7ec9f15 A32/translate: Add TranslateSingleInstruction
efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
08d1d19 A32/decoders: Split instruction list into include file
2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn
f672368 microinstruction: Improve assert messages
7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation
edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
 2018-08-16 10:12:20 +01:00
MerryMage fcc5155601 arm_dynarmic: Remove IsExecuting check from PrepareReschedule 
No longer required. HaltExecution is a no-op if it is not currently executing.
 2018-08-13 13:59:01 +01:00
Subv d923766042 CPU/Timing: Use an approximated amortized amount of ticks when advancing timing. 
We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast.

This lets us bypass certain hangs in some games like Breath of the Wild.

We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
 2018-08-12 20:41:28 -05:00
bunnei f5efac3442
Merge pull request #876 from lioncash/include 
kernel: Remove unnecessary includes
 2018-07-31 19:16:05 -07:00
Lioncash a2304fad16 kernel: Remove unnecessary includes 
Removes unnecessary direct dependencies in some headers and also gets
rid of indirect dependencies that were being relied on to be included.
 2018-07-31 10:15:17 -04:00
Lioncash f08c0520a4 arm_dynarmic: Make SetTlsAddress() prototype and definition consistent 
Makes the definition use the same type aliases as in its prototype.
 2018-07-31 07:58:26 -04:00
Lioncash 9d6aa7bff7 arm_dynarmic: Remove unnecessary qualifying of ThreadContext 
Given the ARM_Dynarmic class inherits from ARM_Interface, we don't need
to qualify here.
 2018-07-31 07:56:59 -04:00
Lioncash 444a01afa6 arm_dynarmic: Correct initializer list order 
Amends the initializer list to be in the same order that each variable
would be initialized in. We also do this to ensure we don't use a bogus
uninitialized instance of the exclusive monitor within MakeJit()

We can also remove the jit member from the initializer list as this is
initialized by PageTableChanged()
 2018-07-31 07:54:58 -04:00
Lioncash 7d124ec82b arm_dynarmic: Make MakeJit() a const member function 
This functions doesn't modify instance state, so it can be a made a
const member function.
 2018-07-23 23:19:37 -04:00
Lioncash e12c84d5c5 exclusive_monitor: Use consistent type alias for u64 
Uses the same type aliases we use for virtual addresses, and converts
one lingering usage of std::array<uint64_t, 2> to u128 for consistency.
 2018-07-23 20:54:57 -04:00
MerryMage 0b1c2e5505 Implement exclusive monitor 2018-07-22 15:55:17 +01:00
bunnei de7cb91995
Merge pull request #750 from lioncash/ctx 
arm_interface: Remove unused tls_address member of ThreadContext
 2018-07-21 11:38:16 -07:00
Subv d84eb9dac6 CPU: Save and restore the TPIDR_EL0 system register on every context switch. 
Note that there's currently a dynarmic bug preventing this register from being written.
 2018-07-20 19:57:45 -05:00
Lioncash ae09adfcb3 arm_interface: Remove unused tls_address member of ThreadContext 
Currently, the TLS address is set within the scheduler, making this
member unused.
 2018-07-20 18:57:40 -04:00
MerryMage 56cc1c11ec scheduler: Clear exclusive state when switching contexts 2018-07-16 11:24:00 +01:00
James Rowe 0d46f0df12 Update clang format 2018-07-02 21:45:47 -04:00
James Rowe 638956aa81 Rename logging macro back to LOG_* 2018-07-02 21:45:47 -04:00
Lioncash 7c9644646f
general: Make formatting of logged hex values more straightforward 
This makes the formatting expectations more obvious (e.g. any zero padding specified
is padding that's entirely dedicated to the value being printed, not any pretty-printing
that also gets tacked on).
 2018-05-02 09:49:36 -04:00
Lioncash 8475496630
general: Convert assertion macros over to be fmt-compatible 2018-04-27 10:04:02 -04:00
Lioncash c33755e2b9
core: Replace remaining old non-generic logger usages with fmt-capable equivalents 
LOG_GENERIC usages will be amended in a follow-up to keep API changes separate from
interface changes, as it will require removing a parameter from the relevant function
in the VMManager class.
 2018-04-26 15:37:16 -04:00
MerryMage 88c9608eac arm_dynarmic: Fix timing 2018-03-24 09:02:19 +00:00
bunnei 23a0d2d7b7
Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo 
Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
 2018-03-18 22:35:47 -04:00
bunnei 403f8e79ea arm_interface: Support unmapping previously mapped memory. 2018-03-16 18:32:24 -04:00
bunnei 7d6653268f core: Move process creation out of global state. 2018-03-14 18:42:19 -04:00
N00byKing bc88cae0c7 Implements citra-emu/citra#3184 2018-02-25 11:44:21 +01:00
MerryMage 32d127ad3e dynarmic: Update to 6b4c6b0 
6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
 2018-02-21 21:39:07 +00:00
MerryMage e8b9731af3 arm_dynarmic: LOG_INFO on unicorn fallback 2018-02-21 21:39:07 +00:00
MerryMage 6085d32cf5 arm_dynarmic: Support direct page table access 2018-02-12 21:53:32 +00:00
MerryMage d3bbed5e78 dynarmic: Update to 41ae12263 
Changes: Primarily implementing more A64 instructions
 2018-02-09 00:29:36 +00:00
River City Ransomware dd62f125c3 Fixes some cast warnings, partial port of citra #3064 (#106) 
* Fixes some cast warnings, partially fixes citra #3064

* Converted casts to uint32_t to u32

* Ran clang-format
 2018-01-19 18:01:41 -05:00
MerryMage 668e5452fa Update dynarmic to bc73004 
bc73004 a64_merge_interpret_blocks: Remove debug output
4e656ed tests/A64: Randomize PSTATE.<NZCV>
fd9530b A64: Optimization: Merge interpret blocks
3c9eb04 testenv: Use format constants
324f3fc tests/A64: Unicorn interface fixes
98ecbe7 tests/A64: Fuzz against unicorn
b1d38e7 tests/A64: Move TestEnvironment to own header
5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
edadeea A64 inferface: Use two argument static_assert
9ab1304 A64: Add ExceptionRaised IR instruction
6843eed Update readme
7438d07 A64/translate: Add TranslateSingleInstruction function
 2018-01-13 22:38:57 +00:00
bunnei 1247c53786 yuzu: Update license text to be consistent across project. 2018-01-13 16:22:39 -05:00
MerryMage d2fbc78320 arm_dynarmic: Implement core 2018-01-12 17:48:29 -05:00
bunnei 6e9d66fd3a arm_dynarmic: More cleanup. 2018-01-04 00:09:12 -05:00
bunnei aa7e061e71 arm_dynarmic: Gut interface until dynarmic is ready for general use. 2018-01-03 22:10:11 -05:00
bunnei b172f0d770 arm: Remove SkyEye/Dyncom code that is ARMv6-only. 2018-01-02 22:24:12 -05:00
bunnei b1d5db1cf6 Merge remote-tracking branch 'upstream/master' into nx 
# Conflicts:
#	src/core/CMakeLists.txt
#	src/core/arm/dynarmic/arm_dynarmic.cpp
#	src/core/arm/dyncom/arm_dyncom.cpp
#	src/core/hle/kernel/process.cpp
#	src/core/hle/kernel/thread.cpp
#	src/core/hle/kernel/thread.h
#	src/core/hle/kernel/vm_manager.cpp
#	src/core/loader/3dsx.cpp
#	src/core/loader/elf.cpp
#	src/core/loader/ncch.cpp
#	src/core/memory.cpp
#	src/core/memory.h
#	src/core/memory_setup.h
 2017-10-09 23:56:20 -04:00
bunnei 6377585edb arm_interface: Set TLS address for dynarmic core. 2017-09-30 14:34:03 -04:00
bunnei 3411883fe3 arm: Use 64-bit addressing in a bunch of places. 2017-09-30 14:28:53 -04:00
Huw Pascoe 529f4a0131 Moved down_count to CoreTiming 2017-09-30 17:38:14 +01:00
MerryMage 67a70bd9e1 ARM_Interface: Implement PageTableChanged 2017-09-24 23:08:25 +01:00
B3n30 813837c5cf Merge pull request #2842 from Subv/switchable_page_table 
Kernel/Memory: Give each process its own page table and allow switching the current page table upon reschedule
 2017-09-15 22:41:45 +02:00
Subv 7a3ab7c63d CPU/Dynarmic: Disable the fast page-table access in dynarmic until it supports switching page tables at runtime. 2017-09-15 14:26:22 -05:00
Subv d237a89048 CPU/Dynarmic: Fixed a warning when incrementing the number of ticks in ExecuteInstructions. 2017-08-21 08:34:25 -05:00
MerryMage e2815408fd arm_dynarmic: Update memory interface 2017-02-03 17:32:51 +00:00
MerryMage 2b36d4c9d7 arm_dynarmic: CP15 support 2017-02-03 17:32:47 +00:00
bunnei 76890672a0 Merge pull request #2366 from MerryMage/MemoryReadCode 
arm_dynarmic: Provide MemoryReadCode callback
 2016-12-22 14:25:15 -05:00
MerryMage f8cf87ce34 arm_dynarmic: Provide MemoryReadCode callback 
Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
 2016-12-22 16:07:14 +00:00
bunnei 8b1e269e58 ThreadContext: Move from "core" to "arm_interface". 2016-12-22 00:27:49 -05:00
Emmanuel Gil Peyrot 643e590b5c Core: Add a forgotten #include <cstring> for memcpy. 2016-12-11 01:20:45 +00:00
MerryMage 27be446049 dynarmic: Add ticks based on ticks executed, not ticks requested 2016-11-26 20:32:33 +00:00
James Rowe bbe57a66ca Expose page table to dynarmic for optimized reads and writes to the JIT 2016-11-24 20:41:18 -07:00
Yuri Kunde Schlesner 84fbbe2629 Use negative priorities to avoid special-casing the self-include 2016-09-21 00:15:56 -07:00
Emmanuel Gil Peyrot ebdae19fd2 Remove empty newlines in #include blocks. 
This makes clang-format useful on those.

Also add a bunch of forgotten transitive includes, which otherwise
prevented compilation.
 2016-09-21 11:15:47 +09:00
bunnei 1b95f61d82 arm_dynarmic: Implement GetVFPSystemReg/SetVFPSystemReg. 2016-09-15 17:58:06 -04:00
bunnei 05e120a4cc arm: ResetContext shouldn't be part of ARM_Interface. 2016-09-15 17:49:30 -04:00
bunnei 85861d44b7 arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword. 2016-09-15 17:49:30 -04:00
bunnei 1976a2d773 dynarmic: Implement ARM CPU interface. 2016-09-15 17:49:26 -04:00