artemist/yuzu
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Merge pull request #283 from Subv/tsc

Browse source 
GPU: Added sampler information structures (TSC)
This commit is contained in:
bunnei 2018-03-26 21:15:23 -04:00 committed by GitHub
parent 010ea89013 4697025b73
commit f934da0e43
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
3 changed files with 148 additions and 26 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
src/video_core/engines/maxwell_3d.cpp
View file

@ -294,8 +294,45 @@ void Maxwell3D::ProcessCBData(u32 value) {
regs.const_buffer.cb_pos = regs.const_buffer.cb_pos + 4;
}
std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) {
std::vector<Texture::TICEntry> textures;
Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const {
GPUVAddr tic_base_address = regs.tic.TICAddress();
GPUVAddr tic_address_gpu = tic_base_address + tic_index * sizeof(Texture::TICEntry);
VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
Texture::TICEntry tic_entry;
Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear,
"TIC versions other than BlockLinear are unimplemented");
ASSERT_MSG(tic_entry.texture_type == Texture::TextureType::Texture2D,
"Texture types other than Texture2D are unimplemented");
auto r_type = tic_entry.r_type.Value();
auto g_type = tic_entry.g_type.Value();
auto b_type = tic_entry.b_type.Value();
auto a_type = tic_entry.a_type.Value();
// TODO(Subv): Different data types for separate components are not supported
ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
return tic_entry;
}
Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const {
GPUVAddr tsc_base_address = regs.tsc.TSCAddress();
GPUVAddr tsc_address_gpu = tsc_base_address + tsc_index * sizeof(Texture::TSCEntry);
VAddr tsc_address_cpu = memory_manager.PhysicalToVirtualAddress(tsc_address_gpu);
Texture::TSCEntry tsc_entry;
Memory::ReadBlock(tsc_address_cpu, &tsc_entry, sizeof(Texture::TSCEntry));
return tsc_entry;
}
std::vector<Texture::FullTextureInfo> Maxwell3D::GetStageTextures(Regs::ShaderStage stage) const {
std::vector<Texture::FullTextureInfo> textures;
auto& fragment_shader = state.shader_stages[static_cast<size_t>(stage)];
auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
@ -309,31 +346,34 @@ std::vector<Texture::TICEntry> Maxwell3D::GetStageTextures(Regs::ShaderStage sta
static constexpr size_t TextureInfoOffset = 0x20;
for (GPUVAddr current_texture = tex_info_buffer.address + TextureInfoOffset;
current_texture < tex_info_buffer_end; current_texture += 4) {
current_texture < tex_info_buffer_end; current_texture += sizeof(Texture::TextureHandle)) {
Texture::TextureHandle tex_info{
Texture::TextureHandle tex_handle{
Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) {
GPUVAddr tic_address_gpu =
tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry);
VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
Texture::FullTextureInfo tex_info{};
// TODO(Subv): Use the shader to determine which textures are actually accessed.
tex_info.index = (current_texture - tex_info_buffer.address - TextureInfoOffset) /
sizeof(Texture::TextureHandle);
Texture::TICEntry tic_entry;
Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
// Load the TIC data.
if (tex_handle.tic_id != 0) {
tex_info.enabled = true;
auto r_type = tic_entry.r_type.Value();
auto g_type = tic_entry.g_type.Value();
auto b_type = tic_entry.b_type.Value();
auto a_type = tic_entry.a_type.Value();
// TODO(Subv): Different data types for separate components are not supported
ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
auto format = tic_entry.format.Value();
textures.push_back(tic_entry);
auto tic_entry = GetTICEntry(tex_handle.tic_id);
// TODO(Subv): Workaround for BitField's move constructor being deleted.
std::memcpy(&tex_info.tic, &tic_entry, sizeof(tic_entry));
}
// Load the TSC data
if (tex_handle.tsc_id != 0) {
auto tsc_entry = GetTSCEntry(tex_handle.tsc_id);
// TODO(Subv): Workaround for BitField's move constructor being deleted.
std::memcpy(&tex_info.tsc, &tsc_entry, sizeof(tsc_entry));
}
if (tex_info.enabled)
textures.push_back(tex_info);
}
return textures;

8
src/video_core/engines/maxwell_3d.h
View file

@ -432,7 +432,7 @@ public:
void SubmitMacroCode(u32 entry, std::vector<u32> code);
/// Returns a list of enabled textures for the specified shader stage.
std::vector<Texture::TICEntry> GetStageTextures(Regs::ShaderStage stage);
std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
private:
MemoryManager& memory_manager;
@ -444,6 +444,12 @@ private:
/// Parameters that have been submitted to the macro call so far.
std::vector<u32> macro_params;
/// Retrieves information about a specific TIC entry from the TIC buffer.
Texture::TICEntry GetTICEntry(u32 tic_index) const;
/// Retrieves information about a specific TSC entry from the TSC buffer.
Texture::TSCEntry GetTSCEntry(u32 tsc_index) const;
/**
* Call a macro on this engine.
* @param method Method to call

84
src/video_core/textures/texture.h
View file

@ -17,11 +17,32 @@ enum class TextureFormat : u32 {
DXT1 = 0x24,
};
enum class TextureType : u32 {
Texture1D = 0,
Texture2D = 1,
Texture3D = 2,
TextureCubemap = 3,
Texture1DArray = 4,
Texture2DArray = 5,
Texture1DBuffer = 6,
Texture2DNoMipmap = 7,
TextureCubeArray = 8,
};
enum class TICHeaderVersion : u32 {
OneDBuffer = 0,
PitchColorKey = 1,
Pitch = 2,
BlockLinear = 3,
BlockLinearColorKey = 4,
};
union TextureHandle {
u32 raw;
BitField<0, 20, u32> tic_id;
BitField<20, 12, u32> tsc_id;
};
static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
struct TICEntry {
union {
@ -33,10 +54,15 @@ struct TICEntry {
BitField<16, 3, u32> a_type;
};
u32 address_low;
u16 address_high;
INSERT_PADDING_BYTES(6);
u16 width_minus_1;
INSERT_PADDING_BYTES(2);
union {
BitField<0, 16, u32> address_high;
BitField<21, 3, TICHeaderVersion> header_version;
};
INSERT_PADDING_BYTES(4);
union {
BitField<0, 16, u32> width_minus_1;
BitField<23, 4, TextureType> texture_type;
};
u16 height_minus_1;
INSERT_PADDING_BYTES(10);
@ -54,6 +80,56 @@ struct TICEntry {
};
static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
enum class WrapMode : u32 {
Wrap = 0,
Mirror = 1,
ClampToEdge = 2,
Border = 3,
ClampOGL = 4,
MirrorOnceClampToEdge = 5,
MirrorOnceBorder = 6,
MirrorOnceClampOGL = 7,
};
enum class TextureFilter : u32 {
Nearest = 1,
Linear = 2,
};
enum class TextureMipmapFilter : u32 {
None = 1,
Nearest = 2,
Linear = 3,
};
struct TSCEntry {
union {
BitField<0, 3, WrapMode> wrap_u;
BitField<3, 3, WrapMode> wrap_v;
BitField<6, 3, WrapMode> wrap_p;
BitField<9, 1, u32> depth_compare_enabled;
BitField<10, 3, u32> depth_compare_func;
};
union {
BitField<0, 2, TextureFilter> mag_filter;
BitField<4, 2, TextureFilter> min_filter;
BitField<6, 2, TextureMipmapFilter> mip_filter;
};
INSERT_PADDING_BYTES(8);
u32 border_color_r;
u32 border_color_g;
u32 border_color_b;
u32 border_color_a;
};
static_assert(sizeof(TSCEntry) == 0x20, "TSCEntry has wrong size");
struct FullTextureInfo {
u32 index;
TICEntry tic;
TSCEntry tsc;
bool enabled;
};
/// Returns the number of bytes per pixel of the input texture format.
u32 BytesPerPixel(TextureFormat format);