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Merge pull request #1508 from JayFoxRox/vs-output-map

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Respect vs output map
This commit is contained in:
bunnei 2016-03-22 11:59:12 -04:00
parent 85edb851b0 f746a00964
commit ebbba0d381
2 changed files with 19 additions and 7 deletions
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8
src/video_core/pica.h
View file

@ -71,7 +71,7 @@ struct Regs {
BitField<0, 24, u32> viewport_depth_range; // float24 BitField<0, 24, u32> viewport_depth_range; // float24
BitField<0, 24, u32> viewport_depth_far_plane; // float24 BitField<0, 24, u32> viewport_depth_far_plane; // float24
INSERT_PADDING_WORDS(0x1); BitField<0, 3, u32> vs_output_total;
union VSOutputAttributes { union VSOutputAttributes {
// Maps components of output vertex attributes to semantics // Maps components of output vertex attributes to semantics
@ -1157,8 +1157,10 @@ struct Regs {
} }
} input_register_map; } input_register_map;
// OUTMAP_MASK, 0x28E, CODETRANSFER_END BitField<0, 16, u32> output_mask;
INSERT_PADDING_WORDS(0x3);
// 0x28E, CODETRANSFER_END
INSERT_PADDING_WORDS(0x2);
struct { struct {
enum Format : u32 enum Format : u32

18
src/video_core/shader/shader.cpp
View file

@ -121,15 +121,23 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
OutputVertex ret; OutputVertex ret;
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to // TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
// figure out what those circumstances are and enable the remaining outputs then. // figure out what those circumstances are and enable the remaining outputs then.
for (int i = 0; i < 7; ++i) { unsigned index = 0;
const auto& output_register_map = g_state.regs.vs_output_attributes[i]; // TODO: Don't hardcode VS here for (unsigned i = 0; i < 7; ++i) {
if (index >= g_state.regs.vs_output_total)
break;
if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
continue;
const auto& output_register_map = g_state.regs.vs_output_attributes[index]; // TODO: Don't hardcode VS here
u32 semantics[4] = { u32 semantics[4] = {
output_register_map.map_x, output_register_map.map_y, output_register_map.map_x, output_register_map.map_y,
output_register_map.map_z, output_register_map.map_w output_register_map.map_z, output_register_map.map_w
}; };
for (int comp = 0; comp < 4; ++comp) { for (unsigned comp = 0; comp < 4; ++comp) {
float24* out = ((float24*)&ret) + semantics[comp]; float24* out = ((float24*)&ret) + semantics[comp];
if (semantics[comp] != Regs::VSOutputAttributes::INVALID) { if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
*out = state.registers.output[i][comp]; *out = state.registers.output[i][comp];
@ -139,10 +147,12 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
memset(out, 0, sizeof(*out)); memset(out, 0, sizeof(*out));
} }
} }
index++;
} }
// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation // The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
for (int i = 0; i < 4; ++i) { for (unsigned i = 0; i < 4; ++i) {
ret.color[i] = float24::FromFloat32( ret.color[i] = float24::FromFloat32(
std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f)); std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
} }