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Merge pull request #750 from lioncash/ctx

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arm_interface: Remove unused tls_address member of ThreadContext
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bunnei 2018-07-21 11:38:16 -07:00 committed by GitHub
parent 867ba1ceee ae09adfcb3
commit de7cb91995
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 0 additions and 9 deletions
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3
src/core/arm/arm_interface.h
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@ -20,9 +20,6 @@ public:
u64 cpsr; u64 cpsr;
std::array<u128, 32> fpu_registers; std::array<u128, 32> fpu_registers;
u64 fpscr; u64 fpscr;
// TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
VAddr tls_address;
}; };
/// Runs the CPU until an event happens /// Runs the CPU until an event happens

2
src/core/arm/dynarmic/arm_dynarmic.cpp
View file

@ -211,7 +211,6 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
ctx.cpsr = jit->GetPstate(); ctx.cpsr = jit->GetPstate();
ctx.fpu_registers = jit->GetVectors(); ctx.fpu_registers = jit->GetVectors();
ctx.fpscr = jit->GetFpcr(); ctx.fpscr = jit->GetFpcr();
ctx.tls_address = cb->tpidrro_el0;
} }
void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) { void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
@ -221,7 +220,6 @@ void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
jit->SetPstate(static_cast<u32>(ctx.cpsr)); jit->SetPstate(static_cast<u32>(ctx.cpsr));
jit->SetVectors(ctx.fpu_registers); jit->SetVectors(ctx.fpu_registers);
jit->SetFpcr(static_cast<u32>(ctx.fpscr)); jit->SetFpcr(static_cast<u32>(ctx.fpscr));
cb->tpidrro_el0 = ctx.tls_address;
} }
void ARM_Dynarmic::PrepareReschedule() { void ARM_Dynarmic::PrepareReschedule() {

4
src/core/arm/unicorn/arm_unicorn.cpp
View file

@ -230,8 +230,6 @@ void ARM_Unicorn::SaveContext(ARM_Interface::ThreadContext& ctx) {
CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31)); CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31));
ctx.tls_address = GetTlsAddress();
for (int i = 0; i < 32; ++i) { for (int i = 0; i < 32; ++i) {
uregs[i] = UC_ARM64_REG_Q0 + i; uregs[i] = UC_ARM64_REG_Q0 + i;
tregs[i] = &ctx.fpu_registers[i]; tregs[i] = &ctx.fpu_registers[i];
@ -259,8 +257,6 @@ void ARM_Unicorn::LoadContext(const ARM_Interface::ThreadContext& ctx) {
CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31)); CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31));
SetTlsAddress(ctx.tls_address);
for (auto i = 0; i < 32; ++i) { for (auto i = 0; i < 32; ++i) {
uregs[i] = UC_ARM64_REG_Q0 + i; uregs[i] = UC_ARM64_REG_Q0 + i;
tregs[i] = (void*)&ctx.fpu_registers[i]; tregs[i] = (void*)&ctx.fpu_registers[i];