shader: Fix ISCADD logic for PO/CC
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@ -30,23 +30,24 @@ void ISCADD(TranslatorVisitor& v, u64 insn, IR::U32 op_b) {
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if (iscadd.neg_b != 0) {
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if (iscadd.neg_b != 0) {
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op_b = v.ir.INeg(op_b);
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op_b = v.ir.INeg(op_b);
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}
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}
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} else {
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// When PO is present, add one
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op_b = v.ir.IAdd(op_b, v.ir.Imm32(1));
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}
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}
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// With the operands already processed, scale A
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// With the operands already processed, scale A
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const IR::U32 scale{v.ir.Imm32(static_cast<u32>(iscadd.scale))};
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const IR::U32 scale{v.ir.Imm32(static_cast<u32>(iscadd.scale))};
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const IR::U32 scaled_a{v.ir.ShiftLeftLogical(op_a, scale)};
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const IR::U32 scaled_a{v.ir.ShiftLeftLogical(op_a, scale)};
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IR::U32 result{v.ir.IAdd(scaled_a, op_b)};
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const IR::U32 result{v.ir.IAdd(scaled_a, op_b)};
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if (po) {
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// .PO adds one to the final result
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result = v.ir.IAdd(result, v.ir.Imm32(1));
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}
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v.X(iscadd.dest_reg, result);
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v.X(iscadd.dest_reg, result);
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if (iscadd.cc != 0) {
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if (iscadd.cc != 0) {
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v.SetZFlag(v.ir.GetZeroFromOp(result));
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v.SetZFlag(v.ir.GetZeroFromOp(result));
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v.SetSFlag(v.ir.GetSignFromOp(result));
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v.SetSFlag(v.ir.GetSignFromOp(result));
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v.SetCFlag(v.ir.GetCarryFromOp(result));
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const IR::U1 carry{v.ir.GetCarryFromOp(result)};
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v.SetOFlag(v.ir.GetOverflowFromOp(result));
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const IR::U1 overflow{v.ir.GetOverflowFromOp(result)};
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v.SetCFlag(po ? v.ir.LogicalOr(carry, v.ir.GetCarryFromOp(op_b)) : carry);
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v.SetOFlag(po ? v.ir.LogicalOr(overflow, v.ir.GetOverflowFromOp(op_b)) : overflow);
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}
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}
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}
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}
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