Merge pull request #8594 from liamwhite/skip-wp
core/arm: skip watchpoint checks when reading instructions
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commit
b8813edc51
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@ -52,7 +52,7 @@ public:
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if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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return MemoryRead32(vaddr);
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return memory.Read32(vaddr);
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}
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void MemoryWrite8(u32 vaddr, u8 value) override {
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@ -97,7 +97,7 @@ public:
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parent.LogBacktrace();
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryRead32(pc));
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num_instructions, memory.Read32(pc));
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}
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void ExceptionRaised(u32 pc, Dynarmic::A32::Exception exception) override {
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@ -115,7 +115,7 @@ public:
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parent.LogBacktrace();
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LOG_CRITICAL(Core_ARM,
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"ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X}, thumb = {})",
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exception, pc, MemoryRead32(pc), parent.IsInThumbMode());
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exception, pc, memory.Read32(pc), parent.IsInThumbMode());
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}
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}
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@ -56,7 +56,7 @@ public:
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if (!memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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return MemoryRead32(vaddr);
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return memory.Read32(vaddr);
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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@ -111,7 +111,7 @@ public:
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parent.LogBacktrace();
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, MemoryRead32(pc));
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num_instructions, memory.Read32(pc));
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}
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void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
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@ -156,7 +156,7 @@ public:
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parent.LogBacktrace();
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, MemoryRead32(pc));
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static_cast<std::size_t>(exception), pc, memory.Read32(pc));
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}
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}
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