Merge pull request #1501 from ReinUsesLisp/half-float
gl_shader_decompiler: Implement H* instructions
This commit is contained in:
bunnei
GitHub
commit
b1f8bff7db
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@ -335,6 +335,26 @@ enum class IsberdMode : u64 {
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enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 };
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enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 };
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enum class HalfType : u64 {
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H0_H1 = 0,
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F32 = 1,
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H0_H0 = 2,
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H1_H1 = 3,
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};
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enum class HalfMerge : u64 {
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H0_H1 = 0,
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F32 = 1,
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Mrg_H0 = 2,
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Mrg_H1 = 3,
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};
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enum class HalfPrecision : u64 {
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None = 0,
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FTZ = 1,
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FMZ = 2,
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};
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enum class IpaInterpMode : u64 {
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enum class IpaInterpMode : u64 {
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Linear = 0,
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Linear = 0,
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Perspective = 1,
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Perspective = 1,
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@ -553,6 +573,70 @@ union Instruction {
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BitField<49, 1, u64> negate_a;
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BitField<49, 1, u64> negate_a;
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} alu_integer;
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} alu_integer;
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union {
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BitField<39, 1, u64> ftz;
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BitField<32, 1, u64> saturate;
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BitField<49, 2, HalfMerge> merge;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<47, 2, HalfType> type_b;
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BitField<35, 2, HalfType> type_c;
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} alu_half;
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union {
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BitField<39, 2, HalfPrecision> precision;
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BitField<39, 1, u64> ftz;
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BitField<52, 1, u64> saturate;
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BitField<49, 2, HalfMerge> merge;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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} alu_half_imm;
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union {
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BitField<29, 1, u64> first_negate;
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BitField<20, 9, u64> first;
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BitField<56, 1, u64> second_negate;
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BitField<30, 9, u64> second;
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u32 PackImmediates() const {
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// Immediates are half floats shifted.
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constexpr u32 imm_shift = 6;
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return static_cast<u32>((first << imm_shift) | (second << (16 + imm_shift)));
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}
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} half_imm;
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union {
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union {
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BitField<37, 2, HalfPrecision> precision;
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BitField<32, 1, u64> saturate;
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BitField<30, 1, u64> negate_c;
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BitField<35, 2, HalfType> type_c;
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} rr;
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BitField<57, 2, HalfPrecision> precision;
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BitField<52, 1, u64> saturate;
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BitField<49, 2, HalfMerge> merge;
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BitField<47, 2, HalfType> type_a;
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BitField<56, 1, u64> negate_b;
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BitField<28, 2, HalfType> type_b;
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BitField<51, 1, u64> negate_c;
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BitField<53, 2, HalfType> type_reg39;
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} hfma2;
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union {
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union {
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BitField<40, 1, u64> invert;
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BitField<40, 1, u64> invert;
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} popc;
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} popc;
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@ -716,6 +800,23 @@ union Instruction {
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BitField<45, 4, PredOperation> op; // op with pred39
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BitField<45, 4, PredOperation> op; // op with pred39
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} csetp;
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} csetp;
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union {
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BitField<35, 4, PredCondition> cond;
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BitField<49, 1, u64> h_and;
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BitField<6, 1, u64> ftz;
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BitField<45, 2, PredOperation> op;
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BitField<3, 3, u64> pred3;
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BitField<0, 3, u64> pred0;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<28, 2, HalfType> type_b;
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BitField<42, 1, u64> neg_pred;
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BitField<39, 3, u64> pred39;
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} hsetp2;
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union {
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union {
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BitField<39, 3, u64> pred39;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<42, 1, u64> neg_pred;
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@ -730,6 +831,21 @@ union Instruction {
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BitField<56, 1, u64> neg_imm;
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BitField<56, 1, u64> neg_imm;
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} fset;
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} fset;
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union {
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BitField<49, 1, u64> bf;
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BitField<35, 3, PredCondition> cond;
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BitField<50, 1, u64> ftz;
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BitField<45, 2, PredOperation> op;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_a;
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BitField<47, 2, HalfType> type_a;
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BitField<31, 1, u64> negate_b;
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BitField<30, 1, u64> abs_b;
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BitField<28, 2, HalfType> type_b;
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BitField<42, 1, u64> neg_pred;
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BitField<39, 3, u64> pred39;
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} hset2;
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union {
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union {
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BitField<39, 3, u64> pred39;
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BitField<39, 3, u64> pred39;
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BitField<42, 1, u64> neg_pred;
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BitField<42, 1, u64> neg_pred;
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@ -1145,6 +1261,18 @@ public:
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LEA_RZ,
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LEA_RZ,
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LEA_IMM,
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LEA_IMM,
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LEA_HI,
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LEA_HI,
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HADD2_C,
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HADD2_R,
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HADD2_IMM,
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HMUL2_C,
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HMUL2_R,
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HMUL2_IMM,
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HFMA2_CR,
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HFMA2_RC,
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HFMA2_RR,
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HFMA2_IMM_R,
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HSETP2_R,
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HSET2_R,
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POPC_C,
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POPC_C,
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POPC_R,
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POPC_R,
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POPC_IMM,
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POPC_IMM,
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@ -1218,9 +1346,12 @@ public:
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ArithmeticImmediate,
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ArithmeticImmediate,
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ArithmeticInteger,
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ArithmeticInteger,
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ArithmeticIntegerImmediate,
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ArithmeticIntegerImmediate,
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ArithmeticHalf,
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ArithmeticHalfImmediate,
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Bfe,
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Bfe,
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Shift,
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Shift,
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Ffma,
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Ffma,
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Hfma2,
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Flow,
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Flow,
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Synch,
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Synch,
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Memory,
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Memory,
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@ -1228,6 +1359,8 @@ public:
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FloatSetPredicate,
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FloatSetPredicate,
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IntegerSet,
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IntegerSet,
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IntegerSetPredicate,
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IntegerSetPredicate,
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HalfSet,
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HalfSetPredicate,
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PredicateSetPredicate,
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PredicateSetPredicate,
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PredicateSetRegister,
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PredicateSetRegister,
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Conversion,
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Conversion,
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@ -1389,6 +1522,18 @@ private:
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INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"),
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INST("001101101101----", Id::LEA_IMM, Type::ArithmeticInteger, "LEA_IMM"),
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INST("010010111101----", Id::LEA_RZ, Type::ArithmeticInteger, "LEA_RZ"),
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INST("010010111101----", Id::LEA_RZ, Type::ArithmeticInteger, "LEA_RZ"),
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INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"),
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INST("00011000--------", Id::LEA_HI, Type::ArithmeticInteger, "LEA_HI"),
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INST("0111101-1-------", Id::HADD2_C, Type::ArithmeticHalf, "HADD2_C"),
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INST("0101110100010---", Id::HADD2_R, Type::ArithmeticHalf, "HADD2_R"),
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INST("0111101-0-------", Id::HADD2_IMM, Type::ArithmeticHalfImmediate, "HADD2_IMM"),
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INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"),
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INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"),
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INST("0111100-0-------", Id::HMUL2_IMM, Type::ArithmeticHalfImmediate, "HMUL2_IMM"),
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INST("01110---1-------", Id::HFMA2_CR, Type::Hfma2, "HFMA2_CR"),
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP_R"),
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INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -375,6 +375,49 @@ public:
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}
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}
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}
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}
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/**
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* Writes code that does a register assignment to a half float value operation.
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* @param reg The destination register to use.
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* @param elem The element to use for the operation.
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* @param value The code representing the value to assign. Type has to be half float.
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* @param type Half float kind of assignment.
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* @param dest_num_components Number of components in the destionation.
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* @param value_num_components Number of components in the value.
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* @param is_saturated Optional, when True, saturates the provided value.
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* @param dest_elem Optional, the destination element to use for the operation.
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*/
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void SetRegisterToHalfFloat(const Register& reg, u64 elem, const std::string& value,
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Tegra::Shader::HalfMerge merge, u64 dest_num_components,
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u64 value_num_components, bool is_saturated = false,
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u64 dest_elem = 0) {
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ASSERT_MSG(!is_saturated, "Unimplemented");
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const std::string result = [&]() {
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switch (merge) {
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case Tegra::Shader::HalfMerge::H0_H1:
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return "uintBitsToFloat(packHalf2x16(" + value + "))";
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case Tegra::Shader::HalfMerge::F32:
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// Half float instructions take the first component when doing a float cast.
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return "float(" + value + ".x)";
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case Tegra::Shader::HalfMerge::Mrg_H0:
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// TODO(Rodrigo): I guess Mrg_H0 and Mrg_H1 take their respective component from the
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// pack. I couldn't test this on hardware but it shouldn't really matter since most
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// of the time when a Mrg_* flag is used both components will be mirrored. That
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// being said, it deserves a test.
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return "((" + GetRegisterAsInteger(reg, 0, false) +
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" & 0xffff0000) | (packHalf2x16(" + value + ") & 0x0000ffff))";
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case Tegra::Shader::HalfMerge::Mrg_H1:
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return "((" + GetRegisterAsInteger(reg, 0, false) +
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" & 0x0000ffff) | (packHalf2x16(" + value + ") & 0xffff0000))";
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default:
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UNREACHABLE();
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return std::string("0");
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}
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}();
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SetRegister(reg, elem, result, dest_num_components, value_num_components, dest_elem);
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}
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/**
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/**
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* Writes code that does a register assignment to input attribute operation. Input attributes
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* Writes code that does a register assignment to input attribute operation. Input attributes
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* are stored as floats, so this may require conversion.
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* are stored as floats, so this may require conversion.
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@ -877,6 +920,19 @@ private:
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return fmt::format("uintBitsToFloat({})", instr.alu.GetImm20_32());
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return fmt::format("uintBitsToFloat({})", instr.alu.GetImm20_32());
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}
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}
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/// Generates code representing a vec2 pair unpacked from a half float immediate
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static std::string UnpackHalfImmediate(const Instruction& instr, bool negate) {
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const std::string immediate = GetHalfFloat(std::to_string(instr.half_imm.PackImmediates()));
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if (!negate) {
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return immediate;
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}
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const std::string negate_first = instr.half_imm.first_negate != 0 ? "-" : "";
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const std::string negate_second = instr.half_imm.second_negate != 0 ? "-" : "";
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const std::string negate_vec = "vec2(" + negate_first + "1, " + negate_second + "1)";
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return '(' + immediate + " * " + negate_vec + ')';
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}
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/// Generates code representing a texture sampler.
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/// Generates code representing a texture sampler.
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std::string GetSampler(const Sampler& sampler, Tegra::Shader::TextureType type, bool is_array,
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std::string GetSampler(const Sampler& sampler, Tegra::Shader::TextureType type, bool is_array,
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bool is_shadow) {
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bool is_shadow) {
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@ -1012,6 +1068,41 @@ private:
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return result;
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return result;
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}
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}
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/*
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* Transforms the input string GLSL operand into an unpacked half float pair.
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* @note This function returns a float type pair instead of a half float pair. This is because
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* real half floats are not standarized in GLSL but unpackHalf2x16 (which returns a vec2) is.
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* @param operand Input operand. It has to be an unsigned integer.
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* @param type How to unpack the unsigned integer to a half float pair.
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* @param abs Get the absolute value of unpacked half floats.
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* @param neg Get the negative value of unpacked half floats.
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* @returns String corresponding to a half float pair.
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*/
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static std::string GetHalfFloat(const std::string& operand,
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Tegra::Shader::HalfType type = Tegra::Shader::HalfType::H0_H1,
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bool abs = false, bool neg = false) {
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// "vec2" calls emitted in this function are intended to alias components.
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const std::string value = [&]() {
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switch (type) {
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case Tegra::Shader::HalfType::H0_H1:
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return "unpackHalf2x16(" + operand + ')';
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case Tegra::Shader::HalfType::F32:
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return "vec2(uintBitsToFloat(" + operand + "))";
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case Tegra::Shader::HalfType::H0_H0:
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case Tegra::Shader::HalfType::H1_H1: {
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const bool high = type == Tegra::Shader::HalfType::H1_H1;
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const char unpack_index = "xy"[high ? 1 : 0];
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return "vec2(unpackHalf2x16(" + operand + ")." + unpack_index + ')';
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}
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default:
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UNREACHABLE();
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return std::string("vec2(0)");
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}
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}();
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return GetOperandAbsNeg(value, abs, neg);
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}
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/*
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/*
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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* Sched instructions always appear before a sequence of 3 instructions.
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@ -1748,6 +1839,86 @@ private:
|
||||||
|
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
case OpCode::Type::ArithmeticHalf: {
|
||||||
|
if (opcode->GetId() == OpCode::Id::HADD2_C || opcode->GetId() == OpCode::Id::HADD2_R) {
|
||||||
|
ASSERT_MSG(instr.alu_half.ftz == 0, "Unimplemented");
|
||||||
|
}
|
||||||
|
const bool negate_a =
|
||||||
|
opcode->GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
|
||||||
|
const bool negate_b =
|
||||||
|
opcode->GetId() != OpCode::Id::HMUL2_C && instr.alu_half.negate_b != 0;
|
||||||
|
|
||||||
|
const std::string op_a =
|
||||||
|
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.alu_half.type_a,
|
||||||
|
instr.alu_half.abs_a != 0, negate_a);
|
||||||
|
|
||||||
|
std::string op_b;
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HADD2_C:
|
||||||
|
case OpCode::Id::HMUL2_C:
|
||||||
|
op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
|
||||||
|
GLSLRegister::Type::UnsignedInteger);
|
||||||
|
break;
|
||||||
|
case OpCode::Id::HADD2_R:
|
||||||
|
case OpCode::Id::HMUL2_R:
|
||||||
|
op_b = regs.GetRegisterAsInteger(instr.gpr20, 0, false);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
op_b = "0";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
op_b = GetHalfFloat(op_b, instr.alu_half.type_b, instr.alu_half.abs_b != 0, negate_b);
|
||||||
|
|
||||||
|
const std::string result = [&]() {
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HADD2_C:
|
||||||
|
case OpCode::Id::HADD2_R:
|
||||||
|
return '(' + op_a + " + " + op_b + ')';
|
||||||
|
case OpCode::Id::HMUL2_C:
|
||||||
|
case OpCode::Id::HMUL2_R:
|
||||||
|
return '(' + op_a + " * " + op_b + ')';
|
||||||
|
default:
|
||||||
|
LOG_CRITICAL(HW_GPU, "Unhandled half float instruction: {}", opcode->GetName());
|
||||||
|
UNREACHABLE();
|
||||||
|
return std::string("0");
|
||||||
|
}
|
||||||
|
}();
|
||||||
|
|
||||||
|
regs.SetRegisterToHalfFloat(instr.gpr0, 0, result, instr.alu_half.merge, 1, 1,
|
||||||
|
instr.alu_half.saturate != 0);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case OpCode::Type::ArithmeticHalfImmediate: {
|
||||||
|
if (opcode->GetId() == OpCode::Id::HADD2_IMM) {
|
||||||
|
ASSERT_MSG(instr.alu_half_imm.ftz == 0, "Unimplemented");
|
||||||
|
} else {
|
||||||
|
ASSERT_MSG(instr.alu_half_imm.precision == Tegra::Shader::HalfPrecision::None,
|
||||||
|
"Unimplemented");
|
||||||
|
}
|
||||||
|
|
||||||
|
const std::string op_a = GetHalfFloat(
|
||||||
|
regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.alu_half_imm.type_a,
|
||||||
|
instr.alu_half_imm.abs_a != 0, instr.alu_half_imm.negate_a != 0);
|
||||||
|
|
||||||
|
const std::string op_b = UnpackHalfImmediate(instr, true);
|
||||||
|
|
||||||
|
const std::string result = [&]() {
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HADD2_IMM:
|
||||||
|
return op_a + " + " + op_b;
|
||||||
|
case OpCode::Id::HMUL2_IMM:
|
||||||
|
return op_a + " * " + op_b;
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
return std::string("0");
|
||||||
|
}
|
||||||
|
}();
|
||||||
|
|
||||||
|
regs.SetRegisterToHalfFloat(instr.gpr0, 0, result, instr.alu_half_imm.merge, 1, 1,
|
||||||
|
instr.alu_half_imm.saturate != 0);
|
||||||
|
break;
|
||||||
|
}
|
||||||
case OpCode::Type::Ffma: {
|
case OpCode::Type::Ffma: {
|
||||||
const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
|
const std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
|
||||||
std::string op_b = instr.ffma.negate_b ? "-" : "";
|
std::string op_b = instr.ffma.negate_b ? "-" : "";
|
||||||
|
|
@ -1792,6 +1963,59 @@ private:
|
||||||
instr.alu.saturate_d);
|
instr.alu.saturate_d);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
case OpCode::Type::Hfma2: {
|
||||||
|
if (opcode->GetId() == OpCode::Id::HFMA2_RR) {
|
||||||
|
ASSERT_MSG(instr.hfma2.rr.precision == Tegra::Shader::HalfPrecision::None,
|
||||||
|
"Unimplemented");
|
||||||
|
} else {
|
||||||
|
ASSERT_MSG(instr.hfma2.precision == Tegra::Shader::HalfPrecision::None,
|
||||||
|
"Unimplemented");
|
||||||
|
}
|
||||||
|
const bool saturate = opcode->GetId() == OpCode::Id::HFMA2_RR
|
||||||
|
? instr.hfma2.rr.saturate != 0
|
||||||
|
: instr.hfma2.saturate != 0;
|
||||||
|
|
||||||
|
const std::string op_a =
|
||||||
|
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.hfma2.type_a);
|
||||||
|
std::string op_b, op_c;
|
||||||
|
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HFMA2_CR:
|
||||||
|
op_b = GetHalfFloat(regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
|
||||||
|
GLSLRegister::Type::UnsignedInteger),
|
||||||
|
instr.hfma2.type_b, false, instr.hfma2.negate_b);
|
||||||
|
op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
|
||||||
|
instr.hfma2.type_reg39, false, instr.hfma2.negate_c);
|
||||||
|
break;
|
||||||
|
case OpCode::Id::HFMA2_RC:
|
||||||
|
op_b = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
|
||||||
|
instr.hfma2.type_reg39, false, instr.hfma2.negate_b);
|
||||||
|
op_c = GetHalfFloat(regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
|
||||||
|
GLSLRegister::Type::UnsignedInteger),
|
||||||
|
instr.hfma2.type_b, false, instr.hfma2.negate_c);
|
||||||
|
break;
|
||||||
|
case OpCode::Id::HFMA2_RR:
|
||||||
|
op_b = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
|
||||||
|
instr.hfma2.type_b, false, instr.hfma2.negate_b);
|
||||||
|
op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
|
||||||
|
instr.hfma2.rr.type_c, false, instr.hfma2.rr.negate_c);
|
||||||
|
break;
|
||||||
|
case OpCode::Id::HFMA2_IMM_R:
|
||||||
|
op_b = UnpackHalfImmediate(instr, true);
|
||||||
|
op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
|
||||||
|
instr.hfma2.type_reg39, false, instr.hfma2.negate_c);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
op_c = op_b = "vec2(0)";
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
const std::string result = '(' + op_a + " * " + op_b + " + " + op_c + ')';
|
||||||
|
|
||||||
|
regs.SetRegisterToHalfFloat(instr.gpr0, 0, result, instr.hfma2.merge, 1, 1, saturate);
|
||||||
|
break;
|
||||||
|
}
|
||||||
case OpCode::Type::Conversion: {
|
case OpCode::Type::Conversion: {
|
||||||
switch (opcode->GetId()) {
|
switch (opcode->GetId()) {
|
||||||
case OpCode::Id::I2I_R: {
|
case OpCode::Id::I2I_R: {
|
||||||
|
|
@ -2611,6 +2835,51 @@ private:
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
case OpCode::Type::HalfSetPredicate: {
|
||||||
|
ASSERT_MSG(instr.hsetp2.ftz == 0, "Unimplemented");
|
||||||
|
|
||||||
|
const std::string op_a =
|
||||||
|
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.hsetp2.type_a,
|
||||||
|
instr.hsetp2.abs_a, instr.hsetp2.negate_a);
|
||||||
|
|
||||||
|
const std::string op_b = [&]() {
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HSETP2_R:
|
||||||
|
return GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
|
||||||
|
instr.hsetp2.type_b, instr.hsetp2.abs_a,
|
||||||
|
instr.hsetp2.negate_b);
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
return std::string("vec2(0)");
|
||||||
|
}
|
||||||
|
}();
|
||||||
|
|
||||||
|
// We can't use the constant predicate as destination.
|
||||||
|
ASSERT(instr.hsetp2.pred3 != static_cast<u64>(Pred::UnusedIndex));
|
||||||
|
|
||||||
|
const std::string second_pred =
|
||||||
|
GetPredicateCondition(instr.hsetp2.pred39, instr.hsetp2.neg_pred != 0);
|
||||||
|
|
||||||
|
const std::string combiner = GetPredicateCombiner(instr.hsetp2.op);
|
||||||
|
|
||||||
|
const std::string component_combiner = instr.hsetp2.h_and ? "&&" : "||";
|
||||||
|
const std::string predicate =
|
||||||
|
'(' + GetPredicateComparison(instr.hsetp2.cond, op_a + ".x", op_b + ".x") + ' ' +
|
||||||
|
component_combiner + ' ' +
|
||||||
|
GetPredicateComparison(instr.hsetp2.cond, op_a + ".y", op_b + ".y") + ')';
|
||||||
|
|
||||||
|
// Set the primary predicate to the result of Predicate OP SecondPredicate
|
||||||
|
SetPredicate(instr.hsetp2.pred3,
|
||||||
|
'(' + predicate + ") " + combiner + " (" + second_pred + ')');
|
||||||
|
|
||||||
|
if (instr.hsetp2.pred0 != static_cast<u64>(Pred::UnusedIndex)) {
|
||||||
|
// Set the secondary predicate to the result of !Predicate OP SecondPredicate,
|
||||||
|
// if enabled
|
||||||
|
SetPredicate(instr.hsetp2.pred0,
|
||||||
|
"!(" + predicate + ") " + combiner + " (" + second_pred + ')');
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
case OpCode::Type::PredicateSetRegister: {
|
case OpCode::Type::PredicateSetRegister: {
|
||||||
const std::string op_a =
|
const std::string op_a =
|
||||||
GetPredicateCondition(instr.pset.pred12, instr.pset.neg_pred12 != 0);
|
GetPredicateCondition(instr.pset.pred12, instr.pset.neg_pred12 != 0);
|
||||||
|
|
@ -2771,6 +3040,50 @@ private:
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
case OpCode::Type::HalfSet: {
|
||||||
|
ASSERT_MSG(instr.hset2.ftz == 0, "Unimplemented");
|
||||||
|
|
||||||
|
const std::string op_a =
|
||||||
|
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.hset2.type_a,
|
||||||
|
instr.hset2.abs_a != 0, instr.hset2.negate_a != 0);
|
||||||
|
|
||||||
|
const std::string op_b = [&]() {
|
||||||
|
switch (opcode->GetId()) {
|
||||||
|
case OpCode::Id::HSET2_R:
|
||||||
|
return GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
|
||||||
|
instr.hset2.type_b, instr.hset2.abs_b != 0,
|
||||||
|
instr.hset2.negate_b != 0);
|
||||||
|
default:
|
||||||
|
UNREACHABLE();
|
||||||
|
return std::string("vec2(0)");
|
||||||
|
}
|
||||||
|
}();
|
||||||
|
|
||||||
|
const std::string second_pred =
|
||||||
|
GetPredicateCondition(instr.hset2.pred39, instr.hset2.neg_pred != 0);
|
||||||
|
|
||||||
|
const std::string combiner = GetPredicateCombiner(instr.hset2.op);
|
||||||
|
|
||||||
|
// HSET2 operates on each half float in the pack.
|
||||||
|
std::string result;
|
||||||
|
for (int i = 0; i < 2; ++i) {
|
||||||
|
const std::string float_value = i == 0 ? "0x00003c00" : "0x3c000000";
|
||||||
|
const std::string integer_value = i == 0 ? "0x0000ffff" : "0xffff0000";
|
||||||
|
const std::string value = instr.hset2.bf == 1 ? float_value : integer_value;
|
||||||
|
|
||||||
|
const std::string comp = std::string(".") + "xy"[i];
|
||||||
|
const std::string predicate =
|
||||||
|
"((" + GetPredicateComparison(instr.hset2.cond, op_a + comp, op_b + comp) +
|
||||||
|
") " + combiner + " (" + second_pred + "))";
|
||||||
|
|
||||||
|
result += '(' + predicate + " ? " + value + " : 0)";
|
||||||
|
if (i == 0) {
|
||||||
|
result += " | ";
|
||||||
|
}
|
||||||
|
}
|
||||||
|
regs.SetRegisterToInteger(instr.gpr0, false, 0, '(' + result + ')', 1, 1);
|
||||||
|
break;
|
||||||
|
}
|
||||||
case OpCode::Type::Xmad: {
|
case OpCode::Type::Xmad: {
|
||||||
ASSERT_MSG(!instr.xmad.sign_a, "Unimplemented");
|
ASSERT_MSG(!instr.xmad.sign_a, "Unimplemented");
|
||||||
ASSERT_MSG(!instr.xmad.sign_b, "Unimplemented");
|
ASSERT_MSG(!instr.xmad.sign_b, "Unimplemented");
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue