Merge pull request #1601 from FernandoS27/shader-precision
Improved Shader accuracy on Vertex and Geometry Shaders.
This commit is contained in:
commit
aa1cf608ed
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@ -341,10 +341,10 @@ public:
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*/
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void SetRegisterToFloat(const Register& reg, u64 elem, const std::string& value,
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u64 dest_num_components, u64 value_num_components,
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bool is_saturated = false, u64 dest_elem = 0) {
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bool is_saturated = false, u64 dest_elem = 0, bool precise = false) {
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SetRegister(reg, elem, is_saturated ? "clamp(" + value + ", 0.0, 1.0)" : value,
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dest_num_components, value_num_components, dest_elem);
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dest_num_components, value_num_components, dest_elem, precise);
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}
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/**
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@ -368,7 +368,7 @@ public:
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const std::string func{is_signed ? "intBitsToFloat" : "uintBitsToFloat"};
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SetRegister(reg, elem, func + '(' + ConvertIntegerSize(value, size) + ')',
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dest_num_components, value_num_components, dest_elem);
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dest_num_components, value_num_components, dest_elem, false);
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if (sets_cc) {
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const std::string zero_condition = "( " + ConvertIntegerSize(value, size) + " == 0 )";
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@ -416,7 +416,7 @@ public:
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}
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}();
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SetRegister(reg, elem, result, dest_num_components, value_num_components, dest_elem);
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SetRegister(reg, elem, result, dest_num_components, value_num_components, dest_elem, false);
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}
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/**
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@ -757,7 +757,8 @@ private:
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* @param dest_elem Optional, the destination element to use for the operation.
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*/
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void SetRegister(const Register& reg, u64 elem, const std::string& value,
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u64 dest_num_components, u64 value_num_components, u64 dest_elem) {
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u64 dest_num_components, u64 value_num_components, u64 dest_elem,
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bool precise) {
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if (reg == Register::ZeroIndex) {
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LOG_CRITICAL(HW_GPU, "Cannot set Register::ZeroIndex");
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UNREACHABLE();
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@ -774,7 +775,18 @@ private:
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src += GetSwizzle(elem);
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}
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shader.AddLine(dest + " = " + src + ';');
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if (precise && stage != Maxwell3D::Regs::ShaderStage::Fragment) {
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shader.AddLine('{');
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++shader.scope;
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// This avoids optimizations of constant propagation and keeps the code as the original
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// Sadly using the precise keyword causes "linking" errors on fragment shaders.
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shader.AddLine("precise float tmp = " + src + ';');
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shader.AddLine(dest + " = tmp;");
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--shader.scope;
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shader.AddLine('}');
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} else {
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shader.AddLine(dest + " = " + src + ';');
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}
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}
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/// Build the GLSL register list.
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@ -1510,8 +1522,9 @@ private:
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ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
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op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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}
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case OpCode::Id::FADD_C:
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@ -1519,8 +1532,9 @@ private:
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case OpCode::Id::FADD_IMM: {
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op_a = GetOperandAbsNeg(op_a, instr.alu.abs_a, instr.alu.negate_a);
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op_b = GetOperandAbsNeg(op_b, instr.alu.abs_b, instr.alu.negate_b);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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}
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case OpCode::Id::MUFU: {
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@ -1528,31 +1542,31 @@ private:
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switch (instr.sub_op) {
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case SubOp::Cos:
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regs.SetRegisterToFloat(instr.gpr0, 0, "cos(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Sin:
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regs.SetRegisterToFloat(instr.gpr0, 0, "sin(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Ex2:
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regs.SetRegisterToFloat(instr.gpr0, 0, "exp2(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Lg2:
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regs.SetRegisterToFloat(instr.gpr0, 0, "log2(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Rcp:
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regs.SetRegisterToFloat(instr.gpr0, 0, "1.0 / " + op_a, 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Rsq:
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regs.SetRegisterToFloat(instr.gpr0, 0, "inversesqrt(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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case SubOp::Sqrt:
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regs.SetRegisterToFloat(instr.gpr0, 0, "sqrt(" + op_a + ')', 1, 1,
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instr.alu.saturate_d);
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instr.alu.saturate_d, 0, true);
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break;
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default:
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LOG_CRITICAL(HW_GPU, "Unhandled MUFU sub op: {0:x}",
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@ -1573,7 +1587,7 @@ private:
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regs.SetRegisterToFloat(instr.gpr0, 0,
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'(' + condition + ") ? min(" + parameters + ") : max(" +
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parameters + ')',
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1, 1);
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1, 1, false, 0, true);
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break;
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}
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case OpCode::Id::RRO_C:
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@ -1602,7 +1616,7 @@ private:
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regs.SetRegisterToFloat(instr.gpr0, 0,
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regs.GetRegisterAsFloat(instr.gpr8) + " * " +
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GetImmediate32(instr),
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1, 1, instr.fmul32.saturate);
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1, 1, instr.fmul32.saturate, 0, true);
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break;
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}
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case OpCode::Id::FADD32I: {
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@ -1625,7 +1639,7 @@ private:
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op_b = "-(" + op_b + ')';
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}
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1, false, 0, true);
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break;
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}
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}
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@ -2087,8 +2101,9 @@ private:
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}
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}
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b + " + " + op_c, 1, 1,
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instr.alu.saturate_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, "fma(" + op_a + ", " + op_b + ", " + op_c + ')',
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1, 1, instr.alu.saturate_d, 0, true);
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break;
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}
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case OpCode::Type::Hfma2: {
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