artemist/yuzu
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

shader_decode: Use proper primitive names

Browse source
This commit is contained in:
ReinUsesLisp 2018-12-26 03:18:11 -03:00
parent 2faad9bf23
commit 50195b1704
4 changed files with 21 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/video_core/renderer_opengl/gl_shader_decompiler.cpp
View file

@ -325,8 +325,8 @@ private:
}
ASSERT(element.second.size() > 0);
// UNIMPLEMENTED_IF_MSG(element.second.size() > 1,
// "Multiple input flag modes are not supported in GLSL");
UNIMPLEMENTED_IF_MSG(element.second.size() > 1,
"Multiple input flag modes are not supported in GLSL");
// TODO(bunnei): Use proper number of elements for these
u32 idx = static_cast<u32>(index) - static_cast<u32>(Attribute::Index::Attribute_0);
@ -1209,7 +1209,7 @@ private:
return expr;
}
std::string Bra(Operation operation) {
std::string Branch(Operation operation) {
const auto target = std::get<ImmediateNode>(*operation[0]);
code.AddLine(fmt::format("jmp_to = 0x{:x}u;", target.GetValue()));
code.AddLine("break;");
@ -1289,7 +1289,7 @@ private:
return {};
}
std::string Kil(Operation operation) {
std::string Discard(Operation operation) {
// Enclose "discard" in a conditional, so that GLSL compilation does not complain
// about unexecuted instructions that may follow this.
code.AddLine("if (true) {");
@ -1449,13 +1449,11 @@ private:
&GLSLDecompiler::F4TextureQueryLod,
&GLSLDecompiler::F4TexelFetch,
&GLSLDecompiler::Bra,
&GLSLDecompiler::PushFlowStack, // Ssy
&GLSLDecompiler::PushFlowStack, // Brk
&GLSLDecompiler::PopFlowStack, // Sync
&GLSLDecompiler::PopFlowStack, // Brk
&GLSLDecompiler::Branch,
&GLSLDecompiler::PushFlowStack,
&GLSLDecompiler::PopFlowStack,
&GLSLDecompiler::Exit,
&GLSLDecompiler::Kil,
&GLSLDecompiler::Discard,
&GLSLDecompiler::EmitVertex,
&GLSLDecompiler::EndPrimitive,

4
src/video_core/shader/decode/memory.cpp
View file

@ -155,8 +155,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
break;
}
case OpCode::Id::ST_L: {
// UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}",
// static_cast<u32>(instr.st_l.unknown.Value()));
UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}",
static_cast<u32>(instr.st_l.unknown.Value()));
const Node index = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8),
Immediate(static_cast<s32>(instr.smem_imm)));

12
src/video_core/shader/decode/other.cpp
View file

@ -54,7 +54,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}",
static_cast<u32>(cc));
bb.push_back(Operation(OperationCode::Kil));
bb.push_back(Operation(OperationCode::Discard));
break;
}
case OpCode::Id::MOV_SYS: {
@ -79,7 +79,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
"BRA with constant buffers are not implemented");
const u32 target = pc + instr.bra.GetBranchTarget();
const Node branch = Operation(OperationCode::Bra, Immediate(target));
const Node branch = Operation(OperationCode::Branch, Immediate(target));
const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
if (cc != Tegra::Shader::ConditionCode::T) {
@ -97,7 +97,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
// target of the jump that the SYNC instruction will make. The SSY opcode has a similar
// structure to the BRA opcode.
const u32 target = pc + instr.bra.GetBranchTarget();
bb.push_back(Operation(OperationCode::Ssy, Immediate(target)));
bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
break;
}
case OpCode::Id::PBK: {
@ -108,7 +108,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
// using SYNC on a PBK address will kill the shader execution. We don't emulate this because
// it's very unlikely a driver will emit such invalid shader.
const u32 target = pc + instr.bra.GetBranchTarget();
bb.push_back(Operation(OperationCode::Pbk, Immediate(target)));
bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
break;
}
case OpCode::Id::SYNC: {
@ -117,7 +117,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
static_cast<u32>(cc));
// The SYNC opcode jumps to the address previously set by the SSY opcode
bb.push_back(Operation(OperationCode::Sync));
bb.push_back(Operation(OperationCode::PopFlowStack));
break;
}
case OpCode::Id::BRK: {
@ -126,7 +126,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
static_cast<u32>(cc));
// The BRK opcode jumps to the address previously set by the PBK opcode
bb.push_back(Operation(OperationCode::Brk));
bb.push_back(Operation(OperationCode::PopFlowStack));
break;
}
case OpCode::Id::IPA: {

12
src/video_core/shader/shader_ir.h
View file

@ -163,13 +163,11 @@ enum class OperationCode {
F4TextureQueryLod, /// (MetaTexture, float[N] coords) -> float4
F4TexelFetch, /// (MetaTexture, int[N], int) -> float4
Bra, /// (uint branch_target) -> void
Ssy, /// (uint branch_target) -> void
Pbk, /// (uint branch_target) -> void
Sync, /// () -> void
Brk, /// () -> void
Exit, /// () -> void
Kil, /// () -> void
Branch, /// (uint branch_target) -> void
PushFlowStack, /// (uint branch_target) -> void
PopFlowStack, /// () -> void
Exit, /// () -> void
Discard, /// () -> void
EmitVertex, /// () -> void
EndPrimitive, /// () -> void