gl_shader_decompiler: Implement HFMA2 instructions
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@ -614,6 +614,29 @@ union Instruction {
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}
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} half_imm;
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union {
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union {
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BitField<37, 2, HalfPrecision> precision;
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BitField<32, 1, u64> saturate;
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BitField<30, 1, u64> negate_c;
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BitField<35, 2, HalfType> type_c;
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} rr;
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BitField<57, 2, HalfPrecision> precision;
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BitField<52, 1, u64> saturate;
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BitField<49, 2, HalfMerge> merge;
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BitField<47, 2, HalfType> type_a;
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BitField<56, 1, u64> negate_b;
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BitField<28, 2, HalfType> type_b;
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BitField<51, 1, u64> negate_c;
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BitField<53, 2, HalfType> type_reg39;
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} hfma2;
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union {
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BitField<40, 1, u64> invert;
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} popc;
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@ -1212,6 +1235,10 @@ public:
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HMUL2_C,
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HMUL2_R,
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HMUL2_IMM,
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HFMA2_CR,
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HFMA2_RC,
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HFMA2_RR,
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HFMA2_IMM_R,
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POPC_C,
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POPC_R,
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POPC_IMM,
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@ -1290,6 +1317,7 @@ public:
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Bfe,
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Shift,
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Ffma,
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Hfma2,
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Flow,
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Synch,
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Memory,
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@ -1464,6 +1492,10 @@ private:
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INST("0111100-1-------", Id::HMUL2_C, Type::ArithmeticHalf, "HMUL2_C"),
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INST("0101110100001---", Id::HMUL2_R, Type::ArithmeticHalf, "HMUL2_R"),
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INST("0111100-0-------", Id::HMUL2_IMM, Type::ArithmeticHalfImmediate, "HMUL2_IMM"),
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INST("01110---1-------", Id::HFMA2_CR, Type::Hfma2, "HFMA2_CR"),
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INST("01100---1-------", Id::HFMA2_RC, Type::Hfma2, "HFMA2_RC"),
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INST("0101110100000---", Id::HFMA2_RR, Type::Hfma2, "HFMA2_RR"),
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INST("01110---0-------", Id::HFMA2_IMM_R, Type::Hfma2, "HFMA2_R_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -1964,6 +1964,59 @@ private:
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instr.alu.saturate_d);
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break;
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}
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case OpCode::Type::Hfma2: {
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if (opcode->GetId() == OpCode::Id::HFMA2_RR) {
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ASSERT_MSG(instr.hfma2.rr.precision == Tegra::Shader::HalfPrecision::None,
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"Unimplemented");
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} else {
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ASSERT_MSG(instr.hfma2.precision == Tegra::Shader::HalfPrecision::None,
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"Unimplemented");
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}
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const bool saturate = opcode->GetId() == OpCode::Id::HFMA2_RR
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? instr.hfma2.rr.saturate != 0
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: instr.hfma2.saturate != 0;
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const std::string op_a =
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GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.hfma2.type_a);
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std::string op_b, op_c;
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switch (opcode->GetId()) {
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case OpCode::Id::HFMA2_CR:
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op_b = GetHalfFloat(regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::UnsignedInteger),
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instr.hfma2.type_b, false, instr.hfma2.negate_b);
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op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
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instr.hfma2.type_reg39, false, instr.hfma2.negate_c);
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break;
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case OpCode::Id::HFMA2_RC:
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op_b = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
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instr.hfma2.type_reg39, false, instr.hfma2.negate_b);
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op_c = GetHalfFloat(regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
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GLSLRegister::Type::UnsignedInteger),
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instr.hfma2.type_b, false, instr.hfma2.negate_c);
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break;
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case OpCode::Id::HFMA2_RR:
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op_b = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
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instr.hfma2.type_b, false, instr.hfma2.negate_b);
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op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
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instr.hfma2.rr.type_c, false, instr.hfma2.rr.negate_c);
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break;
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case OpCode::Id::HFMA2_IMM_R:
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op_b = UnpackHalfImmediate(instr, true);
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op_c = GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr39, 0, false),
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instr.hfma2.type_reg39, false, instr.hfma2.negate_c);
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break;
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default:
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UNREACHABLE();
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op_c = op_b = "vec2(0)";
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break;
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}
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const std::string result = '(' + op_a + " * " + op_b + " + " + op_c + ')';
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regs.SetRegisterToHalfFloat(instr.gpr0, 0, result, instr.hfma2.merge, 1, 1, saturate);
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break;
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}
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case OpCode::Type::Conversion: {
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switch (opcode->GetId()) {
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case OpCode::Id::I2I_R: {
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