arm_disasm: ARMv6 mul/div and abs media instructions
SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD, SMMLA, SMMUL, SMMLS USAD8, USADA8
This commit is contained in:
aroulin
parent
4a1db13072
commit
38c87733d9
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@ -92,8 +92,17 @@ static const char *opcode_names[] = {
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"shsax",
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"shsub16",
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"shsub8",
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"smlad",
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"smlal",
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"smlald",
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"smlsd",
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"smlsld",
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"smmla",
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"smmls",
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"smmul",
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"smuad",
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"smull",
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"smusd",
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"ssat",
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"ssat16",
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"ssax",
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@ -139,6 +148,8 @@ static const char *opcode_names[] = {
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"uqsax",
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"uqsub16",
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"uqsub8",
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"usad8",
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"usada8",
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"usat",
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"usat16",
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"usax",
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@ -341,6 +352,18 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassembleREV(opcode, insn);
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case OP_SEL:
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return DisassembleSEL(insn);
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case OP_SMLAD:
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case OP_SMLALD:
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case OP_SMLSD:
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case OP_SMLSLD:
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case OP_SMMLA:
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case OP_SMMLS:
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case OP_SMMUL:
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case OP_SMUAD:
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case OP_SMUSD:
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case OP_USAD8:
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case OP_USADA8:
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return DisassembleMediaMulDiv(opcode, insn);
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case OP_SSAT:
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case OP_SSAT16:
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case OP_USAT:
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@ -503,6 +526,38 @@ std::string ARM_Disasm::DisassembleCLZ(uint32_t insn)
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return Common::StringFromFormat("clz%s\tr%d, r%d", cond_to_str(cond), rd, rm);
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}
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std::string ARM_Disasm::DisassembleMediaMulDiv(Opcode opcode, uint32_t insn) {
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uint32_t cond = BITS(insn, 28, 31);
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uint32_t rd = BITS(insn, 16, 19);
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uint32_t ra = BITS(insn, 12, 15);
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uint32_t rm = BITS(insn, 8, 11);
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uint32_t m = BIT(insn, 5);
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uint32_t rn = BITS(insn, 0, 3);
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std::string cross = "";
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if (m) {
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if (opcode == OP_SMMLA || opcode == OP_SMMUL || opcode == OP_SMMLS)
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cross = "r";
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else
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cross = "x";
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}
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std::string ext_reg = "";
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std::unordered_set<Opcode, std::hash<int>> with_ext_reg = {
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OP_SMLAD, OP_SMLSD, OP_SMMLA, OP_SMMLS, OP_USADA8
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};
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if (with_ext_reg.find(opcode) != with_ext_reg.end())
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ext_reg = Common::StringFromFormat(", r%u", ra);
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std::string rd_low = "";
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if (opcode == OP_SMLALD || opcode == OP_SMLSLD)
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rd_low = Common::StringFromFormat("r%u, ", ra);
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return Common::StringFromFormat("%s%s%s\t%sr%u, r%u, r%u%s", opcode_names[opcode],
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cross.c_str(), cond_to_str(cond), rd_low.c_str(), rd, rn, rm,
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ext_reg.c_str());
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}
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std::string ARM_Disasm::DisassembleMemblock(Opcode opcode, uint32_t insn)
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{
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std::string tmp_list;
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@ -1339,11 +1394,52 @@ Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
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return OP_MSR;
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}
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Opcode ARM_Disasm::DecodeMediaMulDiv(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 22);
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uint32_t op2_h = BITS(insn, 6, 7);
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uint32_t a = BITS(insn, 12, 15);
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switch (op1) {
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case 0x0:
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if (op2_h == 0x0) {
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if (a != 0xf)
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return OP_SMLAD;
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else
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return OP_SMUAD;
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} else if (op2_h == 0x1) {
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if (a != 0xf)
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return OP_SMLSD;
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else
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return OP_SMUSD;
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}
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break;
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case 0x4:
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if (op2_h == 0x0)
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return OP_SMLALD;
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else if (op2_h == 0x1)
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return OP_SMLSLD;
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break;
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case 0x5:
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if (op2_h == 0x0) {
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if (a != 0xf)
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return OP_SMMLA;
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else
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return OP_SMMUL;
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} else if (op2_h == 0x3) {
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return OP_SMMLS;
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}
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break;
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default:
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break;
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}
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return OP_UNDEFINED;
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}
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Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
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uint32_t op1 = BITS(insn, 20, 24);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t op2 = BITS(insn, 5, 7);
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uint32_t rn = BITS(insn, 0, 3);
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switch (BITS(op1, 3, 4)) {
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case 0x0:
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@ -1352,6 +1448,15 @@ Opcode ARM_Disasm::DecodeMedia(uint32_t insn) {
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case 0x1:
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// Packing, unpacking, saturation, and reversal
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return DecodePackingSaturationReversal(insn);
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case 0x2:
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// Signed multiply, signed and unsigned divide
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return DecodeMediaMulDiv(insn);
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case 0x3:
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if (op2 == 0 && rd == 0xf)
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return OP_USAD8;
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if (op2 == 0 && rd != 0xf)
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return OP_USADA8;
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break;
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default:
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break;
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}
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@ -73,8 +73,17 @@ enum Opcode {
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OP_SHSAX,
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OP_SHSUB16,
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OP_SHSUB8,
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OP_SMLAD,
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OP_SMLAL,
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OP_SMLALD,
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OP_SMLSD,
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OP_SMLSLD,
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OP_SMMLA,
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OP_SMMLS,
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OP_SMMUL,
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OP_SMUAD,
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OP_SMULL,
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OP_SMUSD,
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OP_SSAT,
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OP_SSAT16,
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OP_SSAX,
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@ -120,6 +129,8 @@ enum Opcode {
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OP_UQSAX,
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OP_UQSUB16,
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OP_UQSUB8,
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OP_USAD8,
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OP_USADA8,
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OP_USAT,
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OP_USAT16,
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OP_USAX,
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@ -193,6 +204,7 @@ class ARM_Disasm {
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static Opcode DecodePackingSaturationReversal(uint32_t insn);
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static Opcode DecodeMUL(uint32_t insn);
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static Opcode DecodeMSRImmAndHints(uint32_t insn);
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static Opcode DecodeMediaMulDiv(uint32_t insn);
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static Opcode DecodeMedia(uint32_t insn);
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static Opcode DecodeLDRH(uint32_t insn);
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static Opcode DecodeALU(uint32_t insn);
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@ -202,6 +214,7 @@ class ARM_Disasm {
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static std::string DisassembleBX(uint32_t insn);
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static std::string DisassembleBKPT(uint32_t insn);
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static std::string DisassembleCLZ(uint32_t insn);
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static std::string DisassembleMediaMulDiv(Opcode opcode, uint32_t insn);
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static std::string DisassembleMemblock(Opcode opcode, uint32_t insn);
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static std::string DisassembleMem(uint32_t insn);
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static std::string DisassembleMemHalf(uint32_t insn);
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