artemist/yuzu
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

externals: Update dynarmic to 171d116

Browse source 
171d116 A64: Implement SCVTF, UCVTF (vector, fixed-point), scalar variant
f221bb0 emit_x64_floating_point: Reduce fallback LUT code in EmitFPToFixed
eb123e2 A64: Implement FCVTZS, FCVTZU, UCVTF, SCVTF (vector, fixed-point), vector variant
487d37a A64: Implement UQSHL's vector immediate and register variants
f698933 ir: Add opcodes for unsigned saturating left shifts
7148e66 A64/translate/impl: Make signatures consistent for unimplemented by-element SIMD variants
fdde4ca A64: Implement BRK
b1490db A64/imm: Add full range of comparison operators to Imm template
1ec40ef IR: Add fbits argument to FPVectorFrom{Signed,Unsigned}Fixed
d6d5e98 A64: Implement SCVTF, UCVTF (scalar, fixed-point)
6513595 opcodes.inc: Align columns to a tabstop of 4
6b0d2b5 IR: Add fbits argument to FixedToFP-related opcodes
c4b3831 A64: Implement SQSHL's vector immediate variant
e0d8d2d A64: Implement SQSHL's vector register variant
5327625 ir: Add opcodes for left signed saturated shifts
9705252 branch: Make variables const where applicable
650946e move_wide: Make variables const where applicable
62b3a6d load_store_register_unprivileged: Make variables const where applicable
3add1c7 load_store_register_immediate: Place conditional bodies on their own line
2fc4088 load_store_load_literal: Make variables const where applicable
b2c1462 data_processing_logical: Move datasize declarations after early-exit conditionals
028028f data_processing_conditional_select: Make variables const where applicable
c66042d data_processing_addsub: Move datasize declarations after early-exit conditionals
6bc546e data_processing_bitfield: Move datasize variables after early-exit conditionals
2aad5fa A64: Implement CLS's vector variant
6c877ff emit_x64_vector: Make EmitVectorUnsignedSaturatedAccumulateSigned() internally linked
4b5926d perf_map: Use std::string_view instead of std::string for PerfMapRegister()
7445947 A64: Implement SQRDMULH (vector), vector variant
03b80f2 A64: Implement SQDMULL (vector), vector variant
4a2c596 IR: Add VectorSignedSaturatedDoublingMultiplyLong
59dc33e emit_x64_vector: Changes to VectorSignedSaturatedDoublingMultiply
bbaebeb IR: Implement Vector{Signed,Unsigned}Multiply{16,32}
baac5a8 backend_x64/a64_interface: Re-enable the constant folding pass
e78ca19 emit_x64_vector_floating_point: Hardware FMA implementation for RSqrtStepFused
8a5ae9a emit_x64_vector_floating_point: Hardware FMA implementation of FPVectorRecipStepFused
39818f9 emit_x64_floating_point: Hardware FMA implementation of FPRSqrtStepFused
3d0a0b4 emit_x64_floating_point: Hardware FMA implementation of FPRecipStepFused{32,64}
2293dff emit_x64_vector: SSE implementation of VectorSignedSaturatedAccumulateUnsigned{8,16,32}
2047683 emit_x64_vector: Correct static asserts for < 64-bit type checks in saturated accumulate fallbacks
55e9e40 emit_x64_vector: EmitVectorSignedSaturatedAccumulateUnsigned64: SSE implementation
1076651 emit_x64_vector: Simplify fpsr_qc related code
4039030 A64: Implement CLZ's vector variant
0bb908f ir: Add opcodes for vector CLZ operations
3b13259 A64/translate: VectorZeroUpper for V(64) stores
1931d44 simd_two_register_misc: FNEG (vector) with Q == 0 had dirty upper
a0790f0 emit_x64_vector: Remove unnecessary [[maybe_unused]] attributes
b0e1eb5 A64: Implement USQADD's scalar and vector variants
28424c7 ir: Add opcodes form unsigned saturated accumulations of signed values
9923ea0 A64: Implement SUQADD's scalar and vector variants
4c0adbb ir: Add opcodes for signed saturated accumulations of unsigned values
799bfed A64: Implement SMLAL{2}, SMLSL{2}, UMLAL{2}, and UMLSL{2}'s vector by-element variants
94451ec A64: Implement UMULL{2}'s vector by-element variant
45867de A64: Implement SMULL{2}'s vector by-element variant
0235793 ir/value: Replace includes with forward declarations
450f721 ir/cond: Migrate to C++17 nested namespace specifiers
e649988 CMakeLists: Add missing cond.h header to file listing
d20e769 A64: Implement URSQRTE
4f3bde5 ir: Add opcodes for performing unsigned reciprocal square root estimates
cfeeaec A64: Implement URECPE
622b60e ir: Add opcodes for unsigned reciprocal estimate
d17599a Update Xbyak to 5.71
f7c26e9 Squashed 'externals/xbyak/' changes from 671fc805..1de435ed
8782b69 travis: Make macOS build with Xcode 9.4.1
b575b23 A64: Implement SQNEG's scalar and vector variant
06062a9 A64: Add opcodes for signed saturating negations
1c40579 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtract()
e335050 emit_x64_vector: Simplify "position == 0" case for EmitVectorExtractLower()
8b13421 A64: Implement SQDMULH's by-element scalar variant
9122a6e A64: Implement SQDMULH's by-element vector variant
176e60e backend/x64: Do not clear fast_dispatch_table if not enabled
This commit is contained in:
MerryMage 2018-09-19 20:26:37 +01:00
parent 0432af5ad1
commit 321eb0b6b0
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
externals/dynarmic vendored

@ -1 +1 @@
Subproject commit 959446573f3adfcba173ef4b0011a4a280f18eba
Subproject commit 171d11659d760a4d4674d3a90698fe31ea407e2e