shader_decode: get sampler descriptor from registry.
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namkazy
parent
acd3f0ab37
commit
24cc64c5b3
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@ -10,8 +10,6 @@
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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@ -28,8 +26,10 @@ using Tegra::Texture::TextureFormat;
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using Tegra::Texture::TICEntry;
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namespace {
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ComponentType GetComponentType(TICEntry tic, std::size_t component) {
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const TextureFormat format{tic.format};
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ComponentType GetComponentType(Tegra::Engines::SamplerDescriptor descriptor, std::size_t component) {
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const TextureFormat format{descriptor.format};
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switch (format) {
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case TextureFormat::R16_G16_B16_A16:
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case TextureFormat::R32_G32_B32_A32:
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@ -40,82 +40,82 @@ ComponentType GetComponentType(TICEntry tic, std::size_t component) {
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case TextureFormat::R16:
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case TextureFormat::R8:
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case TextureFormat::R1:
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if (0 == component) {
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return tic.r_type;
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if (component == 0) {
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return descriptor.r_type;
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}
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if (1 == component) {
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return tic.g_type;
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if (component == 1) {
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return descriptor.g_type;
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}
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if (2 == component) {
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return tic.b_type;
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if (component == 2) {
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return descriptor.b_type;
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}
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if (3 == component) {
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return tic.a_type;
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if (component == 3) {
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return descriptor.a_type;
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}
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break;
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case TextureFormat::A8R8G8B8:
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if (0 == component) {
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return tic.a_type;
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if (component == 0) {
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return descriptor.a_type;
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}
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if (1 == component) {
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return tic.r_type;
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if (component == 1) {
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return descriptor.r_type;
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}
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if (2 == component) {
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return tic.g_type;
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if (component == 2) {
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return descriptor.g_type;
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}
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if (3 == component) {
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return tic.b_type;
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if (component == 3) {
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return descriptor.b_type;
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}
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break;
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case TextureFormat::A2B10G10R10:
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case TextureFormat::A4B4G4R4:
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case TextureFormat::A5B5G5R1:
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case TextureFormat::A1B5G5R5:
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if (0 == component) {
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return tic.a_type;
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if (component == 0) {
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return descriptor.a_type;
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}
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if (1 == component) {
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return tic.b_type;
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if (component == 1) {
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return descriptor.b_type;
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}
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if (2 == component) {
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return tic.g_type;
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if (component == 2) {
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return descriptor.g_type;
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}
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if (3 == component) {
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return tic.r_type;
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if (component == 3) {
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return descriptor.r_type;
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}
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break;
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case TextureFormat::R32_B24G8:
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if (0 == component) {
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return tic.r_type;
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if (component == 0) {
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return descriptor.r_type;
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}
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if (1 == component) {
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return tic.b_type;
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if (component == 1) {
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return descriptor.b_type;
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}
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if (2 == component) {
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return tic.g_type;
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if (component == 2) {
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return descriptor.g_type;
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}
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break;
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case TextureFormat::B5G6R5:
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case TextureFormat::B6G5R5:
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if (0 == component) {
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return tic.b_type;
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if (component == 0) {
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return descriptor.b_type;
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}
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if (1 == component) {
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return tic.g_type;
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if (component == 1) {
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return descriptor.g_type;
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}
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if (2 == component) {
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return tic.r_type;
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if (component == 2) {
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return descriptor.r_type;
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}
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break;
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case TextureFormat::G8R24:
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case TextureFormat::G24R8:
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case TextureFormat::G8R8:
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case TextureFormat::G4R4:
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if (0 == component) {
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return tic.g_type;
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if (component == 0) {
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return descriptor.g_type;
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}
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if (1 == component) {
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return tic.r_type;
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if (component == 1) {
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return descriptor.r_type;
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}
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break;
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}
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@ -141,76 +141,76 @@ u32 GetComponentSize(TextureFormat format, std::size_t component) {
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case TextureFormat::R16_G16_B16_A16:
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return 16;
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case TextureFormat::R32_G32_B32:
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return (0 == component || 1 == component || 2 == component) ? 32 : 0;
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return (component == 0 || component == 1 || component == 2) ? 32 : 0;
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case TextureFormat::R32_G32:
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return (0 == component || 1 == component) ? 32 : 0;
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return (component == 0 || component == 1) ? 32 : 0;
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case TextureFormat::R16_G16:
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return (0 == component || 1 == component) ? 16 : 0;
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return (component == 0 || component == 1) ? 16 : 0;
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case TextureFormat::R32:
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return (0 == component) ? 32 : 0;
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return (component == 0) ? 32 : 0;
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case TextureFormat::R16:
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return (0 == component) ? 16 : 0;
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return (component == 0) ? 16 : 0;
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case TextureFormat::R8:
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return (0 == component) ? 8 : 0;
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return (component == 0) ? 8 : 0;
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case TextureFormat::R1:
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return (0 == component) ? 1 : 0;
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return (component == 0) ? 1 : 0;
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case TextureFormat::A8R8G8B8:
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return 8;
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case TextureFormat::A2B10G10R10:
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return (3 == component || 2 == component || 1 == component) ? 10 : 2;
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return (component == 3 || component == 2 || component == 1) ? 10 : 2;
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case TextureFormat::A4B4G4R4:
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return 4;
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case TextureFormat::A5B5G5R1:
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return (0 == component || 1 == component || 2 == component) ? 5 : 1;
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return (component == 0 || component == 1 || component == 2) ? 5 : 1;
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case TextureFormat::A1B5G5R5:
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return (1 == component || 2 == component || 3 == component) ? 5 : 1;
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return (component == 1 || component == 2 || component == 3) ? 5 : 1;
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case TextureFormat::R32_B24G8:
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if (0 == component) {
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if (component == 0) {
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return 32;
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}
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if (1 == component) {
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if (component == 1) {
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return 24;
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}
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if (2 == component) {
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if (component == 2) {
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return 8;
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}
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return 0;
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case TextureFormat::B5G6R5:
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if (0 == component || 2 == component) {
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if (component == 0 || component == 2) {
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return 5;
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}
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if (1 == component) {
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if (component == 1) {
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return 6;
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}
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return 0;
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case TextureFormat::B6G5R5:
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if (1 == component || 2 == component) {
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if (component == 1 || component == 2) {
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return 5;
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}
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if (0 == component) {
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if (component == 0) {
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return 6;
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}
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return 0;
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case TextureFormat::G8R24:
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if (0 == component) {
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if (component == 0) {
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return 8;
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}
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if (1 == component) {
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if (component == 1) {
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return 24;
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}
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return 0;
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case TextureFormat::G24R8:
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if (0 == component) {
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if (component == 0) {
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return 8;
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}
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if (1 == component) {
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if (component == 1) {
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return 24;
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}
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return 0;
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case TextureFormat::G8R8:
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return (0 == component || 1 == component) ? 8 : 0;
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return (component == 0 || component == 1) ? 8 : 0;
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case TextureFormat::G4R4:
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return (0 == component || 1 == component) ? 4 : 0;
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return (component == 0 || component == 1) ? 4 : 0;
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default:
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UNIMPLEMENTED_MSG("texture format not implement={}", format);
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return 0;
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@ -311,10 +311,23 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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} else if (instr.suldst.mode == Tegra::Shader::SurfaceDataMode::D_BA) {
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UNIMPLEMENTED_IF(instr.suldst.GetStoreDataLayout() != StoreType::Bits32);
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const auto maxwell3d = &Core::System::GetInstance().GPU().Maxwell3D();
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const auto tex_info = maxwell3d->GetStageTexture(shader_stage, image.GetOffset());
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auto descriptor = [this, instr] {
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std::optional<Tegra::Engines::SamplerDescriptor> descriptor;
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if (instr.suldst.is_immediate) {
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descriptor = registry.ObtainBoundSampler(instr.image.index.Value());
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} else {
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const Node image_register = GetRegister(instr.gpr39);
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const auto [base_image, buffer, offset] = TrackCbuf(
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image_register, global_code, static_cast<s64>(global_code.size()));
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descriptor = registry.ObtainBindlessSampler(buffer, offset);
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}
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if (!descriptor) {
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UNREACHABLE_MSG("Failed to obtain image descriptor");
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}
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return *descriptor;
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}();
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const auto comp_mask = GetImageComponentMask(tex_info.tic.format);
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const auto comp_mask = GetImageComponentMask(descriptor.format);
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// TODO(namkazt): let's suppose image format is same as store type. we check on it
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// later.
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@ -327,8 +340,8 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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if (!IsComponentEnabled(comp_mask, element)) {
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continue;
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}
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const auto component_type = GetComponentType(tex_info.tic, element);
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const auto component_size = GetComponentSize(tex_info.tic.format, element);
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const auto component_type = GetComponentType(descriptor, element);
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const auto component_size = GetComponentSize(descriptor.format, element);
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bool is_signed = true;
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MetaImage meta{image, {}, element};
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const Node original_value =
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@ -339,20 +352,23 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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case ComponentType::SNORM: {
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// range [-1.0, 1.0]
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auto cnv_value =
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Operation(OperationCode::FMul, original_value, Immediate(128.f));
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Operation(OperationCode::FAdd, original_value, Immediate(1.f));
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cnv_value = Operation(OperationCode::FMul, std::move(cnv_value),
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Immediate(127.f));
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is_signed = false;
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return SignedOperation(OperationCode::ICastFloat, is_signed,
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std::move(cnv_value));
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}
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case ComponentType::UNORM: {
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// range [0.0, 1.0]
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auto cnv_value =
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Operation(OperationCode::FMul, original_value, Immediate(256.f));
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Operation(OperationCode::FMul, original_value, Immediate(255.f));
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is_signed = false;
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return SignedOperation(OperationCode::ICastFloat, is_signed,
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std::move(cnv_value));
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}
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case ComponentType::SINT: // range [-128,128]
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return original_value;
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return Operation(OperationCode::IAdd, original_value, Immediate(128));
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case ComponentType::UINT: // range [0, 255]
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is_signed = false;
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return original_value;
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@ -364,13 +380,13 @@ u32 ShaderIR::DecodeImage(NodeBlock& bb, u32 pc) {
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}
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}();
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// shift element to correct position
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shifted_counter += component_size;
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const auto shifted = 32 - shifted_counter;
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const auto shifted = shifted_counter;
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if (shifted > 0) {
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converted_value =
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SignedOperation(OperationCode::ILogicalShiftLeft, is_signed,
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std::move(converted_value), Immediate(shifted));
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}
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shifted_counter += component_size;
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// add value into result
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value = Operation(OperationCode::UBitwiseOr, value, std::move(converted_value));
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