Merge pull request #9234 from liamwhite/data-cash-money
kernel: implement data cache management operations
This commit is contained in:
commit
1fb33bd1e1
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@ -34,6 +34,8 @@ add_library(common STATIC
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bit_util.h
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bit_util.h
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cityhash.cpp
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cityhash.cpp
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cityhash.h
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cityhash.h
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cache_management.cpp
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cache_management.h
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common_funcs.h
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common_funcs.h
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common_types.h
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common_types.h
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concepts.h
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concepts.h
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60
src/common/cache_management.cpp
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60
src/common/cache_management.cpp
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@ -0,0 +1,60 @@
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// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <cstring>
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#include "alignment.h"
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#include "cache_management.h"
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#include "common_types.h"
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namespace Common {
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#if defined(ARCHITECTURE_x86_64)
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// Most cache operations are no-ops on x86
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void DataCacheLineCleanByVAToPoU(void* start, size_t size) {}
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void DataCacheLineCleanAndInvalidateByVAToPoC(void* start, size_t size) {}
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void DataCacheLineCleanByVAToPoC(void* start, size_t size) {}
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void DataCacheZeroByVA(void* start, size_t size) {
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std::memset(start, 0, size);
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}
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#elif defined(ARCHITECTURE_arm64)
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// BS/DminLine is log2(cache size in words), we want size in bytes
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#define EXTRACT_DMINLINE(ctr_el0) (1 << ((((ctr_el0) >> 16) & 0xf) + 2))
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#define EXTRACT_BS(dczid_el0) (1 << (((dczid_el0)&0xf) + 2))
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#define DEFINE_DC_OP(op_name, function_name) \
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void function_name(void* start, size_t size) { \
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size_t ctr_el0; \
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asm volatile("mrs %[ctr_el0], ctr_el0\n\t" : [ctr_el0] "=r"(ctr_el0)); \
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size_t cacheline_size = EXTRACT_DMINLINE(ctr_el0); \
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uintptr_t va_start = reinterpret_cast<uintptr_t>(start); \
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uintptr_t va_end = va_start + size; \
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for (uintptr_t va = va_start; va < va_end; va += cacheline_size) { \
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asm volatile("dc " #op_name ", %[va]\n\t" : : [va] "r"(va) : "memory"); \
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} \
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}
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#define DEFINE_DC_OP_DCZID(op_name, function_name) \
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void function_name(void* start, size_t size) { \
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size_t dczid_el0; \
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asm volatile("mrs %[dczid_el0], dczid_el0\n\t" : [dczid_el0] "=r"(dczid_el0)); \
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size_t cacheline_size = EXTRACT_BS(dczid_el0); \
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uintptr_t va_start = reinterpret_cast<uintptr_t>(start); \
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uintptr_t va_end = va_start + size; \
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for (uintptr_t va = va_start; va < va_end; va += cacheline_size) { \
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asm volatile("dc " #op_name ", %[va]\n\t" : : [va] "r"(va) : "memory"); \
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} \
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}
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DEFINE_DC_OP(cvau, DataCacheLineCleanByVAToPoU);
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DEFINE_DC_OP(civac, DataCacheLineCleanAndInvalidateByVAToPoC);
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DEFINE_DC_OP(cvac, DataCacheLineCleanByVAToPoC);
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DEFINE_DC_OP_DCZID(zva, DataCacheZeroByVA);
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#endif
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} // namespace Common
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27
src/common/cache_management.h
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27
src/common/cache_management.h
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@ -0,0 +1,27 @@
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// SPDX-FileCopyrightText: Copyright 2022 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include "stdlib.h"
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namespace Common {
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// Data cache instructions enabled at EL0 by SCTLR_EL1.UCI.
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// VA = virtual address
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// PoC = point of coherency
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// PoU = point of unification
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// dc cvau
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void DataCacheLineCleanByVAToPoU(void* start, size_t size);
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// dc civac
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void DataCacheLineCleanAndInvalidateByVAToPoC(void* start, size_t size);
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// dc cvac
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void DataCacheLineCleanByVAToPoC(void* start, size_t size);
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// dc zva
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void DataCacheZeroByVA(void* start, size_t size);
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} // namespace Common
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@ -2701,14 +2701,24 @@ static Result GetThreadList(Core::System& system, u32* out_num_threads, VAddr ou
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return ResultSuccess;
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return ResultSuccess;
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}
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}
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static Result FlushProcessDataCache32([[maybe_unused]] Core::System& system,
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static Result FlushProcessDataCache32(Core::System& system, Handle process_handle, u64 address,
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[[maybe_unused]] Handle handle, [[maybe_unused]] u32 address,
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u64 size) {
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[[maybe_unused]] u32 size) {
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// Validate address/size.
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// Note(Blinkhawk): For emulation purposes of the data cache this is mostly a no-op,
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R_UNLESS(size > 0, ResultInvalidSize);
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// as all emulation is done in the same cache level in host architecture, thus data cache
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R_UNLESS(address == static_cast<uintptr_t>(address), ResultInvalidCurrentMemory);
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// does not need flushing.
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R_UNLESS(size == static_cast<size_t>(size), ResultInvalidCurrentMemory);
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LOG_DEBUG(Kernel_SVC, "called");
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return ResultSuccess;
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// Get the process from its handle.
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KScopedAutoObject process =
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system.Kernel().CurrentProcess()->GetHandleTable().GetObject<KProcess>(process_handle);
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R_UNLESS(process.IsNotNull(), ResultInvalidHandle);
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// Verify the region is within range.
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auto& page_table = process->PageTable();
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R_UNLESS(page_table.Contains(address, size), ResultInvalidCurrentMemory);
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// Perform the operation.
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R_RETURN(system.Memory().FlushDataCache(*process, address, size));
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}
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}
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namespace {
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namespace {
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@ -722,4 +722,12 @@ void SvcWrap32(Core::System& system) {
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FuncReturn(system, retval);
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FuncReturn(system, retval);
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}
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}
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// Used by Invalidate/Store/FlushProcessDataCache32
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template <Result func(Core::System&, Handle, u64, u64)>
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void SvcWrap32(Core::System& system) {
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const u64 address = (Param(system, 3) << 32) | Param(system, 2);
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const u64 size = (Param(system, 4) << 32) | Param(system, 1);
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FuncReturn32(system, func(system, Param32(system, 0), address, size).raw);
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}
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} // namespace Kernel
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} // namespace Kernel
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@ -6,6 +6,7 @@
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/atomic_ops.h"
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#include "common/atomic_ops.h"
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#include "common/cache_management.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "common/page_table.h"
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#include "common/page_table.h"
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@ -329,6 +330,55 @@ struct Memory::Impl {
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});
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});
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}
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}
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template <typename Callback>
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Result PerformCacheOperation(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size,
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Callback&& cb) {
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class InvalidMemoryException : public std::exception {};
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try {
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WalkBlock(
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process, dest_addr, size,
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[&](const std::size_t block_size, const VAddr current_vaddr) {
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LOG_ERROR(HW_Memory, "Unmapped cache maintenance @ {:#018X}", current_vaddr);
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throw InvalidMemoryException();
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},
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[&](const std::size_t block_size, u8* const host_ptr) { cb(block_size, host_ptr); },
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[&](const VAddr current_vaddr, const std::size_t block_size, u8* const host_ptr) {
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system.GPU().FlushRegion(current_vaddr, block_size);
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cb(block_size, host_ptr);
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},
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[](const std::size_t block_size) {});
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} catch (InvalidMemoryException&) {
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return Kernel::ResultInvalidCurrentMemory;
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}
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return ResultSuccess;
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}
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Result InvalidateDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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// Do nothing; this operation (dc ivac) cannot be supported
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// from EL0
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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}
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Result StoreDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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// dc cvac: Store to point of coherency
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Common::DataCacheLineCleanByVAToPoC(host_ptr, block_size);
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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}
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Result FlushDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size) {
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auto perform = [&](const std::size_t block_size, u8* const host_ptr) {
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// dc civac: Store to point of coherency, and invalidate from cache
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Common::DataCacheLineCleanAndInvalidateByVAToPoC(host_ptr, block_size);
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};
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return PerformCacheOperation(process, dest_addr, size, perform);
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}
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void MarkRegionDebug(VAddr vaddr, u64 size, bool debug) {
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void MarkRegionDebug(VAddr vaddr, u64 size, bool debug) {
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if (vaddr == 0) {
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if (vaddr == 0) {
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return;
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return;
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@ -786,6 +836,21 @@ void Memory::ZeroBlock(const Kernel::KProcess& process, VAddr dest_addr, const s
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impl->ZeroBlock(process, dest_addr, size);
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impl->ZeroBlock(process, dest_addr, size);
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}
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}
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Result Memory::InvalidateDataCache(const Kernel::KProcess& process, VAddr dest_addr,
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const std::size_t size) {
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return impl->InvalidateDataCache(process, dest_addr, size);
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}
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Result Memory::StoreDataCache(const Kernel::KProcess& process, VAddr dest_addr,
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const std::size_t size) {
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return impl->StoreDataCache(process, dest_addr, size);
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}
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Result Memory::FlushDataCache(const Kernel::KProcess& process, VAddr dest_addr,
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const std::size_t size) {
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return impl->FlushDataCache(process, dest_addr, size);
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}
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void Memory::RasterizerMarkRegionCached(VAddr vaddr, u64 size, bool cached) {
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void Memory::RasterizerMarkRegionCached(VAddr vaddr, u64 size, bool cached) {
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impl->RasterizerMarkRegionCached(vaddr, size, cached);
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impl->RasterizerMarkRegionCached(vaddr, size, cached);
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}
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}
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@ -7,6 +7,7 @@
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#include <memory>
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#include <memory>
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#include <string>
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#include <string>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "core/hle/result.h"
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namespace Common {
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namespace Common {
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struct PageTable;
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struct PageTable;
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@ -449,6 +450,39 @@ public:
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*/
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*/
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void ZeroBlock(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size);
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void ZeroBlock(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size);
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/**
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* Invalidates a range of bytes within the current process' address space at the specified
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* virtual address.
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*
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* @param process The process that will have data invalidated within its address space.
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* @param dest_addr The destination virtual address to invalidate the data from.
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* @param size The size of the range to invalidate, in bytes.
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*
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*/
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Result InvalidateDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size);
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/**
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* Stores a range of bytes within the current process' address space at the specified
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* virtual address.
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*
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* @param process The process that will have data stored within its address space.
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* @param dest_addr The destination virtual address to store the data from.
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* @param size The size of the range to store, in bytes.
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*
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*/
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Result StoreDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size);
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/**
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* Flushes a range of bytes within the current process' address space at the specified
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* virtual address.
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*
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* @param process The process that will have data flushed within its address space.
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* @param dest_addr The destination virtual address to flush the data from.
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* @param size The size of the range to flush, in bytes.
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*
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*/
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Result FlushDataCache(const Kernel::KProcess& process, VAddr dest_addr, std::size_t size);
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/**
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/**
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* Marks each page within the specified address range as cached or uncached.
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* Marks each page within the specified address range as cached or uncached.
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*
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*
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