gl_shader_decompiler: Setup base for half float unpacking and setting
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@ -335,6 +335,26 @@ enum class IsberdMode : u64 {
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enum class IsberdShift : u64 { None = 0, U16 = 1, B32 = 2 };
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enum class HalfType : u64 {
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H0_H1 = 0,
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F32 = 1,
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H0_H0 = 2,
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H1_H1 = 3,
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};
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enum class HalfMerge : u64 {
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H0_H1 = 0,
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F32 = 1,
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Mrg_H0 = 2,
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Mrg_H1 = 3,
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};
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enum class HalfPrecision : u64 {
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None = 0,
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FTZ = 1,
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FMZ = 2,
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};
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enum class IpaInterpMode : u64 {
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Linear = 0,
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Perspective = 1,
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@ -375,6 +375,49 @@ public:
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}
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}
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/**
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* Writes code that does a register assignment to a half float value operation.
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* @param reg The destination register to use.
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* @param elem The element to use for the operation.
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* @param value The code representing the value to assign. Type has to be half float.
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* @param type Half float kind of assignment.
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* @param dest_num_components Number of components in the destionation.
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* @param value_num_components Number of components in the value.
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* @param is_saturated Optional, when True, saturates the provided value.
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* @param dest_elem Optional, the destination element to use for the operation.
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*/
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void SetRegisterToHalfFloat(const Register& reg, u64 elem, const std::string& value,
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Tegra::Shader::HalfMerge merge, u64 dest_num_components,
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u64 value_num_components, bool is_saturated = false,
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u64 dest_elem = 0) {
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ASSERT_MSG(!is_saturated, "Unimplemented");
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const std::string result = [&]() {
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switch (merge) {
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case Tegra::Shader::HalfMerge::H0_H1:
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return "uintBitsToFloat(packHalf2x16(" + value + "))";
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case Tegra::Shader::HalfMerge::F32:
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// Half float instructions take the first component when doing a float cast.
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return "float(" + value + ".x)";
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case Tegra::Shader::HalfMerge::Mrg_H0:
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// TODO(Rodrigo): I guess Mrg_H0 and Mrg_H1 take their respective component from the
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// pack. I couldn't test this on hardware but it shouldn't really matter since most
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// of the time when a Mrg_* flag is used both components will be mirrored. That
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// being said, it deserves a test.
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return "((" + GetRegisterAsInteger(reg, 0, false) +
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" & 0xffff0000) | (packHalf2x16(" + value + ") & 0x0000ffff))";
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case Tegra::Shader::HalfMerge::Mrg_H1:
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return "((" + GetRegisterAsInteger(reg, 0, false) +
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" & 0x0000ffff) | (packHalf2x16(" + value + ") & 0xffff0000))";
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default:
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UNREACHABLE();
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return std::string("0");
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}
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}();
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SetRegister(reg, elem, result, dest_num_components, value_num_components, dest_elem);
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}
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/**
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* Writes code that does a register assignment to input attribute operation. Input attributes
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* are stored as floats, so this may require conversion.
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@ -1012,6 +1055,41 @@ private:
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return result;
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}
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/*
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* Transforms the input string GLSL operand into an unpacked half float pair.
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* @note This function returns a float type pair instead of a half float pair. This is because
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* real half floats are not standarized in GLSL but unpackHalf2x16 (which returns a vec2) is.
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* @param operand Input operand. It has to be an unsigned integer.
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* @param type How to unpack the unsigned integer to a half float pair.
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* @param abs Get the absolute value of unpacked half floats.
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* @param neg Get the negative value of unpacked half floats.
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* @returns String corresponding to a half float pair.
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*/
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static std::string GetHalfFloat(const std::string& operand,
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Tegra::Shader::HalfType type = Tegra::Shader::HalfType::H0_H1,
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bool abs = false, bool neg = false) {
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// "vec2" calls emitted in this function are intended to alias components.
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const std::string value = [&]() {
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switch (type) {
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case Tegra::Shader::HalfType::H0_H1:
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return "unpackHalf2x16(" + operand + ')';
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case Tegra::Shader::HalfType::F32:
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return "vec2(uintBitsToFloat(" + operand + "))";
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case Tegra::Shader::HalfType::H0_H0:
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case Tegra::Shader::HalfType::H1_H1: {
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const bool high = type == Tegra::Shader::HalfType::H1_H1;
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const char unpack_index = "xy"[high ? 1 : 0];
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return "vec2(unpackHalf2x16(" + operand + ")." + unpack_index + ')';
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}
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default:
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UNREACHABLE();
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return std::string("vec2(0)");
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}
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}();
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return GetOperandAbsNeg(value, abs, neg);
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}
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/*
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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