2014-09-12 22:34:51 +00:00
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// Copyright 2014 Citra Emulator Project
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2014-12-17 05:38:14 +00:00
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// Licensed under GPLv2 or any later version
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2014-11-19 08:49:13 +00:00
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// Refer to the license.txt file included.
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2014-09-12 22:34:51 +00:00
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2016-09-20 15:21:23 +00:00
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#include "core/arm/dyncom/arm_dyncom.h"
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2015-05-06 07:06:12 +00:00
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#include <cstring>
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2016-04-05 12:29:55 +00:00
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#include <memory>
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2014-09-12 22:34:51 +00:00
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#include "core/arm/dyncom/arm_dyncom_interpreter.h"
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2015-02-12 20:11:39 +00:00
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#include "core/arm/dyncom/arm_dyncom_run.h"
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2016-06-27 18:38:49 +00:00
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#include "core/arm/dyncom/arm_dyncom_trans.h"
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2016-09-20 15:21:23 +00:00
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#include "core/arm/skyeye_common/armstate.h"
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#include "core/arm/skyeye_common/armsupp.h"
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#include "core/arm/skyeye_common/vfp/vfp.h"
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2014-12-22 06:30:09 +00:00
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#include "core/core.h"
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2015-01-06 01:17:49 +00:00
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#include "core/core_timing.h"
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2015-02-12 20:11:39 +00:00
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ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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2016-04-05 12:29:55 +00:00
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state = std::make_unique<ARMul_State>(initial_mode);
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2014-09-12 22:34:51 +00:00
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}
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2016-09-19 01:01:46 +00:00
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ARM_DynCom::~ARM_DynCom() {}
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2014-09-12 22:34:51 +00:00
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2016-06-27 18:38:49 +00:00
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void ARM_DynCom::ClearInstructionCache() {
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state->instruction_cache.clear();
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trans_cache_buf_top = 0;
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}
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2014-09-12 22:34:51 +00:00
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void ARM_DynCom::SetPC(u32 pc) {
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2015-02-01 02:44:35 +00:00
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state->Reg[15] = pc;
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2014-09-12 22:34:51 +00:00
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}
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u32 ARM_DynCom::GetPC() const {
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2014-11-09 22:00:59 +00:00
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return state->Reg[15];
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2014-09-12 22:34:51 +00:00
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}
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u32 ARM_DynCom::GetReg(int index) const {
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return state->Reg[index];
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}
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void ARM_DynCom::SetReg(int index, u32 value) {
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state->Reg[index] = value;
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}
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2015-08-07 01:24:25 +00:00
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u32 ARM_DynCom::GetVFPReg(int index) const {
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return state->ExtReg[index];
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}
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void ARM_DynCom::SetVFPReg(int index, u32 value) {
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state->ExtReg[index] = value;
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}
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u32 ARM_DynCom::GetVFPSystemReg(VFPSystemRegister reg) const {
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return state->VFP[reg];
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}
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void ARM_DynCom::SetVFPSystemReg(VFPSystemRegister reg, u32 value) {
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state->VFP[reg] = value;
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}
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2014-09-12 22:34:51 +00:00
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u32 ARM_DynCom::GetCPSR() const {
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return state->Cpsr;
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}
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void ARM_DynCom::SetCPSR(u32 cpsr) {
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state->Cpsr = cpsr;
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}
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2015-04-06 16:57:49 +00:00
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u32 ARM_DynCom::GetCP15Register(CP15Register reg) {
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return state->CP15[reg];
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}
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void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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state->CP15[reg] = value;
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}
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2014-12-24 03:45:52 +00:00
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void ARM_DynCom::AddTicks(u64 ticks) {
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2015-01-06 01:17:49 +00:00
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down_count -= ticks;
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if (down_count < 0)
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CoreTiming::Advance();
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2014-12-24 03:45:52 +00:00
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}
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2014-09-12 22:34:51 +00:00
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void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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state->NumInstrsToExecute = num_instructions;
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2014-11-09 06:26:03 +00:00
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// Dyncom only breaks on instruction dispatch. This only happens on every instruction when
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2014-11-19 08:49:13 +00:00
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// executing one instruction at a time. Otherwise, if a block is being executed, more
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2014-11-09 06:26:03 +00:00
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// instructions may actually be executed than specified.
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2015-01-06 01:17:49 +00:00
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unsigned ticks_executed = InterpreterMainLoop(state.get());
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AddTicks(ticks_executed);
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2014-09-12 22:34:51 +00:00
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}
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2014-12-22 06:30:09 +00:00
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void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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2015-07-26 15:39:57 +00:00
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memcpy(ctx.cpu_registers, state->Reg.data(), sizeof(ctx.cpu_registers));
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memcpy(ctx.fpu_registers, state->ExtReg.data(), sizeof(ctx.fpu_registers));
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2014-09-12 22:34:51 +00:00
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ctx.sp = state->Reg[13];
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ctx.lr = state->Reg[14];
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2014-11-09 22:00:59 +00:00
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ctx.pc = state->Reg[15];
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2014-09-12 22:34:51 +00:00
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ctx.cpsr = state->Cpsr;
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2016-09-02 12:39:42 +00:00
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ctx.fpscr = state->VFP[VFP_FPSCR];
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ctx.fpexc = state->VFP[VFP_FPEXC];
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2014-09-12 22:34:51 +00:00
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}
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2014-12-22 06:30:09 +00:00
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void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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2015-07-26 15:39:57 +00:00
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memcpy(state->Reg.data(), ctx.cpu_registers, sizeof(ctx.cpu_registers));
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memcpy(state->ExtReg.data(), ctx.fpu_registers, sizeof(ctx.fpu_registers));
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2014-09-12 22:34:51 +00:00
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state->Reg[13] = ctx.sp;
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state->Reg[14] = ctx.lr;
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2015-02-01 02:44:35 +00:00
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state->Reg[15] = ctx.pc;
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2014-09-12 22:34:51 +00:00
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state->Cpsr = ctx.cpsr;
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2016-09-02 12:39:42 +00:00
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state->VFP[VFP_FPSCR] = ctx.fpscr;
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state->VFP[VFP_FPEXC] = ctx.fpexc;
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2014-09-12 22:34:51 +00:00
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}
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void ARM_DynCom::PrepareReschedule() {
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state->NumInstrsToExecute = 0;
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}
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