2014-04-16 04:03:41 +00:00
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "common/log.h"
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2014-05-08 01:04:55 +00:00
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#include "common/bit_field.h"
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2014-04-16 04:03:41 +00:00
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2014-04-26 05:48:24 +00:00
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#include "core/mem_map.h"
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2014-04-16 04:03:41 +00:00
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#include "core/hle/hle.h"
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2014-06-01 14:41:23 +00:00
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#include "core/hle/kernel/event.h"
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2014-07-05 04:59:58 +00:00
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#include "core/hle/kernel/shared_memory.h"
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2014-04-16 04:03:41 +00:00
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#include "core/hle/service/gsp.h"
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2014-05-17 20:50:33 +00:00
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#include "core/hw/gpu.h"
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2014-04-26 05:48:24 +00:00
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2014-05-17 20:26:45 +00:00
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#include "video_core/gpu_debugger.h"
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2014-05-08 01:04:55 +00:00
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////////////////////////////////////////////////////////////////////////////////////////////////////
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2014-05-17 20:34:55 +00:00
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// Main graphics debugger object - TODO: Here is probably not the best place for this
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GraphicsDebugger g_debugger;
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2014-05-08 01:04:55 +00:00
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/// GSP shared memory GX command buffer header
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union GX_CmdBufferHeader {
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u32 hex;
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2014-05-17 20:26:45 +00:00
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// Current command index. This index is updated by GSP module after loading the command data,
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// right before the command is processed. When this index is updated by GSP module, the total
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2014-05-08 01:04:55 +00:00
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// commands field is decreased by one as well.
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BitField<0,8,u32> index;
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2014-05-17 20:26:45 +00:00
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2014-05-08 01:04:55 +00:00
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// Total commands to process, must not be value 0 when GSP module handles commands. This must be
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2014-05-17 20:26:45 +00:00
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// <=15 when writing a command to shared memory. This is incremented by the application when
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// writing a command to shared memory, after increasing this value TriggerCmdReqQueue is only
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2014-05-08 01:04:55 +00:00
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// used if this field is value 1.
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2014-05-19 02:09:08 +00:00
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BitField<8,8,u32> number_commands;
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2014-05-08 01:04:55 +00:00
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};
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2014-07-05 04:59:58 +00:00
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Namespace GSP_GPU
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namespace GSP_GPU {
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Handle g_event = 0;
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Handle g_shared_memory = 0;
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u32 g_thread_id = 0;
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2014-05-08 01:04:55 +00:00
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/// Gets a pointer to the start (header) of a command buffer in GSP shared memory
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static inline u8* GX_GetCmdBufferPointer(u32 thread_id, u32 offset=0) {
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2014-07-05 04:59:58 +00:00
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return Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * 0x200) + offset);
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2014-05-08 01:04:55 +00:00
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}
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/// Finishes execution of a GSP command
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void GX_FinishCommand(u32 thread_id) {
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GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(thread_id);
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2014-05-17 20:34:55 +00:00
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g_debugger.GXCommandProcessed(GX_GetCmdBufferPointer(thread_id, 0x20 + (header->index * 0x20)));
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2014-05-08 01:04:55 +00:00
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header->number_commands = header->number_commands - 1;
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2014-05-17 20:26:45 +00:00
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// TODO: Increment header->index?
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2014-05-08 01:04:55 +00:00
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}
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2014-06-01 11:58:14 +00:00
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/// Write a GSP GPU hardware register
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void WriteHWRegs(Service::Interface* self) {
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u32* cmd_buff = Service::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Write address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
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while (size > 0) {
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GPU::Write<u32>(reg_addr + 0x1EB00000, *src);
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size -= 4;
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++src;
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reg_addr += 4;
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}
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}
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2014-04-26 05:48:24 +00:00
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/// Read a GSP GPU hardware register
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void ReadHWRegs(Service::Interface* self) {
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2014-05-08 01:04:55 +00:00
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u32* cmd_buff = Service::GetCommandBuffer();
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2014-04-26 05:48:24 +00:00
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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2014-05-17 20:26:45 +00:00
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2014-06-01 11:58:14 +00:00
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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ERROR_LOG(GPU, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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2014-04-26 05:48:24 +00:00
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2014-06-01 11:58:14 +00:00
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// size should be word-aligned
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if ((size % 4) != 0) {
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ERROR_LOG(GPU, "Invalid size 0x%08x", size);
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return;
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}
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2014-04-27 16:41:25 +00:00
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2014-06-01 11:58:14 +00:00
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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2014-04-26 05:48:24 +00:00
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2014-06-01 11:58:14 +00:00
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while (size > 0) {
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GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
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2014-04-26 05:48:24 +00:00
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2014-06-01 11:58:14 +00:00
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size -= 4;
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++dst;
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reg_addr += 4;
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2014-04-26 05:48:24 +00:00
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}
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}
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2014-07-05 04:59:58 +00:00
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/**
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* GSP_GPU::RegisterInterruptRelayQueue service function
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* Inputs:
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* 1 : "Flags" field, purpose is unknown
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* 3 : Handle to GSP synchronization event
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* Outputs:
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* 0 : Result of function, 0 on success, otherwise error code
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* 2 : Thread index into GSP command buffer
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* 4 : Handle to GSP shared memory
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*/
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2014-04-25 02:20:13 +00:00
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void RegisterInterruptRelayQueue(Service::Interface* self) {
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2014-05-08 01:04:55 +00:00
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u32* cmd_buff = Service::GetCommandBuffer();
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2014-04-25 02:20:13 +00:00
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u32 flags = cmd_buff[1];
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2014-07-05 04:59:58 +00:00
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g_event = cmd_buff[3];
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2014-06-01 14:41:23 +00:00
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2014-07-05 04:59:58 +00:00
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_assert_msg_(GSP, (g_event != 0), "handle is not valid!");
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2014-06-01 14:41:23 +00:00
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2014-07-05 04:59:58 +00:00
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Kernel::SetEventLocked(g_event, false);
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2014-06-01 14:41:23 +00:00
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2014-07-16 09:24:09 +00:00
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// Hack - This function will permanently set the state of the GSP event such that GPU command
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// synchronization barriers always passthrough. Correct solution would be to set this after the
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2014-06-01 14:41:23 +00:00
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// GPU as processed all queued up commands, but due to the emulator being single-threaded they
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// will always be ready.
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2014-07-05 04:59:58 +00:00
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Kernel::SetPermanentLock(g_event, true);
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2014-05-17 20:26:45 +00:00
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2014-07-05 04:59:58 +00:00
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cmd_buff[0] = 0; // Result - no error
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cmd_buff[2] = g_thread_id; // ThreadID
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cmd_buff[4] = g_shared_memory; // GSP shared memory
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2014-05-08 01:04:55 +00:00
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}
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2014-05-17 20:26:45 +00:00
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2014-05-08 01:04:55 +00:00
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/// This triggers handling of the GX command written to the command buffer in shared memory.
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void TriggerCmdReqQueue(Service::Interface* self) {
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2014-07-16 09:24:09 +00:00
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// Utility function to convert register ID to address
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auto WriteGPURegister = [](u32 id, u32 data) {
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GPU::Write<u32>(0x1EF00000 + 4 * id, data);
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};
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2014-05-08 01:04:55 +00:00
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GX_CmdBufferHeader* header = (GX_CmdBufferHeader*)GX_GetCmdBufferPointer(g_thread_id);
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2014-07-22 10:41:16 +00:00
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auto& command = *(const GXCommand*)GX_GetCmdBufferPointer(g_thread_id, 0x20 + (header->index * 0x20));
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2014-04-25 02:20:13 +00:00
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2014-07-22 10:41:16 +00:00
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switch (command.id) {
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2014-05-08 01:04:55 +00:00
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// GX request DMA - typically used for copying memory from GSP heap to VRAM
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2014-05-17 20:26:45 +00:00
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case GXCommandId::REQUEST_DMA:
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2014-07-22 10:41:16 +00:00
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memcpy(Memory::GetPointer(command.dma_request.dest_address),
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Memory::GetPointer(command.dma_request.source_address),
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command.dma_request.size);
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2014-05-08 01:04:55 +00:00
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break;
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2014-07-22 11:04:16 +00:00
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// ctrulib homebrew sends all relevant command list data with this command,
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// hence we do all "interesting" stuff here and do nothing in SET_COMMAND_LIST_FIRST.
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// TODO: This will need some rework in the future.
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2014-05-17 20:26:45 +00:00
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case GXCommandId::SET_COMMAND_LIST_LAST:
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2014-07-22 10:41:16 +00:00
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{
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auto& params = command.set_command_list_last;
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WriteGPURegister(GPU::Regs::CommandProcessor + 2, params.address >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor, params.size >> 3);
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WriteGPURegister(GPU::Regs::CommandProcessor + 4, 1); // TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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2014-05-18 15:28:30 +00:00
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// TODO: Move this to GPU
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// TODO: Not sure what units the size is measured in
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2014-07-22 10:41:16 +00:00
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g_debugger.CommandListCalled(params.address,
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(u32*)Memory::GetPointer(params.address),
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params.size);
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2014-05-17 20:26:45 +00:00
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break;
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2014-07-22 10:41:16 +00:00
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}
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2014-05-17 20:26:45 +00:00
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2014-07-22 11:04:16 +00:00
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// It's assumed that the two "blocks" behave equivalently.
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// Presumably this is done simply to allow two memory fills to run in parallel.
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2014-05-17 20:26:45 +00:00
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case GXCommandId::SET_MEMORY_FILL:
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2014-07-22 10:41:16 +00:00
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{
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auto& params = command.memory_fill;
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WriteGPURegister(GPU::Regs::MemoryFill, params.start1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 1, params.end1 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 2, params.end1 - params.start1);
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WriteGPURegister(GPU::Regs::MemoryFill + 3, params.value1);
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WriteGPURegister(GPU::Regs::MemoryFill + 4, params.start2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 5, params.end2 >> 3);
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WriteGPURegister(GPU::Regs::MemoryFill + 6, params.end2 - params.start2);
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WriteGPURegister(GPU::Regs::MemoryFill + 7, params.value2);
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2014-05-17 20:26:45 +00:00
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break;
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2014-07-22 10:41:16 +00:00
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}
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2014-05-17 20:26:45 +00:00
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2014-05-31 22:22:40 +00:00
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// TODO: Check if texture copies are implemented correctly..
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2014-05-17 20:26:45 +00:00
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case GXCommandId::SET_DISPLAY_TRANSFER:
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case GXCommandId::SET_TEXTURE_COPY:
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2014-07-22 10:41:16 +00:00
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU::Regs::DisplayTransfer, params.in_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 1, params.out_buffer_address >> 3);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 3, params.in_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 2, params.out_buffer_size);
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WriteGPURegister(GPU::Regs::DisplayTransfer + 4, params.flags);
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2014-07-16 09:24:09 +00:00
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// TODO: Should this only be ORed with 1 for texture copies?
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2014-07-22 10:41:16 +00:00
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// trigger transfer
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WriteGPURegister(GPU::Regs::DisplayTransfer + 6, 1);
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2014-05-17 20:26:45 +00:00
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break;
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2014-07-22 10:41:16 +00:00
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}
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2014-05-17 20:26:45 +00:00
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2014-07-22 11:04:16 +00:00
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// TODO: Figure out what exactly SET_COMMAND_LIST_FIRST and SET_COMMAND_LIST_LAST
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// are supposed to do.
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2014-05-17 20:26:45 +00:00
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case GXCommandId::SET_COMMAND_LIST_FIRST:
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{
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break;
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}
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2014-05-08 01:04:55 +00:00
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default:
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2014-07-22 10:41:16 +00:00
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ERROR_LOG(GSP, "unknown command 0x%08X", (int)command.id.Value());
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2014-05-08 01:04:55 +00:00
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}
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2014-05-17 20:26:45 +00:00
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2014-05-08 01:04:55 +00:00
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GX_FinishCommand(g_thread_id);
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2014-04-25 02:20:13 +00:00
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}
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const Interface::FunctionInfo FunctionTable[] = {
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2014-06-01 11:58:14 +00:00
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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2014-06-06 04:35:49 +00:00
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{0x00020084, nullptr, "WriteHWRegsWithMask"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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2014-04-26 05:48:24 +00:00
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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2014-06-06 04:35:49 +00:00
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{0x00050200, nullptr, "SetBufferSwap"},
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{0x00060082, nullptr, "SetCommandList"},
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{0x000700C2, nullptr, "RequestDma"},
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{0x00080082, nullptr, "FlushDataCache"},
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{0x00090082, nullptr, "InvalidateDataCache"},
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{0x000A0044, nullptr, "RegisterInterruptEvents"},
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{0x000B0040, nullptr, "SetLcdForceBlack"},
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2014-05-08 01:04:55 +00:00
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{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
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2014-06-06 04:35:49 +00:00
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{0x000D0140, nullptr, "SetDisplayTransfer"},
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{0x000E0180, nullptr, "SetTextureCopy"},
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{0x000F0200, nullptr, "SetMemoryFill"},
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{0x00100040, nullptr, "SetAxiConfigQoSMode"},
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{0x00110040, nullptr, "SetPerfLogMode"},
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{0x00120000, nullptr, "GetPerfLog"},
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2014-04-25 02:20:13 +00:00
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{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
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2014-06-06 04:35:49 +00:00
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{0x00140000, nullptr, "UnregisterInterruptRelayQueue"},
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{0x00150002, nullptr, "TryAcquireRight"},
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{0x00160042, nullptr, "AcquireRight"},
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{0x00170000, nullptr, "ReleaseRight"},
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{0x00180000, nullptr, "ImportDisplayCaptureInfo"},
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{0x00190000, nullptr, "SaveVramSysArea"},
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{0x001A0000, nullptr, "RestoreVramSysArea"},
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{0x001B0000, nullptr, "ResetGpuCore"},
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{0x001C0040, nullptr, "SetLedForceOff"},
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{0x001D0040, nullptr, "SetTestCommand"},
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{0x001E0080, nullptr, "SetInternalPriorities"},
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2014-04-16 04:03:41 +00:00
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Interface class
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Interface::Interface() {
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Register(FunctionTable, ARRAY_SIZE(FunctionTable));
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2014-07-05 04:59:58 +00:00
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g_shared_memory = Kernel::CreateSharedMemory("GSPSharedMem");
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2014-04-16 04:03:41 +00:00
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}
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Interface::~Interface() {
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}
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} // namespace
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