2018-12-20 22:09:21 +00:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cmath>
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#include <unordered_map>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::IpaMode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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Node ShaderIR::StoreNode(NodeData&& node_data) {
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auto store = std::make_unique<NodeData>(node_data);
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const Node node = store.get();
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stored_nodes.push_back(std::move(store));
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return node;
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}
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Node ShaderIR::Conditional(Node condition, std::vector<Node>&& code) {
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return StoreNode(ConditionalNode(condition, std::move(code)));
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}
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Node ShaderIR::Comment(const std::string& text) {
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return StoreNode(CommentNode(text));
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}
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2018-12-21 01:36:17 +00:00
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Node ShaderIR::Immediate(u32 value) {
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return StoreNode(ImmediateNode(value));
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}
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2018-12-21 01:41:31 +00:00
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Node ShaderIR::GetRegister(Register reg) {
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if (reg != Register::ZeroIndex) {
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used_registers.insert(static_cast<u32>(reg));
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}
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return StoreNode(GprNode(reg));
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}
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2018-12-21 01:36:17 +00:00
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Node ShaderIR::GetImmediate19(Instruction instr) {
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return Immediate(instr.alu.GetImm20_19());
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}
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Node ShaderIR::GetImmediate32(Instruction instr) {
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return Immediate(instr.alu.GetImm20_32());
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}
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2018-12-21 01:42:47 +00:00
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Node ShaderIR::GetConstBuffer(u64 index_, u64 offset_) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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const auto [entry, is_new] = used_cbufs.try_emplace(index);
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entry->second.MarkAsUsed(offset);
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return StoreNode(CbufNode(index, Immediate(offset)));
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}
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Node ShaderIR::GetConstBufferIndirect(u64 index_, u64 offset_, Node node) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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const auto [entry, is_new] = used_cbufs.try_emplace(index);
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entry->second.MarkAsUsedIndirect();
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const Node final_offset = Operation(OperationCode::UAdd, NO_PRECISE, node, Immediate(offset));
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return StoreNode(CbufNode(index, final_offset));
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}
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2018-12-20 22:09:21 +00:00
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Node ShaderIR::GetPredicate(u64 pred_, bool negated) {
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const auto pred = static_cast<Pred>(pred_);
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if (pred != Pred::UnusedIndex && pred != Pred::NeverExecute) {
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used_predicates.insert(pred);
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}
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return StoreNode(PredicateNode(pred, negated));
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}
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2018-12-21 01:36:17 +00:00
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Node ShaderIR::GetPredicate(bool immediate) {
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return GetPredicate(static_cast<u64>(immediate ? Pred::UnusedIndex : Pred::NeverExecute));
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}
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2018-12-21 01:45:34 +00:00
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Node ShaderIR::GetInputAttribute(Attribute::Index index, u64 element,
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const Tegra::Shader::IpaMode& input_mode, Node buffer) {
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const auto [entry, is_new] =
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used_input_attributes.emplace(std::make_pair(index, std::set<Tegra::Shader::IpaMode>{}));
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entry->second.insert(input_mode);
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return StoreNode(AbufNode(index, static_cast<u32>(element), input_mode, buffer));
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}
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Node ShaderIR::GetOutputAttribute(Attribute::Index index, u64 element, Node buffer) {
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if (index == Attribute::Index::ClipDistances0123 ||
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index == Attribute::Index::ClipDistances4567) {
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const auto clip_index =
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static_cast<u32>((index == Attribute::Index::ClipDistances4567 ? 1 : 0) + element);
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used_clip_distances.at(clip_index) = true;
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}
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used_output_attributes.insert(index);
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return StoreNode(AbufNode(index, static_cast<u32>(element), buffer));
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}
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2018-12-21 01:49:59 +00:00
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Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) {
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const Node node = StoreNode(InternalFlagNode(flag));
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if (negated) {
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return Operation(OperationCode::LogicalNegate, node);
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}
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return node;
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}
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2018-12-21 01:51:38 +00:00
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Node ShaderIR::GetLocalMemory(Node address) {
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return StoreNode(LmemNode(address));
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}
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2018-12-20 22:09:21 +00:00
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/*static*/ OperationCode ShaderIR::SignedToUnsignedCode(OperationCode operation_code,
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bool is_signed) {
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if (is_signed) {
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return operation_code;
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}
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switch (operation_code) {
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case OperationCode::FCastInteger:
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return OperationCode::FCastUInteger;
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case OperationCode::IAdd:
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return OperationCode::UAdd;
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case OperationCode::IMul:
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return OperationCode::UMul;
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case OperationCode::IDiv:
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return OperationCode::UDiv;
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case OperationCode::IMin:
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return OperationCode::UMin;
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case OperationCode::IMax:
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return OperationCode::UMax;
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case OperationCode::ICastFloat:
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return OperationCode::UCastFloat;
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case OperationCode::ICastUnsigned:
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return OperationCode::UCastSigned;
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case OperationCode::ILogicalShiftLeft:
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return OperationCode::ULogicalShiftLeft;
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case OperationCode::ILogicalShiftRight:
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return OperationCode::ULogicalShiftRight;
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case OperationCode::IArithmeticShiftRight:
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return OperationCode::UArithmeticShiftRight;
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case OperationCode::IBitwiseAnd:
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return OperationCode::UBitwiseAnd;
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case OperationCode::IBitwiseOr:
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return OperationCode::UBitwiseOr;
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case OperationCode::IBitwiseXor:
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return OperationCode::UBitwiseXor;
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case OperationCode::IBitwiseNot:
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return OperationCode::UBitwiseNot;
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case OperationCode::IBitfieldInsert:
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return OperationCode::UBitfieldInsert;
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case OperationCode::LogicalILessThan:
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return OperationCode::LogicalULessThan;
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case OperationCode::LogicalIEqual:
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return OperationCode::LogicalUEqual;
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case OperationCode::LogicalILessEqual:
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return OperationCode::LogicalULessEqual;
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case OperationCode::LogicalIGreaterThan:
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return OperationCode::LogicalUGreaterThan;
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case OperationCode::LogicalINotEqual:
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return OperationCode::LogicalUNotEqual;
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case OperationCode::LogicalIGreaterEqual:
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return OperationCode::LogicalUGreaterEqual;
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case OperationCode::INegate:
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UNREACHABLE_MSG("Can't negate an unsigned integer");
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case OperationCode::IAbsolute:
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UNREACHABLE_MSG("Can't apply absolute to an unsigned integer");
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}
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UNREACHABLE_MSG("Unknown signed operation with code={}", static_cast<u32>(operation_code));
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}
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} // namespace VideoCommon::Shader
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