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correct some npth clearances for aisler

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This commit is contained in:
jacqueline 2023-11-25 10:08:52 +11:00
parent baa4c6dee3
commit ab06d00697
6 changed files with 4943 additions and 4826 deletions
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16
tangara-mainboard/footprints.pretty/CUI_SJ-3506-SMT.kicad_mod
View file

@ -99,20 +99,20 @@
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp 7741783f-2a61-4ed0-bf5d-129ea169d122))
(fp_line (start 6.8 3) (end 6.1 3)
(stroke (width 0.127) (type solid)) (layer "F.Fab") (tstamp e5334282-c192-44e0-bff1-11192f55afa3))
(pad "1" thru_hole oval (at -4.25 -5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "1" thru_hole oval (at -4.25 -5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp ec4d5fc7-f710-44d9-8264-01ebba60ad03))
(pad "2" thru_hole oval (at 3.6 -5.9) (size 1.8 1.1) (drill oval 1.2 0.7 (offset -0.15 0)) (layers "*.Cu" "*.Mask")
(pad "2" thru_hole oval (at 3.6 -5.9) (size 1.8 1) (drill oval 1.2 0.7 (offset -0.15 0)) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 888868bf-423c-4cce-8dff-06a7e5ec73b1))
(pad "3" thru_hole oval (at 5.4 5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "3" thru_hole oval (at 5.4 5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 04467c23-d785-4b48-a8df-8c7a45dc233c))
(pad "4" thru_hole oval (at 2.9 5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "4" thru_hole oval (at 2.9 5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 5bfa7040-f089-470c-adc2-706697312dcb))
(pad "5" thru_hole oval (at -4.25 5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "5" thru_hole oval (at -4.25 5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 16648ace-324b-438c-8ba2-117831fbf9e9))
(pad "6" thru_hole oval (at 5.4 -5.9) (size 1.8 1.1) (drill oval 1.2 0.7 (offset 0.15 0)) (layers "*.Cu" "*.Mask")
(pad "6" thru_hole oval (at 5.4 -5.9) (size 1.8 1) (drill oval 1.2 0.7 (offset 0.15 0)) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 5753d919-209f-4364-bf56-c4cb571eaa4b))
(pad "SH1" thru_hole oval (at -0.22 -5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "SH1" thru_hole oval (at -0.22 -5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 568c529d-6e46-4625-b95c-a4230f92006c))
(pad "SH2" thru_hole oval (at -0.22 5.9) (size 1.6 1.1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(pad "SH2" thru_hole oval (at -0.22 5.9) (size 1.6 1) (drill oval 1.2 0.7) (layers "*.Cu" "*.Mask")
(solder_mask_margin 0.102) (tstamp 1bd5e7c4-db32-4875-945e-b5af71e0c640))
)

2
tangara-mainboard/fp-info-cache
View file

@ -1,4 +1,4 @@
21503252916720416
21503335621991416
Audio_Module
Reverb_BTDR-1H
Digital Reverberation Unit, http://www.belton.co.kr/inc/downfile.php?seq=17&file=pdf (footprint from http://www.uk-electronic.de/PDF/BTDR-1.pdf)

9742
tangara-mainboard/tangara-mainboard.kicad_pcb
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File diff suppressed because it is too large Load diff

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tangara-mainboard/tangara-mainboard.kicad_pcb.zip
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7
tangara-mainboard/tangara-mainboard.kicad_prl
View file

@ -1,7 +1,7 @@
{
"board": {
"active_layer": 36,
"active_layer_preset": "",
"active_layer": 37,
"active_layer_preset": "Front Assembly View",
"auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [],
@ -38,6 +38,7 @@
8,
9,
10,
12,
13,
15,
16,
@ -63,7 +64,7 @@
39,
40
],
"visible_layers": "00290ba_80000007",
"visible_layers": "00290a0_00000000",
"zone_display_mode": 0
},
"meta": {

2
tangara-mainboard/tangara-mainboard.kicad_pro
View file

@ -122,7 +122,7 @@
"min_clearance": 0.15,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.3,
"min_hole_clearance": 0.125,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,