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changes for producing mainboard at jlc

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Artemis Tosini 2024-02-04 04:50:53 +00:00
parent 8644baa487
commit 5dd8a5f802
Signed by: artemist
GPG key ID: EE5227935FE3FF18
5 changed files with 5582 additions and 3999 deletions
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468
tangara-mainboard/footprints.pretty/bottom.kicad_mod Normal file
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8546
tangara-mainboard/tangara-mainboard.kicad_pcb
View file

File diff suppressed because it is too large Load diff

10
tangara-mainboard/tangara-mainboard.kicad_prl
View file

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39,
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"filename": "tangara-mainboard.kicad_prl",

22
tangara-mainboard/tangara-mainboard.kicad_pro
View file

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"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.15,
"min_via_annular_width": 0.19999999999999998,
"min_via_diameter": 0.39999999999999997,
"min_through_hole_diameter": 0.15,
"min_track_width": 0.09,
"min_via_annular_width": 0.13,
"min_via_diameter": 0.15,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.005,
@ -201,7 +203,7 @@
"drill": 0.281
}
],
"zones_allow_external_fillets": false,
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": [],