497 lines
24 KiB
C
497 lines
24 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3S1B_
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#define _SAM3S1B_
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/** \addtogroup SAM3S1B_definitions SAM3S1B definitions
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This file defines all structures and symbols for SAM3S1B:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- PIO definitions
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*/
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/*@{*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#include <stdint.h>
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#endif
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/* ************************************************************************** */
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/* CMSIS DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_cmsis CMSIS Definitions */
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/*@{*/
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/**< Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ******************************/
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NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
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/****** SAM3S1B specific Interrupt Numbers *********************************/
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SUPC_IRQn = 0, /**< 0 SAM3S1B Supply Controller (SUPC) */
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RSTC_IRQn = 1, /**< 1 SAM3S1B Reset Controller (RSTC) */
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RTC_IRQn = 2, /**< 2 SAM3S1B Real Time Clock (RTC) */
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RTT_IRQn = 3, /**< 3 SAM3S1B Real Time Timer (RTT) */
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WDT_IRQn = 4, /**< 4 SAM3S1B Watchdog Timer (WDT) */
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PMC_IRQn = 5, /**< 5 SAM3S1B Power Management Controller (PMC) */
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EFC_IRQn = 6, /**< 6 SAM3S1B Enhanced Embedded Flash Controller (EFC) */
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UART0_IRQn = 8, /**< 8 SAM3S1B UART 0 (UART0) */
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UART1_IRQn = 9, /**< 9 SAM3S1B UART 1 (UART1) */
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PIOA_IRQn = 11, /**< 11 SAM3S1B Parallel I/O Controller A (PIOA) */
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PIOB_IRQn = 12, /**< 12 SAM3S1B Parallel I/O Controller B (PIOB) */
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USART0_IRQn = 14, /**< 14 SAM3S1B USART 0 (USART0) */
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USART1_IRQn = 15, /**< 15 SAM3S1B USART 1 (USART1) */
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HSMCI_IRQn = 18, /**< 18 SAM3S1B Multimedia Card Interface (HSMCI) */
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TWI0_IRQn = 19, /**< 19 SAM3S1B Two Wire Interface 0 (TWI0) */
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TWI1_IRQn = 20, /**< 20 SAM3S1B Two Wire Interface 1 (TWI1) */
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SPI_IRQn = 21, /**< 21 SAM3S1B Serial Peripheral Interface (SPI) */
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SSC_IRQn = 22, /**< 22 SAM3S1B Synchronous Serial Controler (SSC) */
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TC0_IRQn = 23, /**< 23 SAM3S1B Timer/Counter 0 (TC0) */
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TC1_IRQn = 24, /**< 24 SAM3S1B Timer/Counter 1 (TC1) */
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TC2_IRQn = 25, /**< 25 SAM3S1B Timer/Counter 2 (TC2) */
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ADC_IRQn = 29, /**< 29 SAM3S1B Analog To Digital Converter (ADC) */
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DACC_IRQn = 30, /**< 30 SAM3S1B Digital To Analog Converter (DACC) */
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PWM_IRQn = 31, /**< 31 SAM3S1B Pulse Width Modulation (PWM) */
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CRCCU_IRQn = 32, /**< 32 SAM3S1B CRC Calculation Unit (CRCCU) */
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ACC_IRQn = 33, /**< 33 SAM3S1B Analog Comparator (ACC) */
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UDP_IRQn = 34, /**< 34 SAM3S1B USB Device Port (UDP) */
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PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */
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} IRQn_Type;
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* Cortex-M handlers */
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void* pfnReset_Handler;
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void* pfnNMI_Handler;
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void* pfnHardFault_Handler;
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void* pfnMemManage_Handler;
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void* pfnBusFault_Handler;
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void* pfnUsageFault_Handler;
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void* pfnReserved1_Handler;
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void* pfnReserved2_Handler;
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void* pfnReserved3_Handler;
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void* pfnReserved4_Handler;
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void* pfnSVC_Handler;
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void* pfnDebugMon_Handler;
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void* pfnReserved5_Handler;
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void* pfnPendSV_Handler;
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void* pfnSysTick_Handler;
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/* Peripheral handlers */
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void* pfnSUPC_Handler; /* 0 Supply Controller */
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void* pfnRSTC_Handler; /* 1 Reset Controller */
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void* pfnRTC_Handler; /* 2 Real Time Clock */
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void* pfnRTT_Handler; /* 3 Real Time Timer */
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void* pfnWDT_Handler; /* 4 Watchdog Timer */
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void* pfnPMC_Handler; /* 5 Power Management Controller */
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void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
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void* pvReserved7;
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void* pfnUART0_Handler; /* 8 UART 0 */
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void* pfnUART1_Handler; /* 9 UART 1 */
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void* pvReserved10;
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void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */
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void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */
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void* pvReserved13;
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void* pfnUSART0_Handler; /* 14 USART 0 */
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void* pfnUSART1_Handler; /* 15 USART 1 */
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void* pvReserved16;
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void* pvReserved17;
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void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
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void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */
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void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */
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void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */
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void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */
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void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
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void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
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void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
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void* pvReserved26;
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void* pvReserved27;
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void* pvReserved28;
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void* pfnADC_Handler; /* 29 Analog To Digital Converter */
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void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
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void* pfnPWM_Handler; /* 31 Pulse Width Modulation */
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void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */
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void* pfnACC_Handler; /* 33 Analog Comparator */
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void* pfnUDP_Handler; /* 34 USB Device Port */
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} DeviceVectors;
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/* Cortex-M3 core handlers */
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void Reset_Handler ( void );
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void NMI_Handler ( void );
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void HardFault_Handler ( void );
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void MemManage_Handler ( void );
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void BusFault_Handler ( void );
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void UsageFault_Handler ( void );
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void SVC_Handler ( void );
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void DebugMon_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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/* Peripherals handlers */
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void ACC_Handler ( void );
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void ADC_Handler ( void );
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void CRCCU_Handler ( void );
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void DACC_Handler ( void );
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void EFC_Handler ( void );
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void HSMCI_Handler ( void );
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void PIOA_Handler ( void );
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void PIOB_Handler ( void );
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void PMC_Handler ( void );
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void PWM_Handler ( void );
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void RSTC_Handler ( void );
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void RTC_Handler ( void );
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void RTT_Handler ( void );
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void SPI_Handler ( void );
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void SSC_Handler ( void );
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void SUPC_Handler ( void );
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void TC0_Handler ( void );
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void TC1_Handler ( void );
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void TC2_Handler ( void );
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void TWI0_Handler ( void );
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void TWI1_Handler ( void );
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void UART0_Handler ( void );
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void UART1_Handler ( void );
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void UDP_Handler ( void );
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void USART0_Handler ( void );
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void USART1_Handler ( void );
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void WDT_Handler ( void );
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/**
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* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __CM3_REV 0x0200 /**< SAM3S1B core revision number ([15:8] revision number, [7:0] patch number) */
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#define __MPU_PRESENT 1 /**< SAM3S1B does provide a MPU */
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#define __NVIC_PRIO_BITS 4 /**< SAM3S1B uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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/*
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* \brief CMSIS includes
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*/
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#include <core_cm3.h>
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#if !defined DONT_USE_CMSIS_INIT
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#include "system_sam3s.h"
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#endif /* DONT_USE_CMSIS_INIT */
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/*@}*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_api Peripheral Software API */
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/*@{*/
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#include "component/acc.h"
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#include "component/adc.h"
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#include "component/chipid.h"
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#include "component/crccu.h"
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#include "component/dacc.h"
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#include "component/efc.h"
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#include "component/gpbr.h"
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#include "component/hsmci.h"
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#include "component/matrix.h"
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#include "component/pdc.h"
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#include "component/pio.h"
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#include "component/pmc.h"
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#include "component/pwm.h"
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#include "component/rstc.h"
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#include "component/rtc.h"
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#include "component/rtt.h"
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#include "component/spi.h"
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#include "component/ssc.h"
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#include "component/supc.h"
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#include "component/tc.h"
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#include "component/twi.h"
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#include "component/uart.h"
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#include "component/udp.h"
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#include "component/usart.h"
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#include "component/wdt.h"
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/*@}*/
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/* ************************************************************************** */
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/* REGISTER ACCESS DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_reg Registers Access Definitions */
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/*@{*/
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#include "instance/hsmci.h"
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#include "instance/ssc.h"
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#include "instance/spi.h"
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#include "instance/tc0.h"
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#include "instance/twi0.h"
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#include "instance/twi1.h"
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#include "instance/pwm.h"
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#include "instance/usart0.h"
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#include "instance/usart1.h"
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#include "instance/udp.h"
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#include "instance/adc.h"
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#include "instance/dacc.h"
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#include "instance/acc.h"
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#include "instance/crccu.h"
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#include "instance/matrix.h"
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#include "instance/pmc.h"
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#include "instance/uart0.h"
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#include "instance/chipid.h"
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#include "instance/uart1.h"
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#include "instance/efc.h"
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#include "instance/pioa.h"
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#include "instance/piob.h"
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#include "instance/rstc.h"
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#include "instance/supc.h"
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#include "instance/rtt.h"
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#include "instance/wdt.h"
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#include "instance/rtc.h"
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#include "instance/gpbr.h"
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/*@}*/
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/* ************************************************************************** */
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/* PERIPHERAL ID DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_id Peripheral Ids Definitions */
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/*@{*/
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#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
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#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
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#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
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#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
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#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
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#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
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#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
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#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
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#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
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#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
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#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
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#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
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#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
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#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
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#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */
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#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
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#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
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#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
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#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
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#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
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#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
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#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */
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#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
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#define ID_UDP (34) /**< \brief USB Device Port (UDP) */
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#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */
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/*@}*/
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/* ************************************************************************** */
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/* BASE ADDRESS DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_base Peripheral Base Address Definitions */
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/*@{*/
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
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#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
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#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
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#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */
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#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */
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#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */
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#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */
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#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */
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#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
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#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */
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#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
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#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */
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#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */
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#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */
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#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */
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#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */
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#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */
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#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */
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#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */
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#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */
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#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */
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#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
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#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */
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#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */
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#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */
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#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */
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#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */
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#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
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#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */
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#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */
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#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
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#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */
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#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
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#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */
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#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
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#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */
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#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */
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#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */
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#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */
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#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */
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#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */
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#else
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#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
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#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */
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#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
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#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */
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#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */
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#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */
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#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */
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#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */
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#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
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#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */
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#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */
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#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */
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#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */
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#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */
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#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */
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#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */
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#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */
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#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */
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#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */
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#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */
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#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */
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#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
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#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */
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#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */
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#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */
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#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */
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#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */
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#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
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#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */
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#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */
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#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */
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#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */
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#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
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#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */
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#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
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#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */
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#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */
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#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */
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#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */
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#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */
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#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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/* ************************************************************************** */
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/* PIO DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/** \addtogroup SAM3S1B_pio Peripheral Pio Definitions */
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/*@{*/
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#include "pio/sam3s1b.h"
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/*@}*/
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/* ************************************************************************** */
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/* MEMORY MAPPING DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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#define IFLASH_SIZE (0x10000u)
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#define IFLASH_PAGE_SIZE (256u)
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#define IFLASH_LOCK_REGION_SIZE (16384u)
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#define IFLASH_NB_OF_PAGES (256u)
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#define IFLASH_NB_OF_LOCK_BITS (4u)
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#define IRAM_SIZE (0x4000u)
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#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
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#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
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#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
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#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
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#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
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#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
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#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
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/* ************************************************************************** */
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/* MISCELLANEOUS DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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#define CHIP_JTAGID (0x05B2D03FUL)
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#define CHIP_CIDR (0x28990561UL)
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#define CHIP_EXID (0x0UL)
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#define NB_CH_ADC (10UL)
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#define NB_CH_DAC (2UL)
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/* ************************************************************************** */
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/* ELECTRICAL DEFINITIONS FOR SAM3S1B */
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/* ************************************************************************** */
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/* Device characteristics */
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#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
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#define CHIP_FREQ_SLCK_RC (32000UL)
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#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
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#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
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#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
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#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
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#define CHIP_FREQ_CPU_MAX (64000000UL)
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#define CHIP_FREQ_XTAL_32K (32768UL)
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#define CHIP_FREQ_XTAL_12M (12000000UL)
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/* Embedded Flash Write Wait State */
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#define CHIP_FLASH_WRITE_WAIT_STATE (4U)
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/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */
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#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
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#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
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#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
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#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
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/* HYSTeresis levels: please refer to Electrical Characteristics */
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#define ACC_ACR_HYST_50MV_MAX (0x01UL)
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#define ACC_ACR_HYST_90MV_MAX (0x11UL)
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#ifdef __cplusplus
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}
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#endif
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/*@}*/
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#endif /* _SAM3S1B_ */
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