14899 lines
524 KiB
XML
14899 lines
524 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
|
|
|
|
|
|
<!--
|
|
Software that is described herein is for illustrative purposes only
|
|
which provides customers with programming information regarding the
|
|
products. This software is supplied "AS IS" without any warranties.
|
|
NXP Semiconductors assumes no responsibility or liability for the
|
|
use of the software, conveys no license or title under any patent,
|
|
copyright, or mask work right to the product. NXP Semiconductors
|
|
reserves the right to make changes in the software without
|
|
notification. NXP Semiconductors also make no representation or
|
|
warranty that such application will be suitable for the specified
|
|
use without further testing or modification.
|
|
|
|
-->
|
|
<!-- v.8 updates
|
|
- CCAN removed - will be described in separate svd file
|
|
- readAction tag included in uart rbr, thr, lsr, msr and ssp dr registers -->
|
|
|
|
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" >
|
|
<name>LPC111x</name>
|
|
<version>8</version>
|
|
<description>LPC11xx, LPC11xxL, LPC11xxXL</description>
|
|
<!-- Bus Interface Properties -->
|
|
<!-- Cortex-M0 is byte addressable -->
|
|
<cpu>
|
|
<name>CM0</name>
|
|
<revision>r0p0</revision>
|
|
<endian>little</endian>
|
|
<mpuPresent>0</mpuPresent>
|
|
<fpuPresent>0</fpuPresent>
|
|
<nvicPrioBits>2</nvicPrioBits>
|
|
<vendorSystickConfig>0</vendorSystickConfig>
|
|
</cpu>
|
|
<addressUnitBits>8</addressUnitBits>
|
|
<width>32</width>
|
|
<size>32</size>
|
|
|
|
<peripherals>
|
|
<peripheral>
|
|
<name>I2C</name>
|
|
<description>I2C-bus interface</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CONSET</name>
|
|
<description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AA</name>
|
|
<description>Assert acknowledge flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SI</name>
|
|
<description>I2C interrupt flag.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STO</name>
|
|
<description>STOP flag.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STA</name>
|
|
<description>START flag.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2EN</name>
|
|
<description>I2C interface enable.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xF8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits are unused and are always 0.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Status</name>
|
|
<description>These bits give the actual status information about the I 2C interface.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAT</name>
|
|
<description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds data values that have been received or are to be transmitted.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADR0</name>
|
|
<description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLH</name>
|
|
<description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLH</name>
|
|
<description>Count for SCL HIGH time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCLL</name>
|
|
<description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x04</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>Count for SCL low time period selection.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONCLR</name>
|
|
<description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>AAC</name>
|
|
<description>Assert acknowledge Clear bit.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIC</name>
|
|
<description>I2C interrupt Clear bit.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>STAC</name>
|
|
<description>START flag Clear bit.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2ENC</name>
|
|
<description>I2C interface Disable bit.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMCTRL</name>
|
|
<description>Monitor mode control register.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MM_ENA</name>
|
|
<description>Monitor mode enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MONITOR_MODE_DISABLE</name>
|
|
<description>Monitor mode disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>THE_I2C_MODULE_WILL_</name>
|
|
<description>The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENA_SCL</name>
|
|
<description>SCL output enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCH_ALL</name>
|
|
<description>Select interrupt register match.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MATCH</name>
|
|
<description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ANYADDRESS</name>
|
|
<description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from reserved bits is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1-3</dimIndex>
|
|
<name>ADR%s</name>
|
|
<description>I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GC</name>
|
|
<description>General Call enable bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>Address</name>
|
|
<description>The I2C device address for slave mode.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA_BUFFER</name>
|
|
<description>Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Data</name>
|
|
<description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000).</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask bits.</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. The value read from reserved bits is undefined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>WWDT</name>
|
|
<description>Windowed WatchDog Timer (WDT)</description>
|
|
<groupName>WWDT</groupName>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDT</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WDMOD</name>
|
|
<description>Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WDEN</name>
|
|
<description>Watchdog enable bit. This bit is Set Only. Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to the watchdog oscillator before setting this bit to one.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOPPED</name>
|
|
<description>The watchdog timer is stopped.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RUN</name>
|
|
<description>The watchdog timer is running.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDRESET</name>
|
|
<description>Watchdog reset enable bit. This bit is Set Only.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NORESET</name>
|
|
<description>A watchdog timeout will not cause a chip reset.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET</name>
|
|
<description>A watchdog timeout will cause a chip reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOF</name>
|
|
<description>Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDINT</name>
|
|
<description>Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDPROTECT</name>
|
|
<description>Watchdog update mode. This bit is Set Only.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANYTIME</name>
|
|
<description>The watchdog reload value (WDTC) can be changed at any time.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOWCOUNTER</name>
|
|
<description>The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTC</name>
|
|
<description>Watchdog timer constant register. This register determines the time-out value.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Count</name>
|
|
<description>Watchdog time-out interval.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDFEED</name>
|
|
<description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Feed</name>
|
|
<description>Feed value should be 0xAA followed by 0x55.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTV</name>
|
|
<description>Watchdog timer value register. This register reads out the current value of the Watchdog timer.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>Count</name>
|
|
<description>Counter timer value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDWARNINT</name>
|
|
<description>Watchdog Warning Interrupt compare value.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WARNINT</name>
|
|
<description>Watchdog warning interrupt compare value.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDWINDOW</name>
|
|
<description>Watchdog Window compare value.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINDOW</name>
|
|
<description>Watchdog window value.</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Read value is undefined, only zero should be written.</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART</name>
|
|
<description>UART</description>
|
|
<groupName>UART</groupName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RBR</name>
|
|
<description>Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RBR</name>
|
|
<description>The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>THR</name>
|
|
<description>Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>THR</name>
|
|
<description>Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLL</name>
|
|
<description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
|
|
<alternateRegister>RBR</alternateRegister>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLLSB</name>
|
|
<description>The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLM</name>
|
|
<description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLMSB</name>
|
|
<description>The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. (DLAB=0)</description>
|
|
<alternateRegister>DLM</alternateRegister>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RBRIE</name>
|
|
<description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RDA_INTE</name>
|
|
<description>Disable the RDA interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RDA_INTER</name>
|
|
<description>Enable the RDA interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THREIE</name>
|
|
<description>THRE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5].</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_THRE_INT</name>
|
|
<description>Disable the THRE interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_THRE_INTE</name>
|
|
<description>Enable the THRE interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXLIE</name>
|
|
<description>RX Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1].</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_THE_RX_LINE_</name>
|
|
<description>Disable the RX line status interrupts.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_THE_RX_LINE_S</name>
|
|
<description>Enable the RX line status interrupts.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTEN</name>
|
|
<description>Enables the end of auto-baud interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_END_OF_AUTO_</name>
|
|
<description>Disable end of auto-baud Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_END_OF_AUTO_B</name>
|
|
<description>Enable end of auto-baud Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTEN</name>
|
|
<description>Enables the auto-baud time-out interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_BAUD_TI</name>
|
|
<description>Disable auto-baud time-out Interrupt.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_BAUD_TIM</name>
|
|
<description>Enable auto-baud time-out Interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IIR</name>
|
|
<description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
|
|
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x01</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INTSTATUS</name>
|
|
<description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PENDING</name>
|
|
<description>At least one interrupt is pending.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NO_INTERRUPT_IS_PEND</name>
|
|
<description>No interrupt is pending.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).</description>
|
|
<bitRange>[3:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_RECEIVE_LINE_S</name>
|
|
<description>1 - Receive Line Status (RLS).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2A__RECEIVE_DATA_AV</name>
|
|
<description>2a - Receive Data Available (RDA).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2B__CHARACTER_TIME_</name>
|
|
<description>2b - Character Time-out Indicator (CTI).</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_THRE_INTERRUPT</name>
|
|
<description>3 - THRE Interrupt.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_MODEM_INTERRUP</name>
|
|
<description>4 - Modem interrupt.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FIFOENABLE</name>
|
|
<description>These bits are equivalent to FCR[0].</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINT</name>
|
|
<description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABTOINT</name>
|
|
<description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register. Controls UART FIFO usage and modes.</description>
|
|
<alternateRegister>IIR</alternateRegister>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFO Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>UART FIFOs are disabled. Must not be used in the application.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFORES</name>
|
|
<description>RX FIFO Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFORES</name>
|
|
<description>TX FIFO Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_IMPACT_ON_EITHER_</name>
|
|
<description>No impact on either of UART FIFOs.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RXTL</name>
|
|
<description>RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_0_1_C</name>
|
|
<description>Trigger level 0 (1 character or 0x01).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_1_4_C</name>
|
|
<description>Trigger level 1 (4 characters or 0x04).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_2_8_C</name>
|
|
<description>Trigger level 2 (8 characters or 0x08).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TRIGGER_LEVEL_3_14_</name>
|
|
<description>Trigger level 3 (14 characters or 0x0E).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCR</name>
|
|
<description>Line Control Register. Contains controls for frame formatting and break generation.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WLS</name>
|
|
<description>Word Length Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>5_BIT_CHARACTER_LENG</name>
|
|
<description>5-bit character length.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_CHARACTER_LENG</name>
|
|
<description>6-bit character length.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_CHARACTER_LENG</name>
|
|
<description>7-bit character length.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_CHARACTER_LENG</name>
|
|
<description>8-bit character length.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBS</name>
|
|
<description>Stop Bit Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_STOP_BIT_</name>
|
|
<description>1 stop bit.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_STOP_BITS</name>
|
|
<description>2 stop bits (1.5 if LCR[1:0]=00).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_PARITY_GENER</name>
|
|
<description>Disable parity generation and checking.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_PARITY_GENERA</name>
|
|
<description>Enable parity generation and checking.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ODD_PARITY_NUMBER_O</name>
|
|
<description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EVEN_PARITY_NUMBER_</name>
|
|
<description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_1_STICK_PARIT</name>
|
|
<description>Forced 1 stick parity.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FORCED_0_STICK_PARIT</name>
|
|
<description>Forced 0 stick parity.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BC</name>
|
|
<description>Break Control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_BREAK_TRANSM</name>
|
|
<description>Disable break transmission.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_BREAK_TRANSMI</name>
|
|
<description>Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DLAB</name>
|
|
<description>Divisor Latch Access Bit</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_ACCESS_TO_DI</name>
|
|
<description>Disable access to Divisor Latches.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_ACCESS_TO_DIV</name>
|
|
<description>Enable access to Divisor Latches.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Modem control register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTRC</name>
|
|
<description>DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSC</name>
|
|
<description>RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>LMS</name>
|
|
<description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS flow control</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_RTS_FLO</name>
|
|
<description>Disable auto-rts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_RTS_FLOW</name>
|
|
<description>Enable auto-rts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS flow control</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_CTS_FLO</name>
|
|
<description>Disable auto-cts flow control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_CTS_FLOW</name>
|
|
<description>Enable auto-cts flow control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LSR</name>
|
|
<description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x60</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>EMPTY_</name>
|
|
<description>RBR is empty.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>RBR contains valid data.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OE</name>
|
|
<description>Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Overrun error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Overrun error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Parity error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Parity error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Framing error status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Framing error status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BI</name>
|
|
<description>Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE</name>
|
|
<description>Break interrupt status is inactive.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ACTIVE</name>
|
|
<description>Break interrupt status is active.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>THRE</name>
|
|
<description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>THR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY_</name>
|
|
<description>THR is empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEMT</name>
|
|
<description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>VALID</name>
|
|
<description>THR and/or the TSR contains valid data.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EMPTY_</name>
|
|
<description>THR and the TSR are empty.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOERROR</name>
|
|
<description>RBR contains no UART RX errors or FCR[0]=0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ERROR</name>
|
|
<description>UART RBR contains at least one UART RX error.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Modem status register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DCTS</name>
|
|
<description>Delta CTS. Set upon state change of input CTS. Cleared on a MSR read.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input CTS.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input CTS.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDSR</name>
|
|
<description>Delta DSR. Set upon state change of input DSR. Cleared on a MSR read.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input DSR.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input DSR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TERI</name>
|
|
<description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input, RI.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOW_TO_HIGH_TRANSITI</name>
|
|
<description>Low-to-high transition detected on RI.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DDCD</name>
|
|
<description>Delta DCD. Set upon state change of input DCD. Cleared on a MSR read.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE_DETECTED_O</name>
|
|
<description>No change detected on modem input DCD.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STATE_CHANGE_DETECTE</name>
|
|
<description>State change detected on modem input DCD.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DSR</name>
|
|
<description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RI</name>
|
|
<description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DCD</name>
|
|
<description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Scratch Pad Register. Eight-bit temporary storage for software.</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>pad</name>
|
|
<description>A readable, writable byte.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>Auto-baud stop (auto-baud is not running).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Auto-baud mode select</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MODE_0_</name>
|
|
<description>Mode 0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MODE_1_</name>
|
|
<description>Mode 1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTORESTART</name>
|
|
<description>Restart enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESTART</name>
|
|
<description>No restart</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESTART_IN_CASE_OF_T</name>
|
|
<description>Restart in case of time-out (counter restarts at next UART Rx falling edge)</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[7:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ABEOINTCLR</name>
|
|
<description>End of auto-baud interrupt clear (write only accessible)</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOIMPACT</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ABTOINTCLR</name>
|
|
<description>Auto-baud time-out interrupt clear (write only accessible)</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOIMPACT</name>
|
|
<description>Writing a 0 has no impact.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR</name>
|
|
<description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDR</name>
|
|
<description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVADDVAL</name>
|
|
<description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MULVAL</name>
|
|
<description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TER</name>
|
|
<description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXEN</name>
|
|
<description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485CTRL</name>
|
|
<description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NMMEN</name>
|
|
<description>NMM enable.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXDIS</name>
|
|
<description>Receiver enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>The receiver is enabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>The receiver is disabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AADEN</name>
|
|
<description>AAD enable.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Auto Address Detect (AAD) is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Auto Address Detect (AAD) is enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Select direction control pin</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RTS</name>
|
|
<description>If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DTR</name>
|
|
<description>If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DCTRL</name>
|
|
<description>Auto direction control enable.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_AUTO_DIRECTI</name>
|
|
<description>Disable Auto Direction Control.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_AUTO_DIRECTIO</name>
|
|
<description>Enable Auto Direction Control.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OINV</name>
|
|
<description>Polarity control. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485ADRMATCH</name>
|
|
<description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRMATCH</name>
|
|
<description>Contains the address match value.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RS485DLY</name>
|
|
<description>RS-485/EIA-485 direction control delay.</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>CT16B0</name>
|
|
<description>16-bit counter/timer CT16B0/1 </description>
|
|
<groupName>CT16B0</groupName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT16B0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter Enable. When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>Counter Reset. When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Prescale max value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register. MR can be enabled through the
|
|
MCR to reset the TC, stop both the TC and PC, and/or generate an
|
|
interrupt every time MR matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event will generate an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>CR%s</name>
|
|
<description>Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC).</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000.</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_CAP0</name>
|
|
<description>CT16Bn_CAP0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT16BN_CAP1</name>
|
|
<description>CT16Bn_CAP1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SELCC</name>
|
|
<description>When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CAP0_</name>
|
|
<description>Rising Edge of CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CAP0</name>
|
|
<description>Falling Edge of CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CAP1_</name>
|
|
<description>Rising Edge of CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CAP1</name>
|
|
<description>Falling Edge of CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM channel0 enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT0_IS_CONTR</name>
|
|
<description>CT16Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM channel1 enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT16BN_MAT1_IS_CONTR</name>
|
|
<description>CT16Bn_MAT1 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT16Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM channel2 enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MATCH_CHANNEL_2_OR_P</name>
|
|
<description>Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for match channel 2 or pin CT16B0_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>MATCH_CHANNEL_3_MATC</name>
|
|
<description>Match channel 3 match channel 3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for match channel 3match channel 3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="CT16B0">
|
|
<name>CT16B1</name>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT16B1</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CT32B0</name>
|
|
<description>32-bit counter/timer CT32B0/1 </description>
|
|
<groupName>CT32B0</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT32B0</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IR</name>
|
|
<description>Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0INT</name>
|
|
<description>Interrupt flag for match channel 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR1INT</name>
|
|
<description>Interrupt flag for match channel 1.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR2INT</name>
|
|
<description>Interrupt flag for match channel 2.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MR3INT</name>
|
|
<description>Interrupt flag for match channel 3.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR0INT</name>
|
|
<description>Interrupt flag for capture channel 0 event.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CR1INT</name>
|
|
<description>Interrupt flag for capture channel 1 event.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CRST</name>
|
|
<description>When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TC</name>
|
|
<description>Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Timer counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<description>Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Prescale value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PC</name>
|
|
<description>Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PC</name>
|
|
<description>Prescale counter value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MR0I</name>
|
|
<description>Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0R</name>
|
|
<description>Reset on MR0: the TC will be reset if MR0 matches it.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR0S</name>
|
|
<description>Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1I</name>
|
|
<description>Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1R</name>
|
|
<description>Reset on MR1: the TC will be reset if MR1 matches it.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR1S</name>
|
|
<description>Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2I</name>
|
|
<description>Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2R</name>
|
|
<description>Reset on MR2: the TC will be reset if MR2 matches it.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR2S</name>
|
|
<description>Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3I</name>
|
|
<description>Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3R</name>
|
|
<description>Reset on MR3: the TC will be reset if MR3 matches it.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MR3S</name>
|
|
<description>Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>MR%s</name>
|
|
<description>Match Register. MR can be enabled through the
|
|
MCR to reset the TC, stop both the TC and PC, and/or generate an
|
|
interrupt every time MR matches the TC.</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Timer counter match value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP0RE</name>
|
|
<description>Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0FE</name>
|
|
<description>Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP0I</name>
|
|
<description>Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1RE</name>
|
|
<description>Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1FE</name>
|
|
<description>Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAP1I</name>
|
|
<description>Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP1 event will generate an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:6]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-1</dimIndex>
|
|
<name>CR%s</name>
|
|
<description>Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input.</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Timer counter capture value.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<description>External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>EMC0</name>
|
|
<description>External Match Control 0. Determines the functionality of External Match 0.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC1</name>
|
|
<description>External Match Control 1. Determines the functionality of External Match 1.</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC2</name>
|
|
<description>External Match Control 2. Determines the functionality of External Match 2.</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMC3</name>
|
|
<description>External Match Control 3. Determines the functionality of External Match 3.</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DO_NOTHING_</name>
|
|
<description>Do Nothing.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CLEAR_THE_CORRESPOND</name>
|
|
<description>Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SET_THE_CORRESPONDIN</name>
|
|
<description>Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TOGGLE_THE_CORRESPON</name>
|
|
<description>Toggle the corresponding External Match bit/output.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTCR</name>
|
|
<description>Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CTM</name>
|
|
<description>Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>TIMER_MODE_EVERY_RI</name>
|
|
<description>Timer Mode: every rising PCLK edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COUNTER_MODE_TC_IS_</name>
|
|
<description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIS</name>
|
|
<description>Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_CAP0</name>
|
|
<description>CT32Bn_CAP0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CT32BN_CAP1</name>
|
|
<description>CT32Bn_CAP1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_NOTE_IF_CO</name>
|
|
<description>Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENCC</name>
|
|
<description>Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SELCC</name>
|
|
<description>When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CAP0_</name>
|
|
<description>Rising Edge of CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CAP0</name>
|
|
<description>Falling Edge of CAP0 clears the timer (if bit 4 is set).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RISING_EDGE_OF_CAP1_</name>
|
|
<description>Rising Edge of CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING_EDGE_OF_CAP1</name>
|
|
<description>Falling Edge of CAP1 clears the timer (if bit 4 is set).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMC</name>
|
|
<description>PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>PWM channel 0 enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT0_IS_CONTR</name>
|
|
<description>CT32Bn_MAT0 is controlled by EM0.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>PWM channel 1 enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT1_IS_CONTR</name>
|
|
<description>CT32Bn_MAT1 is controlled by EM1.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT1.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>PWM channel 2 enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT2_IS_CONTR</name>
|
|
<description>CT32Bn_MAT2 is controlled by EM2.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT2.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CT32BN_MAT3_IS_CONTR</name>
|
|
<description>CT32Bn_MAT3 is controlled by EM3.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_MODE_IS_ENABLED_</name>
|
|
<description>PWM mode is enabled for CT32Bn_MAT3.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral derivedFrom="CT32B0">
|
|
<name>CT32B1</name>
|
|
<baseAddress>0x40018000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CT32B1</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC</name>
|
|
<description>10-bit ADC</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x4001C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01).</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>Burst mode</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>SWMODE</name>
|
|
<description>Software-controlled mode: Conversions are software-controlled and require 11 clocks.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HWMODE</name>
|
|
<description>Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>10BIT</name>
|
|
<description>11 clocks / 10 bits</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9BIT</name>
|
|
<description>10 clocks / 9 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8BIT</name>
|
|
<description>9 clocks / 8 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7BIT</name>
|
|
<description>8 clocks / 7 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6BIT</name>
|
|
<description>7 clocks / 6 bits</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5BIT</name>
|
|
<description>6 clocks / 5 bits</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4BIT</name>
|
|
<description>5 clocks / 4 bits</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3BIT</name>
|
|
<description>4 clocks / 3 bits</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>When the BURST bit is 0, these bits control whether and when an A/D conversion is started:</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>STOP</name>
|
|
<description>No start (this value should be used when clearing PDN to 0).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>START</name>
|
|
<description>Start conversion now.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGEPIO0_2</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGEPIO1_5</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGECT32B0_MAT0_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1].</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGECT32B0_MAT1_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1].</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGECT16B0_MAT0_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1].</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>EDGECT16B0_MAT1_1</name>
|
|
<description>Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1].</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDGE</name>
|
|
<description>This bit is significant only when the START field contains 010-111. In these cases: Start conversion on a falling edge on the selected CAP/MAT signal.</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>RISING</name>
|
|
<description>Start conversion on a rising edge on the selected CAP/MAT signal.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FALLING</name>
|
|
<description>Start conversion on a rising edge on the selected CAP/MAT signal.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GDR</name>
|
|
<description>A/D Global Data Register. Contains the result of the most recent A/D conversion.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CHN</name>
|
|
<description>These bits contain the channel from which the result bits V_VREF were converted.</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. These bits always read as zeroes.</description>
|
|
<bitRange>[29:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag.</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>These bits mirror the DONE status flags that appear in the result register for each A/D channel n.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel n. Reading ADSTAT allows checking the status of all A/D channels simultaneously.</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADINT</name>
|
|
<description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused, always 0.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADINTENn</name>
|
|
<description>These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADGINTEN</name>
|
|
<description>When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Unused, always 0.</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-7</dimIndex>
|
|
<name>DR%s</name>
|
|
<description>A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n.</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, always 0. These bits always read as zeroes. </description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>V_VREF</name>
|
|
<description>When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF.</description>
|
|
<bitRange>[15:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>These bits always read as zeroes. </description>
|
|
<bitRange>[29:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>OVERRUN</name>
|
|
<description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register.</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMU</name>
|
|
<description>Power management unit</description>
|
|
<groupName>PMU</groupName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
|
|
<registers>
|
|
<register>
|
|
<name>PCON</name>
|
|
<description>Power control register</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write 1 to this bit.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPDEN</name>
|
|
<description>Deep power-down mode enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>SLEEPMODE</name>
|
|
<description>ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 core turned off).</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEEPPOWERDOWN</name>
|
|
<description>ARM WFI will enter Deep-power down mode (ARM Cortex-M0 core powered-down).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[7:2]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SLEEPFLAG</name>
|
|
<description>Sleep mode flag</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>NOPOWERDOWN</name>
|
|
<description>Read: No power-down mode entered. LPC111x is in Active mode. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERDOWN</name>
|
|
<description>Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>DPDFLAG</name>
|
|
<description>Deep power-down flag</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>NODEEPPOWERDOWN</name>
|
|
<description>Read: Deep power-down mode not entered. Write: No effect.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DEEPPOWERDOWN</name>
|
|
<description>Read: Deep power-down mode entered. Write: Clear the Deep power-down flag.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0-3</dimIndex>
|
|
<name>GPREG%s</name>
|
|
<description>General purpose register</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPDATA</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPREG4</name>
|
|
<description>General purpose register 4</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to this bit.</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WAKEUPHYS</name>
|
|
<description>WAKEUP pin hysteresis enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Hysteresis for WAKEUP pin enabled.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Hysteresis for WAKUP pin disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPDATA</name>
|
|
<description>Data retained during Deep power-down mode.</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASHCTRL</name>
|
|
<description>Flash programming firmware</description>
|
|
<groupName>FLASHCTRL</groupName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FMC</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FLASHCFG</name>
|
|
<description>Flash memory access time configuration register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLASHTIM</name>
|
|
<description>Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>1_SYSTEM_CLOCK_FLASH</name>
|
|
<description>1 system clock flash access time (for system clock frequencies of up to 20 MHz).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_SYSTEM_CLOCKS_FLAS</name>
|
|
<description>2 system clocks flash access time (for system clock frequencies of up to 40 MHz).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_SYSTEM_CLOCKS_FLAS</name>
|
|
<description>3 system clocks flash access time (for system clock frequencies of up to 50 MHz).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSSTART</name>
|
|
<description>Signature start address register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Signature generation start address (corresponds to AHB byte address bits[20:4]).</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSSTOP</name>
|
|
<description>Signature stop-address register</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>BIST stop address divided by 16 (corresponds to AHB byte address [20:4]).</description>
|
|
<bitRange>[16:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>SIG_START</name>
|
|
<description>Start control bit for signature generation.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SIGNATURE_GENERATION</name>
|
|
<description>Signature generation is stopped</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INITIATE_SIGNATURE_G</name>
|
|
<description>Initiate signature generation</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:18]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW0</name>
|
|
<description>Word 0 [31:0]</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW0_31_0</name>
|
|
<description>Word 0 of 128-bit signature (bits 31 to 0).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW1</name>
|
|
<description>Word 1 [63:32]</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW1_63_32</name>
|
|
<description>Word 1 of 128-bit signature (bits 63 to 32).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW2</name>
|
|
<description>Word 2 [95:64]</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW2_95_64</name>
|
|
<description>Word 2 of 128-bit signature (bits 95 to 64).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSW3</name>
|
|
<description>Word 3 [127:96]</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW3_127_96</name>
|
|
<description>Word 3 of 128-bit signature (bits 127 to 96).</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSTAT</name>
|
|
<description>Signature generation status register</description>
|
|
<addressOffset>0xFE0</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIG_DONE</name>
|
|
<description>When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMSTATCLR</name>
|
|
<description>Signature generation status clear register</description>
|
|
<addressOffset>0xFE8</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SIG_DONE_CLR</name>
|
|
<description>Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>SPI0</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSS</name>
|
|
<description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>4_BIT_TRANSFER</name>
|
|
<description>4-bit transfer</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5_BIT_TRANSFER</name>
|
|
<description>5-bit transfer</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6_BIT_TRANSFER</name>
|
|
<description>6-bit transfer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7_BIT_TRANSFER</name>
|
|
<description>7-bit transfer</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>8_BIT_TRANSFER</name>
|
|
<description>8-bit transfer</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>9_BIT_TRANSFER</name>
|
|
<description>9-bit transfer</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10_BIT_TRANSFER</name>
|
|
<description>10-bit transfer</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11_BIT_TRANSFER</name>
|
|
<description>11-bit transfer</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12_BIT_TRANSFER</name>
|
|
<description>12-bit transfer</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13_BIT_TRANSFER</name>
|
|
<description>13-bit transfer</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14_BIT_TRANSFER</name>
|
|
<description>14-bit transfer</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15_BIT_TRANSFER</name>
|
|
<description>15-bit transfer</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16_BIT_TRANSFER</name>
|
|
<description>16-bit transfer</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame Format.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPI</name>
|
|
<description>SPI</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TI</name>
|
|
<description>TI</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MICROWIRE</name>
|
|
<description>Microwire</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>This combination is not supported and should not be used.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Out Polarity. This bit is only used in SPI mode.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>SPI controller maintains the bus clock low between frames.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>SPI controller maintains the bus clock high between frames.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Out Phase. This bit is only used in SPI mode.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>FIRSTCLOCK</name>
|
|
<description>SPI controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SECONDCLOCK</name>
|
|
<description>SPI controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCR</name>
|
|
<description>Serial Clock Rate. The number of prescaler output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>Control Register 1. Selects master/slave and other modes.</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loop Back Mode.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>NORMAL</name>
|
|
<description>During normal operation.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LOOPBACK</name>
|
|
<description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSE</name>
|
|
<description>SPI Enable.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>The SPI controller is disabled.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>The SPI controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SPI/SSP registers and interrupt controller registers, before setting this bit.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MS</name>
|
|
<description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>test</name>
|
|
<enumeratedValue>
|
|
<name>MASTER</name>
|
|
<description>The SPI controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SLAVE</name>
|
|
<description>The SPI controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOD</name>
|
|
<description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SPI controller from driving the transmit data line (MISO).</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<readAction>modify</readAction>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SPI controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SPI controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s.</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TNF</name>
|
|
<description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RNE</name>
|
|
<description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy. This bit is 0 if the SPI controller is idle, 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSR</name>
|
|
<description>Clock Prescale Register</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPSDVSR</name>
|
|
<description>This even value between 2 and 254, by which SPI_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMSC</name>
|
|
<description>Interrupt Mask Set and Clear Register</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIM</name>
|
|
<description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXIM</name>
|
|
<description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status Register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000008</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORRIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXRIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXRIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked Interrupt Status Register</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORMIS</name>
|
|
<description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RXMIS</name>
|
|
<description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TXMIS</name>
|
|
<description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSPICR Interrupt Clear Register</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RORIC</name>
|
|
<description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RTIC</name>
|
|
<description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a timeout period interrupt. The timeout period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]).</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IOCON</name>
|
|
<description>I/O configuration (IOCONFIG) </description>
|
|
<groupName>IOCON</groupName>
|
|
<baseAddress>0x40044000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IOCON_PIO2_6</name>
|
|
<description>I/O configuration for pin PIO2_6/ CT32B0_MAT1</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_0</name>
|
|
<description>I/O configuration for pin PIO2_0/DTR/SSEL1</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_DTR_</name>
|
|
<description>Select function DTR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_SSEL</name>
|
|
<description>Select function SSEL1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_RESET_PIO0_0</name>
|
|
<description>I/O configuration for pin RESET/PIO0_0</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RES</name>
|
|
<description>Selects function RESET.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_1</name>
|
|
<description>I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2</description>
|
|
<addressOffset>0x010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CLK</name>
|
|
<description>Selects function CLKOUT.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_8</name>
|
|
<description>I/O configuration for pin PIO1_8/CT16B1_CAP0</description>
|
|
<addressOffset>0x014</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_8.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B1_CAP0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_2</name>
|
|
<description>I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0</description>
|
|
<addressOffset>0x01C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SSE</name>
|
|
<description>Selects function SSEL0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_7</name>
|
|
<description>I/O configuration for pin PIO2_7/ CT32B0_MAT2/RXD</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RXD</name>
|
|
<description>Selects function RXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_8</name>
|
|
<description>I/O configuration for pin PIO2_8/ CT32B0_MAT3/TXD</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_8.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_TXD</name>
|
|
<description>Selects function TXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_1</name>
|
|
<description>I/O configuration for pin PIO2_1/DSR/SCK1</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_DSR_</name>
|
|
<description>Select function DSR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_SCK1</name>
|
|
<description>Select function SCK1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_3</name>
|
|
<description>I/O configuration for pin PIO0_3</description>
|
|
<addressOffset>0x02C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_4</name>
|
|
<description>I/O configuration for pin PIO0_4/SCL</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_4 (open-drain pin).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_I2C_FUNCTION</name>
|
|
<description>Selects I2C function SCL (open-drain pin).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CMODE</name>
|
|
<description>Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_MODE_FAST</name>
|
|
<description>Standard mode/ Fast-mode I2C.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDARD_IO_FUNCTION</name>
|
|
<description>Standard I/O functionality</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_I2C</name>
|
|
<description>Fast-mode Plus I2C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_5</name>
|
|
<description>I/O configuration for pin PIO0_5/SDA</description>
|
|
<addressOffset>0x034</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_5 (open-drain pin).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_I2C_FUNCTION</name>
|
|
<description>Selects I2C function SDA (open-drain pin).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2CMODE</name>
|
|
<description>Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_MODE_FAST</name>
|
|
<description>Standard mode/ Fast-mode I2C.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>STANDARD_IO_FUNCTION</name>
|
|
<description>Standard I/O functionality</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>FAST_MODE_PLUS_I2C</name>
|
|
<description>Fast-mode Plus I2C</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_9</name>
|
|
<description>I/O configuration for pin PIO1_9/CT16B1_MAT0/ MOSI1</description>
|
|
<addressOffset>0x038</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_9.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B1_MAT0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_MOS</name>
|
|
<description>Selects function MOSI1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_4</name>
|
|
<description>I/O configuration for pin PIO3_4/ CT16B0_CAP1/RXD</description>
|
|
<addressOffset>0x03C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_4.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_CAP1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RXD</name>
|
|
<description>Selects function RXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_4</name>
|
|
<description>I/O configuration for pin PIO2_4/ CT16B1_MAT1/ SSEL1</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_4.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B1_MAT1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SSE</name>
|
|
<description>Selects function SSEL1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_5</name>
|
|
<description>I/O configuration for pin PIO2_5/ CT32B0_MAT0</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_5.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_5</name>
|
|
<description>I/O configuration for pin PIO3_5/ CT16B1_CAP1/TXD</description>
|
|
<addressOffset>0x048</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_5.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B1_CAP1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_TXD</name>
|
|
<description>Selects function TXD.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_6</name>
|
|
<description>I/O configuration for pin PIO0_6/SCK0</description>
|
|
<addressOffset>0x04C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SCK</name>
|
|
<description>Selects function SCK0 (only if pin PIO0_6/SCK0 selected in Table 147).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_7</name>
|
|
<description>I/O configuration for pin PIO0_7/CTS</description>
|
|
<addressOffset>0x050</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_CTS_</name>
|
|
<description>Select function CTS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_9</name>
|
|
<description>I/O configuration for pin PIO2_9/ CT32B0_CAP0</description>
|
|
<addressOffset>0x054</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_9.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_CAP0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_10</name>
|
|
<description>I/O configuration for pin PIO2_10</description>
|
|
<addressOffset>0x058</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_10.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_2</name>
|
|
<description>I/O configuration for pin PIO2_2/DCD/MISO1</description>
|
|
<addressOffset>0x05C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_DCD_</name>
|
|
<description>Select function DCD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_MISO</name>
|
|
<description>Select function MISO1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_8</name>
|
|
<description>I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0</description>
|
|
<addressOffset>0x060</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_8.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_MIS</name>
|
|
<description>Selects function MISO0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO0_9</name>
|
|
<description>I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1</description>
|
|
<addressOffset>0x064</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_9.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_MOS</name>
|
|
<description>Selects function MOSI0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_SWCLK_PIO0_10</name>
|
|
<description>I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2</description>
|
|
<addressOffset>0x068</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SWC</name>
|
|
<description>Selects function SWCLK.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_10.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SCK</name>
|
|
<description>Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 147).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_10</name>
|
|
<description>I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1/ MISO1</description>
|
|
<addressOffset>0x06C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_10.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD6</name>
|
|
<description>Selects function AD6.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B1_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_MIS</name>
|
|
<description>Selects function MISO1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_11</name>
|
|
<description>I/O configuration for pin PIO2_11/SCK0/ CT32B0_CAP1</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_11.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_SCK0</name>
|
|
<description>Select function SCK0 (only if pin PIO2_11/SCK0 selected in Table 147).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECT_FUNCTION_CT32</name>
|
|
<description>Select function CT32B0_CAP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_R_PIO0_11</name>
|
|
<description>I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_R_</name>
|
|
<description>Selects function R. This function is reserved. Select one of the alternate functions below.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO0_11.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD0</name>
|
|
<description>Selects function AD0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT3.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_R_PIO1_0</name>
|
|
<description>I/O configuration for pin R/PIO1_0/AD1/CT32B1_CAP0</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_R_</name>
|
|
<description>Selects function R. This function is reserved. Select one of the alternate functions below.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_0.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD1</name>
|
|
<description>Selects function AD1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_CAP0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_R_PIO1_1</name>
|
|
<description>I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0</description>
|
|
<addressOffset>0x07C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_R_</name>
|
|
<description>Selects function R. This function is reserved. Select one of the alternate functions below.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_1.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD2</name>
|
|
<description>Selects function AD2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_MAT0.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_R_PIO1_2</name>
|
|
<description>I/O configuration for pin R/PIO1_2/AD3/CT32B1_MAT1</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_R_</name>
|
|
<description>Selects function R. This function is reserved. Select one of the alternate functions below.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_2.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD3</name>
|
|
<description>Selects function AD3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_MAT1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_0</name>
|
|
<description>I/O configuration for pin PIO3_0/DTR/CT16B0_MAT0/TXD</description>
|
|
<addressOffset>0x084</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_0.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_DTR</name>
|
|
<description>Selects function DTR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_TXD</name>
|
|
<description>Selects function TXD.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_1</name>
|
|
<description>I/O configuration for pin PIO3_1/DSR/CT16B0_MAT1/RXD</description>
|
|
<addressOffset>0x088</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_1.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_DSR</name>
|
|
<description>Selects function DSR.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RXD</name>
|
|
<description>Selects function RXD.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO2_3</name>
|
|
<description>I/O configuration for pin PIO2_3/RI/MOSI1</description>
|
|
<addressOffset>0x08C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO2_3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RI_</name>
|
|
<description>Selects function RI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_MOS</name>
|
|
<description>Selects function MOSI1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_SWDIO_PIO1_3</name>
|
|
<description>I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2</description>
|
|
<addressOffset>0x090</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SWD</name>
|
|
<description>Selects function SWDIO.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_3.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD4</name>
|
|
<description>Selects function AD4.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_MAT2.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_4</name>
|
|
<description>I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. This pin functions as WAKEUP pin if the LPC111x is in Deep power-down mode regardless of the value of FUNC. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_4.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD5</name>
|
|
<description>Selects function AD5.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_MAT3.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_11</name>
|
|
<description>I/O configuration for pin PIO1_11/AD7/CT32B1_CAP1</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_11.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_AD7</name>
|
|
<description>Selects function AD7.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B1_CAP1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Selects Analog/Digital mode</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>ANALOG_INPUT_MODE</name>
|
|
<description>Analog input mode</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>DIGITAL_FUNCTIONAL_M</name>
|
|
<description>Digital functional mode</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_2</name>
|
|
<description>I/O configuration for pin PIO3_2/DCD/ CT16B0_MAT2/SCK1</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_2.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_DCD</name>
|
|
<description>Selects function DCD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_MAT2.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_SCK</name>
|
|
<description>Selects function SCK1.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_5</name>
|
|
<description>I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0</description>
|
|
<addressOffset>0x0A0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_5.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RTS</name>
|
|
<description>Selects function RTS.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_6</name>
|
|
<description>I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0</description>
|
|
<addressOffset>0x0A4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_6.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RXD</name>
|
|
<description>Selects function RXD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO1_7</name>
|
|
<description>I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1</description>
|
|
<addressOffset>0x0A8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO1_7.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_TXD</name>
|
|
<description>Selects function TXD.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT3</name>
|
|
<description>Selects function CT32B0_MAT1.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_PIO3_3</name>
|
|
<description>I/O configuration for pin PIO3_3/RI/ CT16B0_CAP0</description>
|
|
<addressOffset>0x0AC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0xD0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>Selects pin function. All other values are reserved.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_PIO</name>
|
|
<description>Selects function PIO3_3.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_RI_</name>
|
|
<description>Selects function RI.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_FUNCTION_CT1</name>
|
|
<description>Selects function CT16B0_CAP0.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>INACTIVE_NO_PULL_DO</name>
|
|
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_DOWN_RESISTOR_E</name>
|
|
<description>Pull-down resistor enabled.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PULL_UP_RESISTOR_ENA</name>
|
|
<description>Pull-up resistor enabled.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>REPEATER_MODE_</name>
|
|
<description>Repeater mode.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HYS</name>
|
|
<description>Hysteresis.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>DISABLE_</name>
|
|
<description>Disable.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_</name>
|
|
<description>Enable.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>OD</name>
|
|
<description>Selects pseudo open-drain mode.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>STANDARD_GPIO_OUTPUT</name>
|
|
<description>Standard GPIO output</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>OPEN_DRAIN_OUTPUT</name>
|
|
<description>Open-drain output</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:11]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_SCK0_LOC</name>
|
|
<description>SCK0 pin location select register</description>
|
|
<addressOffset>0x0B0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKLOC</name>
|
|
<description>Selects pin location for SCK0 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_SCK0_FUNCTIO</name>
|
|
<description>Selects SCK0 function in pin location SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (see Table 129).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SCK0_FUNCTIO</name>
|
|
<description>Selects SCK0 function in pin location PIO2_11/SCK0 (see Table 131).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SCK0_FUNCTIO</name>
|
|
<description>Selects SCK0 function in pin location PIO0_6/SCK0 (see Table 122).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_DSR_LOC</name>
|
|
<description>DSR pin location select register</description>
|
|
<addressOffset>0x0B4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSRLOC</name>
|
|
<description>Selects pin location for DSR function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_DSR_FUNCTIO</name>
|
|
<description>Selects DSR function in pin location PIO2_1/DSR/SCK1 (see Table 113).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_DSR_FUNCTION</name>
|
|
<description>Selects DSR function in pin location PIO3_1/DSR (see Table 137).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_DCD_LOC</name>
|
|
<description>DCD pin location select register</description>
|
|
<addressOffset>0x0B8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DCDLOC</name>
|
|
<description>Selects pin location for DCD function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_DCD_FUNCTIO</name>
|
|
<description>Selects DCD function in pin location PIO2_2/DCD/MISO1 (see Table 126).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_DCD_FUNCTION</name>
|
|
<description>Selects DCD function in pin location PIO3_2/DCD (see Table 142).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_RI_LOC</name>
|
|
<description>RI pin location select register</description>
|
|
<addressOffset>0x0BC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RILOC</name>
|
|
<description>Selects pin location for RI function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_RI_FUNCTION</name>
|
|
<description>Selects RI function in pin location PIO2_3/RI/MOSI1 (see Table 138).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_RI_FUNCTION_</name>
|
|
<description>Selects RI function in pin location PIO3_3/RI (see Table 146).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_SSEL1_LOC</name>
|
|
<description>SSEL1 pin location select register</description>
|
|
<addressOffset>0x018</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSEL1LOC</name>
|
|
<description>Selects pin location for SSEL1 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_SSEL1_FUNCTI</name>
|
|
<description>Selects SSEL1 function in pin location PIO2_2/DCD/MISO1 (see Table 126).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SSEL1_FUNCTI</name>
|
|
<description>Selects SSEL1 function in pin location PIO2_4/CT16B1_MAT1/SSEL1 (see Table 119).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_CT16B0_CAP0_LOC</name>
|
|
<description>CT16B0_CAP0 pin location select register</description>
|
|
<addressOffset>0x0C0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CT16B0_CAP0LOC</name>
|
|
<description>Selects pin location for CT16B0_CAP0 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_CT16B0_CAP0_</name>
|
|
<description>Selects CT16B0_CAP0 function in pin location PIO0_2/SSEL0/CT16B0_CAP0 (see Table 110).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_CT16B0_CAP0_</name>
|
|
<description>Selects CT16B0_CAP0 function in pin location PIO3_3/RI/CT16B0 (see Table 146).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_SCK1_LOC</name>
|
|
<description>SCK1 pin location select register</description>
|
|
<addressOffset>0x0C4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCK1LOC</name>
|
|
<description>Selects pin location for SCK1 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_SCK1_FUNCTIO</name>
|
|
<description>Selects SCK1 function in pin location PIO2_1/DSR/SCK1 (see Table 113).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_SCK1_FUNCTIO</name>
|
|
<description>Selects SCK1 function in pin location PIO3_2/DCD/CT16B0_MAT2/SCK1 (see Table 142).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_MISO1_LOC</name>
|
|
<description>MISO1 pin location select register</description>
|
|
<addressOffset>0x0C8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MISO1LOC</name>
|
|
<description>Selects pin location for the MISO1 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_MISO1_FUNCTI</name>
|
|
<description>Selects MISO1 function in pin location PIO2_2/DCD/MISO1 (see Table 126).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_MISO1_FUNCTI</name>
|
|
<description>Selects MISO1 function in pin location PIO1_10/AD6/CT16B1_MAT1/MISO1 (see Table 130).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_MOSI1_LOC</name>
|
|
<description>MOSI1 pin location select register</description>
|
|
<addressOffset>0x0CC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOSI1LOC</name>
|
|
<description>Selects pin location for the MOSI1 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_MOSI1_FUNCTI</name>
|
|
<description>Selects MOSI1 function in pin location PIO2_3/RI/MOSI1 (see Table 138).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_MOSI1_FUNCTI</name>
|
|
<description>Selects MOSI1 function in pin location PIO1_9/CT16B1_MAT0/MOSI1 (see Table 117).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_CT32B0_CAP0_LOC</name>
|
|
<description>CT32B0_CAP0 pin location select register</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CT32B0_CAP0LOC</name>
|
|
<description>Selects pin location for the CT32B0_CAP0 function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_CT32B0_CAP0_</name>
|
|
<description>Selects CT32B0_CAP0 function in pin location PIO1_5/RTS/CT32B0_CAP0 (see Table 143).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_CT32B0_CAP0_</name>
|
|
<description>Selects CT32B0_CAP0 function in pin location PIO2_9/CT32B0_CAP0 (Table 124).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED_</name>
|
|
<description>Reserved.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOCON_RXD_LOC</name>
|
|
<description>RXD pin location select register</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXDLOC</name>
|
|
<description>Selects pin location for the RXD function.</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
|
|
<enumeratedValue>
|
|
<name>SELECTS_RXD_FUNCTION</name>
|
|
<description>Selects RXD function in pin location PIO1_6/RXD/CT32B0_MAT0 (see Table 144).</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_RXD_FUNCTION</name>
|
|
<description>Selects RXD function in pin location PIO2_7/CT32B0_MAT2/RXD (see Table 111).</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_RXD_FUNCTION</name>
|
|
<description>Selects RXD function in pin location PIO3_1/DSR/CT16B0_MAT1/RXD (see Table 137).</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SELECTS_RXD_FUNCTION</name>
|
|
<description>Selects RXD function in pin location PIO3_4/CT16B0_CAP1/RXD (see Table 118).</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved.</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>SYSCON</name>
|
|
<description>System configuration (SYSCON)</description>
|
|
<groupName>SYSCON</groupName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>BOD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_0</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_1</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_2</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_3</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_4</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_5</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_6</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_7</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_8</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_9</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_10</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO0_11</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>PIO1_0</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SYSMEMREMAP</name>
|
|
<description>System memory remap</description>
|
|
<addressOffset>0x000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x002</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAP</name>
|
|
<description>System memory remap</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>BOOT_LOADER_MODE_IN</name>
|
|
<description>Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USER_RAM_MODE_INTER</name>
|
|
<description>User RAM Mode. Interrupt vectors are re-mapped to Static RAM.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>USER_FLASH_MODE_INT</name>
|
|
<description>User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESETCTRL</name>
|
|
<description>Peripheral reset control</description>
|
|
<addressOffset>0x004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSP0_RST_N</name>
|
|
<description>SPI0 reset control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPIO0RESET</name>
|
|
<description>Resets the SPI0 peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPIO0NORESET</name>
|
|
<description>SPI0 reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C_RST_N</name>
|
|
<description>I2C reset control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>I2CRESET</name>
|
|
<description>Resets the I2C peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>I2CNORESET</name>
|
|
<description>I2C reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSP1_RST_N</name>
|
|
<description>SPI1 reset control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>SPI1RESET</name>
|
|
<description>Resets the SPI1 peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SPI2NORESET</name>
|
|
<description>SPI1 reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN_RST_N</name>
|
|
<description>C_CAN reset control. See Section 3.1 for part specific details.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>CANRESET</name>
|
|
<description>Resets the C_CAN peripheral.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>CANNORESET</name>
|
|
<description>C_CAN reset de-asserted.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:4]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCTRL</name>
|
|
<description>System PLL control</description>
|
|
<addressOffset>0x008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Post divider ratio P. The division ratio is 2 x P.</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>P_EQ_1</name>
|
|
<description>P = 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_2</name>
|
|
<description>P = 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_4</name>
|
|
<description>P = 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>P_EQ_8</name>
|
|
<description>P = 8</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write ones to reserved bits.</description>
|
|
<bitRange>[31:7]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLSTAT</name>
|
|
<description>System PLL status</description>
|
|
<addressOffset>0x00C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>PLL lock status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>PLL_NOT_LOCKED</name>
|
|
<description>PLL not locked</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PLL_LOCKED</name>
|
|
<description>PLL locked</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSOSCCTRL</name>
|
|
<description>System oscillator control</description>
|
|
<addressOffset>0x020</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BYPASS</name>
|
|
<description>Bypass system oscillator</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NOBYPASS</name>
|
|
<description>Oscillator is not bypassed.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BYPASS_ENABLED_PLL_</name>
|
|
<description>Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FREQRANGE</name>
|
|
<description>Determines frequency range for Low-power oscillator.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LOW</name>
|
|
<description>1 - 20 MHz frequency range.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>HIGH</name>
|
|
<description>15 - 25 MHz frequency range</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTOSCCTRL</name>
|
|
<description>Watchdog oscillator control</description>
|
|
<addressOffset>0x024</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVSEL</name>
|
|
<description>Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>FREQSEL</name>
|
|
<description>Select watchdog oscillator analog output frequency (Fclkana).</description>
|
|
<bitRange>[8:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>0_6_MHZ</name>
|
|
<description>0.6 MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_05_MHZ</name>
|
|
<description>1.05 MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_4_MHZ</name>
|
|
<description>1.4 MHz</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1_75_MHZ</name>
|
|
<description>1.75 MHz</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_1_MHZ</name>
|
|
<description>2.1 MHz</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_4_MHZ</name>
|
|
<description>2.4 MHz</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2_7_MHZ</name>
|
|
<description>2.7 MHz</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_0_MHZ</name>
|
|
<description>3.0 MHz</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_25_MHZ</name>
|
|
<description>3.25 MHz</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_5_MHZ</name>
|
|
<description>3.5 MHz</description>
|
|
<value>0xA</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3_75_MHZ</name>
|
|
<description>3.75 MHz</description>
|
|
<value>0xB</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_0_MHZ</name>
|
|
<description>4.0 MHz</description>
|
|
<value>0xC</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_2_MHZ</name>
|
|
<description>4.2 MHz</description>
|
|
<value>0xD</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_4_MHZ</name>
|
|
<description>4.4 MHz</description>
|
|
<value>0xE</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4_6_MHZ</name>
|
|
<description>4.6 MHz</description>
|
|
<value>0xF</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:9]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRCCTRL</name>
|
|
<description>IRC control</description>
|
|
<addressOffset>0x028</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x080</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>Trim value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSRSTSTAT</name>
|
|
<description>System reset status register</description>
|
|
<addressOffset>0x030</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>POR reset status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_POR_DETECTED_</name>
|
|
<description>No POR detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POR_DETECTED_WRITIN</name>
|
|
<description>POR detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EXTRST</name>
|
|
<description>Status of the external RESET pin.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_RESET_EVENT_DETEC</name>
|
|
<description>No RESET event detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESET_DETECTED_WRIT</name>
|
|
<description>RESET detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Status of the Watchdog reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_WDT_RESET_DETECTE</name>
|
|
<description>No WDT reset detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_RESET_DETECTED_</name>
|
|
<description>WDT reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD</name>
|
|
<description>Status of the Brown-out detect reset</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_BOD_RESET_DETECTE</name>
|
|
<description>No BOD reset detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>BOD_RESET_DETECTED_</name>
|
|
<description>BOD reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSRST</name>
|
|
<description>Status of the software system reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_SYSTEM_RESET_DETE</name>
|
|
<description>No System reset detected.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_RESET_DETECTE</name>
|
|
<description>System reset detected. Writing a one clears this reset.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCLKSEL</name>
|
|
<description>System PLL clock source select</description>
|
|
<addressOffset>0x040</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>System PLL clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSPLLCLKUEN</name>
|
|
<description>System PLL clock source update enable</description>
|
|
<addressOffset>0x044</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable system PLL clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKSEL</name>
|
|
<description>Main clock source select</description>
|
|
<addressOffset>0x070</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>Clock source for main clock</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>INPUT_CLOCK_TO_SYSTE</name>
|
|
<description>Input clock to system PLL</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WDT_OSCILLATOR</name>
|
|
<description>WDT oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_PLL_CLOCK_OUT</name>
|
|
<description>System PLL clock out</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAINCLKUEN</name>
|
|
<description>Main clock source update enable</description>
|
|
<addressOffset>0x074</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable main clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKDIV</name>
|
|
<description>System AHB clock divider</description>
|
|
<addressOffset>0x078</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSAHBCLKCTRL</name>
|
|
<description>System AHB clock control</description>
|
|
<addressOffset>0x080</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x85F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYS</name>
|
|
<description>Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M0 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Enables clock for ROM.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAM</name>
|
|
<description>Enables clock for RAM.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHREG</name>
|
|
<description>Enables clock for flash register interface.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHARRAY</name>
|
|
<description>Enables clock for flash array access.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLED</name>
|
|
<description>Disabled</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLED</name>
|
|
<description>Enabled</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>I2C</name>
|
|
<description>Enables clock for I2C.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GPIO</name>
|
|
<description>Enables clock for GPIO.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT16B0</name>
|
|
<description>Enables clock for 16-bit counter/timer 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT16B1</name>
|
|
<description>Enables clock for 16-bit counter/timer 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT32B0</name>
|
|
<description>Enables clock for 32-bit counter/timer 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CT32B1</name>
|
|
<description>Enables clock for 32-bit counter/timer 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSP0</name>
|
|
<description>Enables clock for SPI0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART</name>
|
|
<description>Enables clock for UART. See Section 3.1 for part specific details.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC</name>
|
|
<description>Enables clock for ADC.</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDT</name>
|
|
<description>Enables clock for WDT.</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IOCON</name>
|
|
<description>Enables clock for I/O configuration block.</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAN</name>
|
|
<description>Enables clock for C_CAN. See Section 3.1 for part specific details.</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSP1</name>
|
|
<description>Enables clock for SPI1.</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE</name>
|
|
<description>Disable</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE</name>
|
|
<description>Enable</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:19]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSP0CLKDIV</name>
|
|
<description>SPI0 clock divider</description>
|
|
<addressOffset>0x094</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>SPI0_PCLK clock divider values 0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UARTCLKDIV</name>
|
|
<description>UART clock divder</description>
|
|
<addressOffset>0x098</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSP1CLKDIV</name>
|
|
<description>SPI1 clock divder</description>
|
|
<addressOffset>0x09C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>SPI1_PCLK clock divider values 0: Disable SPI1_PCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTCLKSEL</name>
|
|
<description>WDT clock source select</description>
|
|
<addressOffset>0x0D0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>WDT clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR</name>
|
|
<description>Watchdog oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTCLKUEN</name>
|
|
<description>WDT clock source update enable</description>
|
|
<addressOffset>0x0D4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable WDT clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDTCLKDIV</name>
|
|
<description>WDT clock divider</description>
|
|
<addressOffset>0x0D8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>WDT clock divider values 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTCLKSEL</name>
|
|
<description>CLKOUT clock source select</description>
|
|
<addressOffset>0x0E0</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL</name>
|
|
<description>CLKOUT clock source</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>IRC_OSCILLATOR</name>
|
|
<description>IRC oscillator</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSTEM_OSCILLATOR</name>
|
|
<description>System oscillator</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>WATCHDOG_OSCILLATOR</name>
|
|
<description>Watchdog oscillator</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>MAIN_CLOCK</name>
|
|
<description>Main clock</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:2]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTUEN</name>
|
|
<description>CLKOUT clock source update enable</description>
|
|
<addressOffset>0x0E4</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENA</name>
|
|
<description>Enable CLKOUT clock source update</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>NO_CHANGE</name>
|
|
<description>No change</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UPDATE_CLOCK_SOURCE</name>
|
|
<description>Update clock source</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:1]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTCLKDIV</name>
|
|
<description>CLKOUT clock divider</description>
|
|
<addressOffset>0x0E8</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Clock output divider values 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255.</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:8]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP0</name>
|
|
<description>POR captured PIO status 0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPPIO0_n</name>
|
|
<description>Raw reset status input PIO0_n: PIO0_11 to PIO0_0</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO1_n</name>
|
|
<description>Raw reset status input PIO1_n: PIO1_11 to PIO1_0</description>
|
|
<bitRange>[23:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO2_n</name>
|
|
<description>Raw reset status input PIO2_n: PIO2_7 to PIO2_0</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOPORCAP1</name>
|
|
<description>POR captured PIO status 1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAPPIO2_8</name>
|
|
<description>Raw reset status input PIO2_8</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO2_9</name>
|
|
<description>Raw reset status input PIO2_9</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO2_10</name>
|
|
<description>Raw reset status input PIO2_10</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO2_11</name>
|
|
<description>Raw reset status input PIO2_11</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_0</name>
|
|
<description>Raw reset status input PIO3_0</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_1</name>
|
|
<description>Raw reset status input PIO3_1</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_2</name>
|
|
<description>Raw reset status input PIO3_2</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_3</name>
|
|
<description>Raw reset status input PIO3_3</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_4</name>
|
|
<description>Raw reset status input PIO3_4</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CAPPIO3_5</name>
|
|
<description>Raw reset status input PIO3_5</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BODCTRL</name>
|
|
<description>BOD control</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BODRSTLEV</name>
|
|
<description>BOD reset level</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_THE_RESET_A</name>
|
|
<description>Level 0: The reset assertion threshold voltage is 1.46 V; the reset de-assertion threshold voltage is 1.63 V.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1_THE_RESET_A</name>
|
|
<description>Level 1: The reset assertion threshold voltage is 2.06 V; the reset de-assertion threshold voltage is 2.15 V.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_RESET_A</name>
|
|
<description>Level 2: The reset assertion threshold voltage is 2.35 V; the reset de-assertion threshold voltage is 2.43 V.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_RESET_A</name>
|
|
<description>Level 3: The reset assertion threshold voltage is 2.63 V; the reset de-assertion threshold voltage is 2.71 V.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODINTVAL</name>
|
|
<description>BOD interrupt level</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>LEVEL_0_THE_INTERRU</name>
|
|
<description>Level 0: The interrupt assertion threshold voltage is 1.65 V; the interrupt de-assertion threshold voltage is 1.80 V.</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_1THE_INTERRUP</name>
|
|
<description>Level 1:The interrupt assertion threshold voltage is 2.22 V; the interrupt de-assertion threshold voltage is 2.35 V.</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_2_THE_INTERRU</name>
|
|
<description>Level 2: The interrupt assertion threshold voltage is 2.52 V; the interrupt de-assertion threshold voltage is 2.66 V.</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>LEVEL_3_THE_INTERRU</name>
|
|
<description>Level 3: The interrupt assertion threshold voltage is 2.80 V; the interrupt de-assertion threshold voltage is 2.90 V.</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BODRSTENA</name>
|
|
<description>BOD reset enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>DISABLE_RESET_FUNCTI</name>
|
|
<description>Disable reset function.</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ENABLE_RESET_FUNCTIO</name>
|
|
<description>Enable reset function.</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSTCKCAL</name>
|
|
<description>System tick counter calibration</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>System tick timer calibration value</description>
|
|
<bitRange>[25:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:26]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NMISRC</name>
|
|
<description>NMI source selection</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRQNO</name>
|
|
<description>The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 in this register is 1. See Table 54 for the list of interrupt sources and their IRQ numbers.</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[30:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NMIEN</name>
|
|
<description>Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0.</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTAPRP0</name>
|
|
<description>Start logic edge control register 0</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>APRPIO0_0</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_1</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_2</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_3</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_4</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_5</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_6</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_7</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_8</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_9</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_10</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO0_11</name>
|
|
<description>Edge select for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>APRPIO1_0</name>
|
|
<description>Edge select for start logic input PIO1_0 0 = Falling edge 1 = Rising edge</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write a 1 to reserved bits in this register.</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTERP0</name>
|
|
<description>Start logic signal enable register 0</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERPIO0_0</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_1</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_2</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_3</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_4</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_5</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_6</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_7</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_8</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_9</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_10</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO0_11</name>
|
|
<description>Enable start signal for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ERPIO1_0</name>
|
|
<description>Enable start signal for start logic input PIO1_0 0 = Disabled 1 = Enabled</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write a 1 to reserved bits in this register.</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTRSRP0CLR</name>
|
|
<description>Start logic reset register 0</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSRPIO0_0</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_1</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_2</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_3</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_4</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_5</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_6</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_7</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_8</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_9</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_10</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO0_11</name>
|
|
<description>Start signal reset for start logic input PIO0_n:PIO0_11 to PIO0_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RSRPIO1_0</name>
|
|
<description>Start signal reset for start logic input PIO1_0 0 = Do nothing. 1 = Writing 1 resets the start signal.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved. Do not write a 1 to reserved bits in this register.</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STARTSRP0</name>
|
|
<description>Start logic status register 0</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRPIO0_0</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_1</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_2</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_3</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_4</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_5</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_6</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_7</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_8</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_9</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_10</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO0_11</name>
|
|
<description>Start signal status for start logic input PIO0_n: PIO0_11 to PIO0_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SRPIO1_0</name>
|
|
<description>Start signal status for start logic input PIO1_0 0 = No start signal received. 1 = Start signal pending.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDSLEEPCFG</name>
|
|
<description>Power-down states in Deep-sleep mode</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NOTUSED0</name>
|
|
<description>Reserved. Always write these bits as 111.</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD power-down control in Deep-sleep mode, see Table 40.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED1</name>
|
|
<description>Reserved. Always write these bits as 11.</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator power control in Deep-sleep mode, see Table 40.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED2</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED3</name>
|
|
<description>Reserved. Always write these bits as 000.</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED4</name>
|
|
<description>Reserved. Always write these bits as 11.</description>
|
|
<bitRange>[12:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:13]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDAWAKECFG</name>
|
|
<description>Power-down states after wake-up from Deep-sleep mode</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000EDF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output wake-up configuration</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC_PD</name>
|
|
<description>IRC oscillator power-down wake-up configuration</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PD</name>
|
|
<description>Flash wake-up configuration</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD wake-up configuration</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PD</name>
|
|
<description>ADC wake-up configuration</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>System oscillator wake-up configuration</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator wake-up configuration</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL wake-up configuration</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED0</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED1</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED2</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED3</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED4</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED5</name>
|
|
<description>Reserved. Always write these bits as 111.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDRUNCFG</name>
|
|
<description>Power-down configuration register</description>
|
|
<addressOffset>0x238</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000EDF0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IRCOUT_PD</name>
|
|
<description>IRC oscillator output power-down</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRC_PD</name>
|
|
<description>IRC oscillator power-down</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PD</name>
|
|
<description>Flash power-down</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOD_PD</name>
|
|
<description>BOD power-down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PD</name>
|
|
<description>ADC power-down</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSOSC_PD</name>
|
|
<description>System oscillator power-down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDTOSC_PD</name>
|
|
<description>Watchdog oscillator power-down</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSPLL_PD</name>
|
|
<description>System PLL power-down</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<enumeratedValues>
|
|
<name>ENUM</name>
|
|
<enumeratedValue>
|
|
<name>POWERED</name>
|
|
<description>Powered</description>
|
|
<value>0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>POWERED_DOWN</name>
|
|
<description>Powered down</description>
|
|
<value>1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED0</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED1</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED2</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED3</name>
|
|
<description>Reserved. Always write this bit as 1.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED4</name>
|
|
<description>Reserved. Always write this bit as 0.</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>NOTUSED5</name>
|
|
<description>Reserved. Always write these bits as 111.</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICE_ID</name>
|
|
<description>Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L.</description>
|
|
<addressOffset>0x3F4</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEID</name>
|
|
<description>Part ID numbers for LPC111x 0x041E 502B; 0x2516 D02B = LPC1111FHN33/101 0x2516 D02B = LPC1111FHN33/102 0x0416 502B; 0x2516 902B = LPC1111FHN33/201 0x2516 902B = LPC1111FHN33/202 0x042D 502B; 0x2524 D02B = LPC1112FHN33/101 0x2524 D02B = LPC1112FHN33/102 0x0425 502B; 0x2524 902B = LPC1112FHN33/201 0x2524 902B = LPC1112FHN33/202 0x2524 902B = LPC1112FHI33/202 0x0434 502B; 0x2532 902B = LPC1113FHN33/201 0x2532 902B = LPC1113FHN33/202 0x0434 102B; 0x2532 102B = LPC1113FHN33/301 0x2532 102B = LPC1113FHN33/302 0x0434 102B; 0x2532 102B = LPC1113FBD48/301 0x2532 102B = LPC1113FBD48/302 0x0444 502B; 0x2540 902B = LPC1114FHN33/201 0x2540 902B = LPC1114FHN33/202 0x0444 102B; 0x2540 102B = LPC1114FHN33/301 0x2540 102B = LPC1114FHN33/302 0x2540 102B = LPC1114FHI33/302 0x0444 102B; 0x2540 102B = LPC1114FBD48/301 0x2540 102B = LPC1114FBD48/302 0x2540 102B = LPC11D14FBD100/302</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI1</name>
|
|
<baseAddress>0x40058000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIO0</name>
|
|
<description>GPIO0</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO0</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>Port n data register for pins PIOn_0 to PIOn_11</description>
|
|
<addressOffset>0x3FFC</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x00000000</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA0</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA1</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA2</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA3</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA4</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA5</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA6</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA7</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA8</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA9</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA10</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>DATA11</name>
|
|
<description>Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIR</name>
|
|
<description>Data direction register for port n</description>
|
|
<addressOffset>0x8000</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IO0</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO1</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO2</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO3</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO4</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO5</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO6</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO7</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO8</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO9</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO10</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IO11</name>
|
|
<description>Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IS</name>
|
|
<description>Interrupt sense register for port n</description>
|
|
<addressOffset>0x8004</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISENSE0</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE1</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE2</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE3</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE4</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE5</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE6</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE7</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE8</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE9</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE10</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ISENSE11</name>
|
|
<description>Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IBE</name>
|
|
<description>Interrupt both edges register for port n</description>
|
|
<addressOffset>0x8008</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IBE0</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE1</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE2</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE3</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE4</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE5</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE6</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE7</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE8</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE9</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE10</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IBE11</name>
|
|
<description>Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOnIEV. 1 = Both edges on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IEV</name>
|
|
<description>Interrupt event register for port n</description>
|
|
<addressOffset>0x800C</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IEV0</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV1</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV2</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV3</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV4</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV5</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV6</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV7</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV8</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV9</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV10</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>IEV11</name>
|
|
<description>Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOnIS (see Table 109), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOnIS (see Table 109), rising edges or HIGH level on pin PIOn_x trigger an interrupt.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<description>Interrupt mask register for port n</description>
|
|
<addressOffset>0x8010</addressOffset>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK0</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK1</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK2</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK3</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK4</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK5</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK6</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK7</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK8</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK9</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK10</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK11</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw interrupt status register for port n</description>
|
|
<addressOffset>0x8014</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RAWST0</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST1</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST2</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST3</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST4</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST5</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST6</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST7</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST8</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST9</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST10</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RAWST11</name>
|
|
<description>Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>Masked interrupt status register for port n</description>
|
|
<addressOffset>0x8018</addressOffset>
|
|
<access>read-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK0</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK1</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK2</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK3</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK4</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK5</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK6</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK7</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK8</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK9</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK10</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>MASK11</name>
|
|
<description>Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IC</name>
|
|
<description>Interrupt clear register for port n</description>
|
|
<addressOffset>0x801C</addressOffset>
|
|
<access>write-only</access>
|
|
<resetValue>0x00</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR0</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR1</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR2</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR3</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR4</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR5</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR6</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR7</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR8</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR9</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR10</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>CLR11</name>
|
|
<description>Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x.</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>RESERVED</name>
|
|
<description>Reserved</description>
|
|
<bitRange>[31:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
|
|
|
|
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO0">
|
|
<name>GPIO1</name>
|
|
<baseAddress>0x50010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO1</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO0">
|
|
<name>GPIO2</name>
|
|
<baseAddress>0x50020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO2</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO0">
|
|
<name>GPIO3</name>
|
|
<baseAddress>0x50030000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xFFFFFF</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>GPIO3</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|